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Segger embOS-MPU Manual

Real-time operating system
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embOS-MPU
Real-Time Operating System
CPU & Compiler specifics for Cortex-
M using IAR Embedded Workbench
Document: UM01065
Software Version: 5.8.2.1
Revision: 0
Date: February 3, 2020
A product of SEGGER Microcontroller GmbH
www.segger.com

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Summary of Contents for Segger embOS-MPU

  • Page 1 Real-Time Operating System CPU & Compiler specifics for Cortex- M using IAR Embedded Workbench Document: UM01065 Software Version: 5.8.2.1 Revision: 0 Date: February 3, 2020 A product of SEGGER Microcontroller GmbH www.segger.com...
  • Page 2 While the information herein is assumed to be accurate, SEGGER Microcontroller GmbH (SEG- GER) assumes no responsibility for any errors or omissions. SEGGER makes and you receive no warranties or conditions, express, implied, statutory or in any communication with you. SEGGER specifically disclaims any implied warranty of merchantability or fitness for a particular purpose.
  • Page 3 Chapter “MPU support” updated. 5.8.2.0 200106 Chapter “MPU support” updated. 5.8.0.0 191030 New software version. 5.02 180629 New software version. 4.30 161202 New software version. 4.26.1 160928 First version. 4.26 160908 embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...
  • Page 4 Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...
  • Page 5 Comments in program examples. Sample comment Reference to chapters, sections, tables and figures or other doc- Reference uments. GUIElement Buttons, dialog boxes, menu names, menu commands. Emphasis Very important sections. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...
  • Page 6 Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 7: Table Of Contents

    Interrupt-stack switching ................31 Zero latency interrupts ................. 31 Interrupt priorities ..................31 Interrupt nesting ..................32 Interrupt handling API .................. 34 CMSIS ......................... 39 The generic CMSIS start project ..............40 embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...
  • Page 8 Cortex-M XN bit (Execute Never) ..............51 9.12 Further information ..................51 RTT and SystemView ....................52 10.1 SEGGER Real Time Transfer .................53 10.2 SEGGER SystemView .................. 54 Technical data ......................55 11.1 Memory requirements ................. 56 embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 9: Using Embos

    Chapter 1 Using embOS This chapter describes how to start with and use embOS. You should follow these steps to become familiar with embOS. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 10: Installation

    IDE, it may be used without the IDE using batch files or a make utility without any problem. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 11: First Steps

    For additional information you should open the ReadMe.txt file which is part of every specific project. The ReadMe file describes the different configurations of the project and gives additional information about specific hardware settings of the supported eval boards, if required. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 12: The Example Application Os_Startledblink.c

    // Initialize required hardware BSP_Init(); // Initialize LED ports OS_TASK_CREATE(&TCBHP, "HP Task", 100, HPTask, StackHP); OS_TASK_CREATE(&TCBLP, "LP Task", 50, LPTask, StackLP); OS_Start(); // Start embOS return /*************************** End of file ****************************/ embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 13: Stepping Through The Sample Application

    Step through it to see what is done. OS_Start() should be the last line in main(), because it starts multitasking and does not return. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...
  • Page 14 As OS_Start() is part of the embOS library, you can step through it in disassembly mode only. Click GO, step over OS_Start(), or step into OS_Start() in disassembly mode until you reach the highest priority task. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...
  • Page 15 You will arrive there when you step into the OS_TASK_Delay() function in disassembly mode. OS_Idle() is part of RTOSInit.c. You may also set a breakpoint there before step- ping over the delay in LPTask(). embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...
  • Page 16 As can be seen by the value of embOS timer variable OS_Global.Time, shown in the Watch window, HPTask() continues operation after expiration of the 50 system tick delay. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 17: Build Your Own Application

    Chapter 2 Build your own application This chapter provides all information to set up your own embOS project. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 18: Introduction

    CPU. You may have to modify OS_InitH- W(), OS_COM_Init(), the interrupt service routines for embOS system timer tick and com- munication to embOSView and the low level initialization. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 19: Libraries

    Chapter 3 Libraries This chapter includes CPU-specific information such as CPU-modes and available libraries. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 20: Naming Conventions For Prebuilt Libraries

    Note Up to V5.02 of embOS-MPU for Cortex-M and IAR, the workaround for ARM erra- tum 837070 was applied by default for ARMv7-M devices. Starting with V5.8.0.0, the workaround is no longer applied by default. If libraries including the workaround are desired, a suitable set of libraries is provided, but projects would need to be updated accordingly.

  • Page 21: Cpu And Compiler Specifics

    Chapter 4 CPU and compiler specifics embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 22: Standard System Libraries

    IAR compiler V8.10 and newer To enable the automatic thread-safe locking functions, the source module xmtx.c which is included in every CPU specific Setup folder of the embOS shipment has to be included in embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...
  • Page 23 Note that thread-safe system library, file i/o and C++ dynamic lock support is required only when non-thread-safe functions are called from multiple tasks, or thread-local storage is used in multiple tasks. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 24: Thread-Local Storage Tls

    OS_STACKPTR StackHP[128], StackLP[128]; // Task stacks static OS_TASK TCBHP, TCBLP; // Task control blocks static void HPTask(void) { OS_TASK_SetContextExtensionTLS(); while (1) { errno = 42; // errno specific to HPTask embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...
  • Page 25 // errno not specific to any task OS_Init(); // Initialize embOS OS_InitHW(); // Initialize required hardware OS_TASK_CREATE(&TCBHP, "HP Task", 100, HPTask, StackHP); OS_TASK_CREATE(&TCBLP, "LP Task", 50, LPTask, StackLP); OS_Start(); // Start embOS return embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 26: Arm Erratum 837070

    ARM erratum 837070 ARM erratum 837070 Up to V5.02 of embOS-MPU for Cortex-M and IAR the workaround for ARM erratum 837070 was applied by default for ARMv7-M devices. Starting with V5.8.0.0, the workaround is no longer applied by default. If libraries including the workaround are desired, a suitable set of libraries is provided, but projects would need to be updated accordingly.

  • Page 27: Stacks

    Chapter 5 Stacks This chapter describes how embOS uses the different stacks of the Cortex-M CPU. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 28: Task Stack For Cortex-M

    OS_STACK_SetCheckLimit() and by default is configured at 70 percent of the total stack size. This will impact the minimum size requirement for both task stacks and the CSTACK. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 29: Interrupts

    The Cortex-M core comes with a built-in vectored interrupt controller which supports up to 240 external interrupt sources. The real number of interrupt sources depends on the specific target CPU. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 30: What Happens When An Interrupt Occurs

    Note Some older BSPs used to name the PendSV ISR OS_Exception() and thus need to rename it to PendSV_Handler(). embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 31: Interrupt-Stack Switching

    This is done for efficiency reasons. Basically the define OS_IPL_DI_DEFAULT in RTOS.h and the RTOS.s file must be modified. There might be other modifications necessary. Please contact the embOS support if you like to change this threshold. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 32: Interrupt Nesting

    For any interrupt handler, the user may decide indi- vidually whether this interrupt handler may be preempted or not by choosing the prologue function. 6.7.1 OS_INT_Enter() Description Disables nesting. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...
  • Page 33 _Systick(void) { OS_INT_EnterNestable(); // Inform embOS that interrupt code is running OS_HandleTick(); // Can be interrupted by higher priority interrupts OS_INT_LeaveNestable(); // Inform embOS that interrupt handler is left embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 34: Interrupt Handling Api

    RAM vector table address. RAMVectorTableBaseAddr Additional information This function must be called before OS_ARM_EnableISR(), OS_ARM_InstallISRHandler(), OS_ARM_DisableISR(), OS_ARM_ISRSetPrio() can be called. Example void OS_InitHW(void) { OS_ARM_ISRInit(1u, 82, (OS_ISR_HANDLER**)__Vectors, (OS_ISR_HANDLER**)pRAMVectTable); OS_ARM_InstallISRHandler(OS_ISR_ID_TICK, OS_Systick); OS_ARM_ISRSetPrio(OS_ISR_ID_TICK, 0xE0u); OS_ARM_EnableISR(OS_ISR_ID_TICK); embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...
  • Page 35 Flash. OS_ARM_InstallISRHandler() copies the vector table from Flash to RAM when it is called for the first time and RAM vector table is enabled. Example void OS_InitHW(void) { OS_ARM_ISRInit(1u, 82, (OS_ISR_HANDLER**)__Vectors, (OS_ISR_HANDLER**)pRAMVectTable); OS_ARM_InstallISRHandler(OS_ISR_ID_TICK, OS_Systick); OS_ARM_ISRSetPrio(OS_ISR_ID_TICK, 0xE0u); OS_ARM_EnableISR(OS_ISR_ID_TICK); embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...
  • Page 36 0 for the first entry in the vector table. The first peripheral index therefore has the ISRIndex 16, because the first peripheral interrupt vector is located after the 16 generic vectors in the vector table. This differs from index values used with CMSIS. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...
  • Page 37 0 for the first entry in the vector table. The first peripheral index therefore has the ISRIndex 16, because the first peripheral interrupt vector is located after the 16 generic vectors in the vector table. This differs from index values used with CMSIS. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...
  • Page 38 The function can be called to set the priority for all interrupt sources, regardless of whether embOS is used or not in the specified interrupt handler. Note that interrupt handlers run- ning on priorities from 127 or higher must not call any embOS function. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 39: Cmsis

    As SEGGER is one of the CMSIS partners, embOS for Cortex-M is fully CMSIS compliant. embOS comes with a generic CMSIS start project which should run on any Cortex-M3 CPU.

  • Page 40: The Generic Cmsis Start Project

    SystemCoreClockUpdate(). • SystemInit(): The system init function is delivered by the vendor specific CMSIS library and is normally called from the reset handler in the startup code. The system init embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 41: Cmsis Generic Functions Needed For Embos With Cmsis

    CMSIS files for the specific CPU may be added to the project without any modification on existing files. Note that the OS_InitHW() function in the RTOSInit file ini- embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...
  • Page 42 (8 - __NVIC_PRIO_BITS). In any case, half of the priorities with lower values (from zero) are high priorities which must not be used with any interrupt handler using embOS functions. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 43: Interrupt And Exception Handling With Cmsis

    31 and Interrupt nesting on page 32, about the differences between interrupt priority and ID values used to setup the NVIC controller, please refer to Different interrupt priority values on page 42. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 44: Vfp Support

    Chapter 8 VFP support embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 45: Vector Floating Point Support

    Using the VFP in interrupt service routines does not require any additional functions to save and restore the VFP registers. The VFP registers are automatically saved and restored by the hardware. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 46: Mpu Support

    Chapter 9 MPU support This section describes the optional Memory Protection Unit (MPU). embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 47: Introduction

    MPU in your application. This is automatically handled by embOS. Supervisor call embOS-MPU needs a safe way to switch from an unprivileged task to the privileged OS. With Cortex-M this is done via the SVC call. A SVC exception handler is necessary to handle the SVC call.

  • Page 48: Memory Attributes

    OS_ARM_CACHEMODE_WRITE_BACK_NO_ALLOC cate Outer and Inner Non-cacheable OS_ARM_CACHEMODE_NON_CACHEABLE Outer and Inner Write-Back, Write and OS_ARM_CACHEMODE_WRITE_BACK_ALLOC Read-Allocate Example: void HPTask(void) { OS_MPU_AddRegion(&TCBHP, (OS_U32)MyQBuffer, 512, OS_MPU_READWRITE, OS_ARM_CACHEMODE_WRITE_BACK_ALLOC); OS_MPU_SwitchToUnprivState(); while (1) { DoSomething() OS_TASK_Delay(10), embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 49: Cache Maintenance

    Example: void PrivTask(void) { OS_MPU_ExtendTaskContext(); SetMPURegsiter(); // Program MPU/cache settings OS_Delay(1); // Force a re-schedule which enables the MPU while (1) { embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 50: Os_Mpu_Extendtaskcontext()

    • Enable the MPU • Enable data and instruction cache (only when cache is available) MPU types embOS-MPU supports different MPU implementations with and without cache. These defines can be used with OS_MPU_EnableEx(). OS_MPU_Enable() uses OS_ARMv7M_MPU_API. Core Define ARMv7-M (Cortex-M0+/M3/M4/M4F)

  • Page 51: Cortex-M Xn Bit (Execute Never)

    9.12 Further information Please refer to the MPU chapter in the generic embOS manual. It describes the general embOS-MPU usage. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 52: Rtt And Systemview

    Chapter 10 RTT and SystemView This chapter contains information about SEGGER Real Time Transfer and SEGGER Sys- temView. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 53: Segger Real Time Transfer

    10.1 SEGGER Real Time Transfer SEGGER’s Real Time Transfer (RTT) is the new technology for interactive user I/O in em- bedded applications. RTT can be used with any J-Link model and any supported target processor which allows background memory access.

  • Page 54: Segger Systemview

    10.2 SEGGER SystemView SEGGER SystemView is a real-time recording and visualization tool to gain a deep under- standing of the runtime behavior of an application, going far beyond what debuggers are offering. The SystemView module collects and formats the monitor data and passes it to RTT.

  • Page 55: Technical Data

    Chapter 11 Technical data This chapter lists technical data of embOS used with Cortex-M CPUs. embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

  • Page 56: Memory Requirements

    Note that the sizes depend on selected embOS library mode. embOS resource RAM [bytes] Task control block Software timer Mutex Semaphore Mailbox Queue Task event Event object embOS-MPU for Cortex-M and IAR © 2010-2020 SEGGER Microcontroller GmbH...

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