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IC BLOCK DIAGRAM & DESCRIPTION
IC902 IC78601RE (ANALOG SIGNAL PROCESSOR)
No.
Pin Name Function
It is junction in unused time, 0 V defect detecting signal (DEF) input
1
DEF1
terminal
2
3V / *5V
It is 5 V use 3 V use, L H power supply voltage selection input terminal.
The phase comparison output terminal for outside VCO control(PLL
3
PDO
control)
Earth terminal for internal organs VCO control , connecting it to 0 V by
4
VVss
all means
Resistance connection terminal for electric current adjustment of PDO
5
ISET
output
6
VVdd
Power supply terminal for internal VCO control
7
FR
VCO frequency range adjustment control
8
Vss
Digital series earth terminal. Being connected to 0 V by all means.
9
EFMO
EFM signal output terminal.(Slice level control )
10
EFMIN
EFM signal input terminal.(Slice level control )
11
TMOD
Input terminal for a test. (Being connected to 0 V by all means)
12
CLV
The output terminal for disk motor control. 3 value output
13
HFL
Truck detecting signal input terminal.
14
TES
Tracking error signal input terminal.
15
TOFF
Tracking OFF output terminal
16
TGL
The output terminal for tracking gain change. (Go up gain with L)
17
JP
The output terminal for tracking jump control. (3 value output)
18
LASER
Laser control terminal. (The pull-down resistor internal )
19
FSTA
The FS TA control terminal. (The pull-down resistor internal )
20
EFBAL
EFBAL control terminal. (The pull-down resistor internal )
21
SP8
SP 8 control terminal. (The pull-down resistor internal )
22
Vdd
Digital series power supply terminal
The synchronising signal search output terminal. When synchronising
23
FSEQ
signal of inside creation agreed with the synchronising signal which
detected it from EFM signal, it become "H"
Clock monitor terminal for EFM data reproduction. ( Limited at the time
24
PCK
of test mode but)
25
SLOF
Thread OFF control output terminal
26
SLED+
The thread field output terminal
27
SLED-
The thread field output terminal
28
PUIN
Limit switch sensing input terminal. (The pull-up resister internal )
29
DOUT
Digital OUT output terminal. (EIAJ format)
30
NC
NC (Being open)
31
*SEG8
The segment output (8) terminal. (The pull-up resister internal )
32
*SEG7
The segment output (7) terminal. (The pull-up resister internal )
No.
PIN NAME
Function
33
*SEG6
The segment output (6) terminal. (The pull-up resister internal )
34
*SEG5
The segment output (5) terminal. (The pull-up resister internal )
35
*SEG4
The segment output (4) terminal. (The pull-up resister internal )
36
*SEG3
The segment output (3) terminal. (The pull-up resister internal )
37
*SEG2
The segment output (2) terminal. (The pull-up resister internal )
38
*SEG1
The segment output (1) terminal. (The pull-up resister internal )
39
Vcc
Digital series earth terminal. (It is connection in 0 V by all means)
40
NC
NC
41
*DIG2
The common drive output (2) terminal.The pull-up resister internal
42
*DIG1
The common drive output (1) terminal.The pull-up resister internal
Program movement monitor output terminal. (The pull-up resister
43
*PROG
internal )
44
*KEYIN
Key matrix input terminal. (The pull-up resister internal )
45
NC
NC (Being open)
46
NC
NC (Being open)
47
*RANDOM Random mode display output terminal
48
RMTSL3
The wireless remote controller identification input (3) terminal
49
EFLG
C1 , C2 , 1 fold , 2fold Correction monitor
7.35KHz synchronizing signal output terminal which did dividing from
50
FSX
OSC. As a condition, Limited at the time of test mode
51
*AMUTE
audio , Mute output signal
52
REMOTE
Wireless remote controller signal input terminal
53
RMTSL2
Wireless remote controller identification input(2) terminal
54
LCHO
D/A , L channel output terminal
55
L/R Vdd
D/A control power source terminal
56
L/RVss
D/A control earth terminal. (It is connection in 0 V by all means)
57
RCHO
D/A, R channel output terminal
58
CLOSE
Closing switch sensing input terminal. The pull-up resister internal
Wireless remote controller identification input(1) terminal. (The pull-up
59
RMTSL1
resister internal )
60
Xout
Connection terminal of 16.9344 MHz crystal OSC
61
Xin
Connection terminal of 16.9344 MHz crystal OSC
62
XVdd
Power supply terminal for crystal OSC
63
*RES
Reset input terminal
64
DRF
DRF input terminal
- 10 -
SCHEMATIC DIAGRAM (TUNER)
This is a basic schematic diagram.
- 11 -
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