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Circuit Diagrams and PWB Layouts
10-5-3
B03A, Class-D & muting
Class-D & muting
B03A
+3V3D
+3V3D
I425
3
D_RESET
5
7401-2
I420
PUMH2
4
6
POWER_DOWN
2
7401-1
PUMH2
1
F407
A_STBY
2401
I404
47n
2400
F409
MUTE
2404
3406
470R
7402
SI2304
+3V3STBY
+3V3_AUDIO
3
2
3426
6400
2471
+12VS
1K0
PDZ2.7B(COL)
1n0
F405
F408
5416
+3V3D
+3V3_AUDIO
30R
RES 5417
+3V3_SW
30R
L12M3.1L LA
10.
+VSND
*
*
*
*
*
3411
+3V3D
1R0
3412
+3V3D
1R0
15K
3404
+3V3D
RES
3419
15K
AOLRCK
20
LRCLK
AOBCK
21
SCLK
15
AOMCLK
MCLK
AOSDATA0
22
SDIN
SDA
3402
47R
23
SDA
SCL
3403
47R
24
SCL
14
A_SEL
D_RESET
25
RESET
19
PDN
11
P
10
PLL_FLT
M
4401
8
PBTL
3405
6
470R
SSTIMER
I405
4n7
26
STEST
2n2
I407
12
VR_ANA
18
VR_DIG
31
2402
VREG
50
47n
51
2403
I406
52
53
4n7
54
2405
55
VIA
56
10u
57
I408
2406
58
59
I409
100n
2407
100n
GND_PLL
EN 72
*
*
*
*
*
1
OUT_A
4
I410
2408
33n
BST_A
43
I411
2409
33n
BST_B
7400
46
TAS5731PHP
OUT_B
39
OUT_C
42
I412
2410
33n
BST_C
33
I413
2462
33n
BST_D
36
OUT_D
16
I414
3407
18K2
OSC_RES
32
GVDD_OUT
5
7
RES
3420
22K
40
NC
41
44
45
60
61
62
I424
63
64
VIA
65
66
67
68
69
F410
GND_PLL
back to
2013-Jun-21
div. table
F416
5400
5414
SPEAKER_L+
30R
10u
I421
SPEAKER_L+
SPEAKER_L-
5401
5406
F417
SPEAKER_L-
10u
30R
3408
2419
18R
I422
330p
SPEAKER_R+
F418
5402
5415
SPEAKER_R+
10u
30R
SPEAKER_R-
I423
2421
330p
5403
5408
SPEAKER_R-
10u
30R
SPDIF_OUT
PCB SB SSB
MT5396 R2 LATAM 2K13
B03A
F401
1D01
F403
Left+
1
Left-
2
Right+
3
Right-
4
F404
2041145-4
F402
+3V3_SW
SPDIF
F413
1D03
2460
2
VCC
3421
100n
F406
1
VIN
33R
F414
3
GND
MT
4 5
1
2013-01-11
3139 123 6544
19510_502_130411.eps
130411
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