Ic Pin Function Description - Sony STR-DA3000ES Service Manual

STR-DA3000ES

6-58. IC PIN FUNCTION DESCRIPTION

• DIGITAL BOARD IC2121 LC89056W-E (DIGITAL AUDIO INTERFACE RECEIVER)
Pin No. Pin Name
1 DISEL
2
DOUT
3 DIN0
4, 5
DIN1,DIN2
6
D. GND
7 DVDD
8
R
9
VIN
10 LPF
11
AVDD
12
AGND
13
CKOUT
14 BCK
15 LRCK
16 DATAO
17 XSTATE
18 DGND
19 DVDD
20 XMCK
21 XOUT
22 XIN
23 EMPHA
24 AUDIO
25 CSFLAG
F0/P0/C0 to
26 to 29
F3/P3/C3
30 DVDD
31 DGND
32 AUTO
33 BPSYNC
34
ERROR
35 DO
36 DI
37 CE
38 CLK
39 XSEL
40, 41
MODE0, MODE1
42 DGND
43 DVDD
44, 45
DOSEL0, DOSEL1
46 CKSEL0
47 CKSEL1
48 XMODE
92
I/O
I
Selection signal input terminal of data input terminal Fixed at "L" in this set
O
Digital data output to the external output terminal Not used
I Digital data input from the external input terminal
I
Digital data input from the external input terminal Fixed at "L" in this set
—
Ground terminal (for digital)
— Power supply terminal (+3.3V) (for digital)
I
Input terminal for VCO gain control
I
Input terminal for VCO free-run frequency setting
O PLL loop filter setting terminal
—
Power supply terminal (+3.3V) (for analog)
—
Ground terminal (for analog)
O
Audio clock signal output to the selector
O Bit clock signal (2.8224 MHz) output to the digital signal processor and A/D converter
O
L/R sampling clock signal (44.1 kHz) output to the digital signal processor and A/D converter
O
Audio serial data output to the digital signal processor and main system controller
O
Source clock selection monitor output to the main system controller
— Ground terminal (for digital)
—
Power supply terminal (+3.3V) (for digital)
O
System clock signal (12.288 MHz) output to the A/D converter
O
System clock output terminal (12.288 MHz) Not used
I System clock input terminal (12.288 MHz)
O
Channel status emphasis information output terminal Not used
O
Channel status bit 1 output to the digital signal processor
O Channel status head 40 bit renewal flag output terminal Not used
O Output terminal of input frequency calculation result Not used
—
Power supply terminal (+3.3V) (for digital)
—
Ground terminal (for digital)
O Not used
O
Non-PCM burst preamble sync signal output terminal Not used
PLL lock error signal and data error flag output to the digital signal processor and main system
O
controller
O
Read data output to the main system controller
I
Write data input from the main system controller
I Chip enable signal input from the main system controller
I
Clock signal input from the main system controller
I
Selection signal input terminal of crystal oscillator frequency Fixed at "H" in this set
I Mode setting terminal Fixed at "L" in this set
—
Ground terminal (for digital)
—
Power supply terminal (+3.3V) (for digital)
I
Output data format selection signal input terminal Fixed at "L" in this set
I Output clock selection signal input terminal Fixed at "L" in this set
I
Output clock selection signal input from the main system controller
I
System reset signal input from the main system controller "L": reset
Description