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- SBAS (USA: WAAS, Europe: EGNOS, Japan: MSAS, India: GAGAN) Thus FURUNO is not liable for the degradation of the above systems so therefore FURUNO cannot guarantee specification based on their conditions. By solar flare or coronal mass ejection due to solar surface activity, depending on the scale, there is a possibility that a decrease in reception sensitivity or deterioration in precision may be temporarily observed.
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GF-8801, GF-8802, GF-8803 Hardware Specifications SE19-410-006-00 Revision History Version Change contents Date Initial release 2019.4.18...
GF-8801, GF-8802, GF-8803 Hardware Specifications SE19-410-006-00 1 Outline This document describes the hardware specifications of GF-8801, GF-8802 and GF-8803 which is the GNSS Disciplined Oscillator (GNSSDO). This document uses GNSS as general term of GPS, GLONASS, Galileo and QZSS. 2 Function Overview This product is a GNSSDO that can provide PVT (Position, Velocity and Time) information.
GF-8801, GF-8802, GF-8803 Hardware Specifications SE19-410-006-00 3 GNSS General Performance These performances are measured and evaluated under the environment shown in Figure 3-1. The measurement conditions are default setting and 25°C constant (no wind). When the signal level mask is set, the performance is limited by the mask.
GF-8801, GF-8802, GF-8803 Hardware Specifications SE19-410-006-00 4 1PPS and Clock (VCLK, GCLK) Signal Specifications The follow is the specifications of 1PPS and clock (GCLK, VCLK). Please refer to the eSIP Protocol Specification for switching setting etc. The performance described in this chapter is measured and evaluated under the environment shown in Figure 4-1 and 4-2 below.
[*5] MTIE of G.8272 PRTC-B compliant means that it meets the following specifications. Observation interval τ [sec] MTIE limit [nsec] 0.275τ + 25 1<τ<55 55<τ G.8272 PRTC-B compliant [*6] is GF-8802 and GF-8803 only. TDEV and MTIE of GF-8801 is G.8272 PRTC-A compliant.
GF-8801, GF-8802, GF-8803 Hardware Specifications SE19-410-006-00 5 Time to FINE LOCK This product transitions to FINE LOCK for GPS time within 5 minutes from power on. However, the conditions are constant temperature and open sky. Otherwise, the time to FINE LOCK may be extended.
GF-8801, GF-8802, GF-8803 Hardware Specifications SE19-410-006-00 9 I/O Signal Description 9.1 I/O Signal Description Table 9.1-1. I/O signal description Pin name Type PU/PD [*1] Note RST_N Digital input External reset input pin [*2] VANT Power supply input pin for antenna...
GF-8801, GF-8802, GF-8803 Hardware Specifications SE19-410-006-00 9.2 Pin Arrangement #RF⇒ Figure 9.2-1. Top of view 9.3 Alarm Signal (ALM_N) It shows the status of “alarm” field in CRZ (TPS4) sentence. The alarm signal specification is shown in Table 9.3-1. Table 9.3-1. Alarm signal specifications...
GF-8801, GF-8802, GF-8803 Hardware Specifications SE19-410-006-00 9.5 PPS Input Signal for External Synchronization (EPPS) When 1PPS is input to the EPPS pin and the command is set up, the VCLK and the PPS will be synchronized with the pulse. The synchronous target is the rising edge of the pulse to be input to the EPPS. Please refer to the “EXTSYNC”...
GF-8801, GF-8802, GF-8803 Hardware Specifications SE19-410-006-00 10 Electrical Characteristics 10.1 Absolute Maximum Rating Table 10.1-1 shows the values when used in the operating temperature range shown in Chapter 7. Stresses beyond those listed under those range may cause permanent damage to the product.
GF-8801, GF-8802, GF-8803 Hardware Specifications SE19-410-006-00 10.2 Power supply Below are power supply specifications. The conditions satisfying this specification are Ta = 25 °C. Table 10.2-1. Power supply Characteristics Note Item Symbol Unit VCC supply voltage VANT supply voltage VBK supply voltage...
GF-8801, GF-8802, GF-8803 Hardware Specifications SE19-410-006-00 10.3 Reset This product has an internal power-on reset circuit which detects the VCC voltage and creates POR_N (power-on reset) signal form initializing the module. Table 10.3-1 shows the threshold voltages to detect and create POR_N signal.
GF-8801, GF-8802, GF-8803 Hardware Specifications SE19-410-006-00 10.6 UART Wake-up Timing The start timing specifications of UART input / output are described below. Figure 10.6-1 shows the UART wake-up timing by the internal reset control (without external reset). RTH_POR 1ITXD1 Valid...
GF-8801, GF-8802, GF-8803 Hardware Specifications SE19-410-006-00 18 Packaging Below is a description of the packaging. This packaging is applied only when shipping the regular lot number (100 pieces). Regarding the shipment when the number of order is less than the regular lot number, we will contact you separately.
GF-8801, GF-8802, GF-8803 Hardware Specifications SE19-410-006-00 [Exterior packaging] Interior box Attach the cushioning materials to the interior box. Cushioning material Put the interior box in the exterior box. Exterior box Close the cover with sealing tape, and attach the product label.
20.2 Electronic Component Components in this product are planned to be purchased from multiple manufacturers / vendors according to FURUNO’s procurement policy. Therefore, multiple components from multiple manufacturers / vendors may be used even in the same production lot. 20.3 Precautions at Mounting (1) This product contains semiconductor inside.
GF-8801, GF-8802, GF-8803 Hardware Specifications SE19-410-006-00 20.4 Precautions on Industrial Property Rights (1) Since this document includes our copyrights and know-how, do not use it for any purpose other than the intended use of this product. Do not make any copies of this document and disclose it to any third parties without our prior consent.
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