NXP Semiconductors AN12868 Quick Start Manual
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NXP Semiconductors AN12868 Quick Start Manual

NXP Semiconductors AN12868 Quick Start Manual

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AN12868
Camera Interface in LPC55(S)xx
Rev. 3 - 07 September 2021

1 Introduction

This application note introduces a parallel interface for the camera solution for
LPC55(S)xx. It includes the introduction of camera interface, features and API
routines, and demo.

2 Target application

The camera interface can be used as important part of camera usage as below:
• Object detection
• Gesture recognition
• Color recognition
• QR code scanning, and so on

3 Introduction of camera interfaces

A typical camera interface supports at least one parallel interface, although
nowadays many camera interfaces begin to support the MIPI CSI interface.
The camera parallel interface consists of the following lines:
• Data line (D[0:11]):
These parallel data lines carry pixel data. The data transmitted on these
lines change with every Pixel Clock (PCLK).
• Horizontal Sync (HSYNC)
This is a special signal that goes from the camera sensor. An HSYNC indicates that one line of the frame is transmitted.
• Vertical Sync (VSYNC)
This signal is transmitted after the entire frame is transferred. This signal is often a way to indicate that one entire frame
is transmitted.
• Pixel Clock (PCLK)
This pixel clock changes on every pixel.
The application note only focuses on Digital-Video-Port (DVP) interface which is parallel interface.

4 Features of camera interface

• Supported formats (8-bit): RGB565
• Maximum image transfer rate: 30 fps for QVGA(320 × 240). For small RAM parts, reduce the size of image and frame
rate.
• Camera module tested: OV7673
Contents
1
Introduction......................................1
2
Target application............................1
3
4
5
Function description........................ 2
5.1
5.2
Camera driver library................... 2
5.3
LCD display..................................2
5.4
System clock................................2
5.5
Clock source of camera............... 2
2
5.6
C interface................................. 2
5.7
Memory usage............................. 2
5.8
..................................................... 2
6
Pin description.................................3
6.1
Connection of interface................ 3
6.2
7
Library and API routine................... 4
7.1
Library.......................................... 4
7.2
API routine................................... 4
7.3
API routine description.................4
7.4
Code detail description................ 4
8
Demonstration................................. 7
9
Revision history............................... 8
A
module used in this demo............... 8
Application Note

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Summary of Contents for NXP Semiconductors AN12868

  • Page 1: Table Of Contents

    AN12868 Camera Interface in LPC55(S)xx Rev. 3 — 07 September 2021 Application Note Contents 1 Introduction Introduction........1 Target application......1 This application note introduces a parallel interface for the camera solution for Introduction of camera interfaces..1 LPC55(S)xx. It includes the introduction of camera interface, features and API Features of camera interface..

  • Page 2: Function Description

    NXP Semiconductors Function description • Other camera modules can be supported as long as they provide the same signal timing. 5 Function description 5.1 Camera interface engine There is a dedicated processor in LPC55S69 which can handle the signals of camera.

  • Page 3: Pin Description

    NXP Semiconductors Pin description PCLK PCLK (Row Data) HREF Last First Last D[7:0] Byte Byte Byte First Byte Second Byte D[7] D[7] D[6] D[6] D[5] D[5] D[4] D[4] D[3] D[3] D[2] D[2] D[1] D[1] D[0] D[0] Figure 1. Camera module configuration 2.

  • Page 4: Requirement Of Interface

    NXP Semiconductors Library and API routine NOTE Use P0_16 as a clkout pin to provide clock source for the camera. 6.2 Requirement of interface • The D0-D7 must be connected to P0.0-P0.7 for byte reading the data. • SIOC and SIOD must be connected to the I C interface of MCU for configuration.
  • Page 5 NXP Semiconductors Library and API routine 7.4.1 System clock Camera engine needs short time to store the data when every pixel edge comes. If the clock frequency of engine is higher, the time cost is shorter. In this solution, the system clock must be set at 150 MHz when engine is running. The code to configure system clock is shown as below: BOARD_BootClockPLL150M();...
  • Page 6 NXP Semiconductors Library and API routine are input function pins which can receive the VSYNC and pixel signals. The Pixel clock is 1/4 of clock source, P0_13 P0_15 it is 12.5 MHz. As clock output pin, provides 50 MHz clock to camera as its clock source.

  • Page 7: Demonstration

    NXP Semiconductors Demonstration 8 Demonstration 1. Build and compile the project. 2. Plug one side of USB cable in PC USB port and another side in the debug link port in the EVK board, and then download the image in the MCU.

  • Page 8: Revision History

    NXP Semiconductors Revision history 9 Revision history Table 3. Revision history Rev. Date Description 07 September • Added purchase link for camera module in Purchasing LCD module and camera module 2021 used in this demo • Changed "coprocessor" to "dedicated processor"...
  • Page 9 Right to make changes - NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

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