Block Diagram; Main Block Diagram - Panasonic TH-32A410R Service Manual

Chassis: km26
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TH-32A410R

9 Block Diagram

9.1.

Main Block Diagram

2ndLow_IF,IFAGC
1stLow_IF IFAGC
Terrestrial(1)
Terestllial/cable(2)
cable
OPT
HDMI1
HDMI2
HK/CHINA: DTMB
Colombia/Vietnum: T2
TS-IN
HS1BCLKIN
HS1SYNCIN
HS1VALIN
HS1DIN0
S3.3
S3.3
HS1DIN1
S3.3 / TU1.8
HS1DIN2
DCDC
HS1DIN3
1.2V
HS1DIN4
HS1DIN5
DMD_IIC1 (IIC2)
HS1DIN6
IF_AGC2
HS1DIN7
Low -IF2
HS1DIN8
Demod.
< FE_XRST
Low -IF1
IF_AGC1
DMD_IIC0
or
CXD2840/2837
< FE_XRST
Terrestrial
Cross Stream Switch
DTV Decoder
VIF Decoder
ADC
SIF Decoder
Y1,Pb1,Pr1
LIN1, RIN1
Lout2,Rout2
VIO
V-SW
V1
AV2(SIDE) INPUT
CVBS)
Lin3,Rin3
AIO
A-SW
SOUND_VCC
A-Chip
ALRCKO
ASDOUT0
AMP
ABCKO
ASMCK
Optical OUT
IECOUT
ARCOUT
Rx*
DDC* > STM, Peaks
HPD* < STM
HDMI_5V_DET* > STM
Rx*
HDMI
Rx
MUX
DDC* > STM, Peaks
x3
HPD* < STM
HDMI_5V_DET* > STM
XERWE0
XERWE0
STB5/5VS
CPU BUS
XECS1
CTRL
AAR/DATA
ERXW
S5/ S3.3
ES0
BOOTSWAP
ES1
XRST
ES2
XRSTSTM
Support
< TV_SOS
ED[7:0]
AMP/HP MUTE
Card
MONITOROUT MUTE
JTAG
DTV_XRST
S3.3
B/B70: 1G
(Brazil: 2G)
BL model: 4G
NAND
S12
S12
Flash
1G
CI-IF
XNFCE,XNFW
Peaks
DC
DC
DCDC_EN
PCOE
Peaks
PCWAIT
P
DCDC
PCWE
DCDC
PCCD1
NFCLE,NFALE
VM
PCIORD
DTV_XRST >
DT
T
PCCD2
XNFWE,XNFR
JTAG
PCIOWR
PCREADY
E
SW_OFF_DET >
SW
W
PCRESET
AFB
NANDRYBY
S1.1
S1.5
S3 3 3
S3.3
PCCE1
ED[ :0]
NFD[7:0]
CPUBUS
Trans Port Decoder
NAND-IF
IIC
DMD
DMD-IIC0
P-IIC2 (For DMD only)
DMD-IIC1
Peaks
Video
Analog Video
Format
IPR INS
Processor
sLD8A
Processor
DSP
I2S
SW
A-D Chip
Internal BUS
D-Chip
DMD IIC
IIC
DMD_IIC0
P-IIC0
DMD_IIC1
P-IIC1
AMP
PWM
SPDIF
SW
CLK
GEN
25MHz
26
S9
S12/S5
(SD-Data-VCC)
S9-REG
Analog
3
3.3/1.8
3
3
3
1
1
/
/
8
8
ASIC
UHS-1
< (SDVOLC)
AN34043A
REG
STB3.3V/1.2V_REG
OVP
Safety
STB5V Reset IC (STM)
SOS
Circuit
S9V_REG
S12V Reset IC (Peaks)
Audio MUTE
< MON_MUTE
OCP/OVP/TV-SOS
< SP_HP_MUTE
HP_MUTE,EXT_MUTE
UHS-I_REG
PWM >
TV_SOS
PWM
Back Light
PWM >
BL_ON >
BL_SOS <
INVERTER
or
LED Driver
STB3.3
XRST
STB_XRST
PWMA
POWER_DET
Panel
LVDS
HD : (DATA 4pairs / CLK 1pair) single8bit
FHD: (DATA 4pairs / CLK 1pair) dual8bit
LVDS-Tx
mini-LVDS-Tx
PANEL_TEST_ON
SCL0/SDA0(B70/BL70)
DDR3
S1.5
S1.5
DDR3+(1333)
DDR3+(1333)
B7/B70: 1G+1G
DDR-IF
x16
x16
(Brazil 2G+2G)
BL7/BL70: 2G+4G
S5
USB
USB2VBUS >
USB
< USB2OC
S5
Power SW
USB Memory
S5
USB
USB2DP/N
S5
USB1VBUS >
< USB1OC
USB
USB-IF
S5
Power SW
3port
USB1DP/N
S5
S5
USB0VBUS >
< USB0OD
USB
S5
Power SW
WiFi Module
S5
USB0DP/N
Serial
LAN
P-Serial0
ETHER
P-Serial1
PHY
P-UART0
P-UART2
SD CARD
SD-IF
Only for study
STM
IIC
STM-IIC
Serial
STM-Serial0
STM-Serial1
STB3.3
<
KEY3
POWER KEY
< KEY1
CONTROL PANEL KEY

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