ARM ARM1136JF-S Application Note

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Application Note 174

Changing clocks on the ARM1136JF-S Core Module

Released on: 21 March, 2007

DAI0174A

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Summary of Contents for ARM ARM1136JF-S

Page 2 This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.
Page 3 Many customers want to increase the performance of ARM development boards to be nearer their final ASIC. For example, the ARM1136JF-S core was designed to run at 330-550MHz, but the test chip on our boards runs at a default 240MHz. Please note that we cannot guarantee the maximum operating frequency of our boards, there will be some variation between boards, and you may only be able to achieve a relatively small increase, for example to 285MHz.
Page 4 Logic Tile FPGA. Test Chip Figure 2 on page 5 shows the clock circuit inside the ARM1136JF-S test chip. The default clock frequencies, divider and multiplexer settings for a CM1136 fitted on top of an Integrator/CP are shown.
Page 5 Application Note 174 Figure 2 Clock circuit inside the ARM1136 test chip The test chip clock circuit has three parts: an analogue Phase Locked Loop (PLL) surrounded by 3 dividers that can generate arbitrary frequencies from the incoming REFCLK signal; multiplexers to bypass the PLL or select an alternative clock source for asynchronous mode;...
Page 6 • HCLKI must be an integer multiple of HCLKE. In ARM1136JF-S synchronous mode (the default), CLK must be an integer multiple of HCLKI greater than 1. •...
Page 7 Application Note 174 • All divider ratios are (register value + 1). For example, a PLLOUTDIV value of 0 means divide by 1, a value of 1 means divide by 2. • You must preserve the original values of bits you are not writing to (read-modify-write the register).
Page 8 Application Note 174 Table 3 Clock control registers (continued) Register Address Bits Parameter Description 0x3F200080 25:20 Divides the PLL output (or REFCLK if PLL ClkGenCtrlReg HCLKEDIV bypassed, or ARM_HCLK in async mode) to generate HCLKE. Maximum value is 0x3E. The divide ratio is HCLKE_DIV + 1 0x3F200080 19:14...
Page 9 Application Note 174 Measuring the Frequency If you manually set the registers you should measure the resulting frequencies to be sure you have set them correctly. You can use an oscilloscope to measure the input to the test chip (REFCLK at U32 pin 11) and the output (HCLKE at test point TP16). Figure 3 shows the test points for clocks on the CM1136.
Page 10 Application Note 174 A utility is provided with this application note so you can measure the ARM1136 core frequency. The utility comprises two stand-alone programs called InitTCM.axf and Speedtest.axf. Tightly Coupled Memory (TCM) on the ARM1136 test chip runs at the core frequency with zero wait states;...
Page 11 0x10000000 to display the Core Module control registers. The calculator program CM1136_clocks.axf calculates the register values needed for a given ARM core frequency, then sets the registers to change the frequency. Load and run the CM1136_clocks.axf program in RVD: select Target → Load Image then Debug →...
Page 12 Application Note 174 The program prompts you to enter a target ARM1136 core frequency in the range 100 to 340MHz. You can enter a number such as 233 or 233.33 but do not enter 'MHz'. The program will calculate the new register settings and prompt you to accept them. Enter 'Y' and the program will write the new values and initiate a soft reset to make the values take effect.
Page 13 Application Note 174 Software The calculator program is fairly straightforward: it prompts you to enter a target core frequency, it searches all combinations to find a core frequency closest to the target, then it searches for a suitable external bus frequency, and finally it sets the registers and initiates a soft reset. If you do not wish to use the program then replace step 7 above with the following method: Using the test chip diagram above, determine the REFCLK frequency and divider values that you want to use.