Summary of Contents for Bruker DPP1
- Page 1 Bruker BioSpin Digital Preemphasis Processor DPP1 Technical Manual Version NMR Spectroscopy think forward...
- Page 2 Copyright © by Bruker BioSpin NMR GmbH All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form, or by any means without the prior consent of the publisher. Product...
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Page 3: Table Of Contents
Contact for Technical Assistance ............7 Installation and Handling ........... 9 Product Requirements and Handling ........... 9 PCI Requirements ................9 Handling .................... 9 Mounting the DPP1 PCI Board ............10 Booting the DPP1 ................10 Ports ....................11 Connectors ...................12 Currents and Voltages ..............12 Reference Numbers ............ - Page 4 Functional Coordination between the Hardware and Software .. 45 Serial Gradient Cycle, Serial Processing by the DSP ....46 Description ................47 Description ................48 Engineering Design ................49 Dimensions ................49 JTAG Structure ................ 49 Figures ................51 Tables ................53 BRUKER BIOSPIN Technical Manual Version 001...
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Page 5: Introduction
DPP1, as well as other detailed technical specifications and information. The DPP1, is a standard PCI expansion card. It modifies the data stream sent by the gradient controller (G–Controller) to the gradient amplifier. The DPP1 is super- vised by a software driver running under LINUX and has to be mounted in an PCI environment (see "Installation and Handling"... -
Page 6: Disclaimer
The DPP1 should only be used for its intended purpose as described in this man- ual. Use of the DPP1 for any purpose other than that for which it is intended is tak- en only at the users own risk and invalidates any and all manufacturer warranties. -
Page 7: Special Safety Symbols
Intended Use The DPP1 is to be used only in a PCI environment and with Bruker AVANCE III spectrometers for the modification of data streams sent by the gradient controller. The board is not intended for use outside of these standard parameters. - Page 8 Introduction 8 (55) BRUKER BIOSPIN Technical Manual Version 001...
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Page 9: Installation And Handling
Handling Product Requirements and Handling The DPP1 Digital Preemphasis Board is a Customer Replaceable Unit (CRU). To insert or remove the DPP1 follow the instructions in this manual. Replacing CRU‘s requires opening of the enclosure. Before doing this, the unit must be completely switched off and unplugged or disconnected and dismounted from its rack. -
Page 10: Mounting The Dpp1 Pci Board
Installation and Handling Mounting the DPP1 PCI Board The DPP1 board is intended to be mounted in a PCI environment. The driver is LI- NUX specific and will only work in an AVANCE III IPSO system. DSP firmware is loaded from the TopSpin PC via the PCI bus and Ethernet. -
Page 11: Ports
When you have entered the IP address in the browser the browser will display the “IPSO Service Web” page. Click consecutively on the following to show a list of all the controllers found as PCI devices. One of them will be the DPP1: ! Information... -
Page 12: Connectors
A word width of 48 bits. “Next Value” Clock from IPSO When installed in the “IPSO 19” the DPP1 takes the “Next Value” clock via its ST1 connector connected to ST32 of the IPSO (IMB) using the cable H5516. In the “IPSO AQS”... -
Page 13: Reference Numbers
Reference Numbers Table 3.1. Parts and Assemblies for the DPP1, H12513F1 Part Number Drawing Number Description Version H12551F2 H4P2820b PCB Layout DPP1, ECL 01 H12551F3 H4P2820c PCB Layout DPP1, ECL 02/03/04 H12536 DPP1 Programming File HZ13694 DPP Slot Bracket Table 3.2. -
Page 14: Reference Numbers
Reference Numbers 14 (55) BRUKER BIOSPIN Technical Manual Version 001... -
Page 15: Product Status And Modifications
Firmware Number Number File Setting H12513F1 DPP1 H4P2820b Program File The name of the program file includes the layout number and the EC level. Configuration and Settings Jumper Setting There are no jumpers on this board. Some configuration settings have been made using zero Ohm resistors and should not be changed. -
Page 16: Lvds Configuration
USB + USB - Firmware The firmware is loaded via PCI and Ethernet from the TopSpin PC as part of Top- Spin. The DPP1 driver is a part of the “diskless” LINUX. Modification History Table 4.3. DPP1, H12513F1 Modification History... -
Page 17: Versions
Description Versions Firmware Name Part Number EC Number Increments Number H12513 28 Bit LVDS (test version) DPP1 H12513F1 48 Bit LVDS DPP1 H12513F1 Removing NV configuration Structure Figure 5.1: DPP1 Block Diagram Technical Manual Version 001 BRUKER BIOSPIN 17 (55) -
Page 18: The Pci Interface
The DSP controls access from its host interface via the EMIF bus. The DSP mem- ory (EMIF) bus is attached to an external memory, the DPP1 control logic, and the LVDS input and output FIFO’s. The additional mailbox register attached offers the possibility of the DSP exchanging data directly with the PCI bus. -
Page 19: Lvds
Description LVDS The data from the GCNTR to the DPP1 and from the DPP1 to the gradient ampli- fier is transmitted via two serial LVDS links. The word width transmitted is 48 bit and the word transfer speed is 80 MHz. -
Page 20: Table 5.1: Word On The Lvds 48 Bit 80 Mhz Parallel Interface
There is no gradient data in this word. Parity bit, even parity, bit sum over the bits 1 to 47 (DPP only). The DPP1 is software controlled. !LAST The last word in the gradient package is marked with !NG=0 or !VALID=0;... -
Page 21: Software Interface
Base Address 4: Memory access to [31:0] FFFF 0000 h 64K range Local Bus CS2 24 h Base Address 5: Memory access to [31:0] FFFF 0000 h 64K range Local Bus CS3 28 h Not supported Technical Manual Version 001 BRUKER BIOSPIN 21 (55) -
Page 22: Pci Software Interface
BIOS using the contents in the configuration registers “base address 0...5”. The results are the PCI base addresses for the local bus chip se- lects which are written into the same configuration registers by BIOS. 22 (55) BRUKER BIOSPIN Technical Manual Version 001... -
Page 23: Table 5.3: Pci Local Bus Addresses
Values in the column “Local Address” depend on the content of the “Local Base Address Remap Registers”. Values in the column “Destination” depend on the content of the “Local Bus Chip Select Registers”. Technical Manual Version 001 BRUKER BIOSPIN 23 (55) -
Page 24: Local Bus Interface
Local Address Space 1 Range LAS1RR FFFF 0000 h 64kB Byte Local Mem- ory Space, non-prefetch Local Address Space 2 Range LAS1RR FFFF 0000 h 64kB Byte Local Mem- ory Space, non-prefetch 24 (55) BRUKER BIOSPIN Technical Manual Version 001... - Page 25 Region Descriptor NRDD 1, NWAD 1, Write Hold 1 30 h Local Address Space 2 Bus LAS2BRD 4040 8820 h 16 Bit Local Bus Width, Region Descriptor NRDD 1, NWAD 1, Write Hold Technical Manual Version 001 BRUKER BIOSPIN 25 (55)
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Page 26: Local Bus Address Map
Two byte, data bit 7...0 attached; data bit 15...8 not used; there- fore the flash prom occupies the double address area. Cycle Control: Clock controlled. Cycle Length: Approximately 85 nanoseconds for posting and 270 nanosec- onds for the reading cycle. 26 (55) BRUKER BIOSPIN Technical Manual Version 001... -
Page 27: Registers At The Local Bus
Type of Flash Proms used on the DPP Local Hex Address Size (KByte) Word (Byte) Type Type of Controller C000 0000 - C000 00FF 1 Byte DPP1 H12513F Registers at the Local Bus 5.4.6 Table 5.10: DSP HPI Register 0000 DSP HPI Control Register low word. 15–0 0002 DSP HPI Control Register high word. -
Page 28: Pipeline Register
IDLE, DPP is up but nothing to do. INPUT, DPP read from input buffer. OUTPUT, DPP write to output buffer. INTR, DPP has send Interrupt. ERROR, DPP detected error, info in mailbox. 28 (55) BRUKER BIOSPIN Technical Manual Version 001... -
Page 29: Dsp Reset
ED (7:0) side of the bus. In Big Endian mode (HD8 = 0), the 8 bit or 16 bit EMIF data will be pres- ent on the ED (31:24) side of the bus [default]. Technical Manual Version 001 BRUKER BIOSPIN 29 (55) -
Page 30: Dsp Defined Address Ranges
0190 0000 – 0193 FFFF Timer 0 Registers 256 K 0194 0000 – 0197 FFFF Timer 1 Registers 256 K 0198 0000 – 019B FFFF Interrupt Selector Registers 019C 0000 – 019C 01FF 30 (55) BRUKER BIOSPIN Technical Manual Version 001... - Page 31 EMIF CE1 256 M 9000 0000 – 9FFF FFFF EMIF CE2 256 M A000 0000 – AFFF FFFF EMIF CE3 256 M B000 0000 – BFFF FFFF Reserved C000 0000 – FFFF FFFF Technical Manual Version 001 BRUKER BIOSPIN 31 (55)
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Page 32: The Dsp External Memory Interface (Emif)
RW, + 1111 Bit15..14 Bit 13..8 Bit 7..4 Bit 3 Bit 2..0 Read strobe MTYPE Write hold MSB(1) Read hold RW, +1111 RW, +111111 RW,+ 11 RW, + 0 RW, + 011 32 (55) BRUKER BIOSPIN Technical Manual Version 001... -
Page 33: The Dsp Pll Register
(D0) and four dividers (OSCDIV1, D1, D2, D3). The PLL controller is able to generate different clocks for different parts of the system (DSP core, exter- nal memory interface and other peripherals). The picture below illustrates the PLL and clock generation logic. Technical Manual Version 001 BRUKER BIOSPIN 33 (55) -
Page 34: Figure 5.2: Pll Register Structure
Divide by 1 PLLDIV 1 0x1B7C118 0x8000 Divide by 1 PLLDIV 2 0x1B7C11C 0x8001 Divide by 2 PLLDIV 3 0x1B7C120 0x8002 Divide by 3 PLLCSR 0x1B7C100 0x40 Quit reset PLLCSR 0x1B7C100 0x41 Enable PLL 34 (55) BRUKER BIOSPIN Technical Manual Version 001... -
Page 35: Configuration Of Interrupts
DSP. The PCI controller interrupt inputs LINT1 and LINT2 are routed to the PCI connec- tor pin INT A. The PLX controller interrupt inputs are routed to the PCI bus INT A. Technical Manual Version 001 BRUKER BIOSPIN 35 (55) -
Page 36: Configuration Of The External Memory Interface (Emif)
32 bit SBRAM DSP CE 2 A0000000 Receiver reg. CE 2 FF43 FIFO Space control 180 0014 FFFF 32 bit SBRAM DSP CE 3 B000 0000 Output reg. CE 3 FF43 FIFO 36 (55) BRUKER BIOSPIN Technical Manual Version 001... -
Page 37: Description Of The Global Control Register
0 No hold is disabled. Hold request via the HOLD input are acknowledge via the HOLDA output at the earliest possible time. 1 No hold is enabled. Hold request via the HOLD input are ignored. Technical Manual Version 001 BRUKER BIOSPIN 37 (55) -
Page 38: Description Of The Global Control Register
Bit Fields for the Space Control Register 8 7 .. 4 3 2 1 0 Bits Write setup Write Write Read setup Read MTYPE Read Fields strobe hold strobe hold 1111 111111 1111 111111 0000 Res. 38 (55) BRUKER BIOSPIN Technical Manual Version 001... -
Page 39: Table 5.30: Bit Field Description
128K x 36 bit. Table 5.31: Type of External Memory Local Hex Size Word Bandwidth Type Type of Controller Identification Address [KByte] [Byte] [MByte/s] 8000 0000 – 4 Byte SRAM DPP H12513F1 subdev=??? 8007 FFFF Technical Manual Version 001 BRUKER BIOSPIN 39 (55) -
Page 40: Table 5.32: Bit Allocation At The Emif Bus
29..20 19..0 Data Bus or Logic The input FIFO and output have a size of 36 bits x 8192 words. Table 5.33: Type of FIFO‘s Used on the DPP1 Local Hex Size Word Bandwidth Type Type of Controller Identification... -
Page 41: Dsp Address Map
The control word makes the differentiated control of the logic functions possible. CNTR 9000 0000 Control Register 31-0 Table 5.36: Control Register: Bit Fields 31..9 8..6 Bits CALC REC EN SEND TIME CALC Fields allocated Error Counter Res. Technical Manual Version 001 BRUKER BIOSPIN 41 (55) -
Page 42: Table 5.37: Control Register Bit Field Description
0 = Reset Output Reset FIFO Int. 0 = Reset 0 = Reset LVDS Calculation Transmitter 0 = Reset 0 = Reset Next Value Calculation synchronisation Counter 0 = Reset Receiver FIFO 42 (55) BRUKER BIOSPIN Technical Manual Version 001... -
Page 43: Table 5.39: Information Register Bit Fields
11 0000 0000 Table 5.42: ADR Debug Register Bit Field Description Field Value Description NG_SM_ERR The phase acquisition NV clock to the LVDS clock is correct. The LV clock edge was not correctly determined. Technical Manual Version 001 BRUKER BIOSPIN 43 (55) -
Page 44: Functionality Of Devices
The „NEXT Gradient“ appears before the „NEXT VALUE“. The included gradient packet is transferred directly before or after it, so that the „Next Value“ after next is available at the FIFO output. 44 (55) BRUKER BIOSPIN Technical Manual Version 001... -
Page 45: Functional Coordination Between The Hardware And Software
• The control word is the last word of a gradient packet in both FIFO‘s. With the DPP1 the control word is transferred with the packet and is used to control the gradient amplifier. With the DPP (48-bit test version) the control word from the out FIFO serves only as a delimiter for the packets and is not transferred with the packet to the gradient amplifier. -
Page 46: Serial Gradient Cycle, Serial Processing By The Dsp
Figure 5.6: Gradient Cycle without Parallel Processor Figure 5.6: Gradient cycle without parallel processor, „g “ is transferred with maxi- mum delay in a packet with „g “ with a maximum delay to the Next Gradient. 46 (55) BRUKER BIOSPIN Technical Manual Version 001... -
Page 47: Description
Control word The control word is the last word of a gradient packet in both FIFO‘s. With the DPP1 the control word is transferred with the packet and is used to control the gradient amplifier. With the DPP (48-bit test version) the control word from the out- FIFO serves only as a delimiter for the packets and is not trans- ferred with the packet to the gradient amplifier. -
Page 48: Description
Figure 5.7: Gradient Cycle During Leading Transmission of the Gradients Sepa- rately from NG Description in-FIFO 1st out First output line of the FIFO. The DSP reads the gradient block con- tained in the gaps. 48 (55) BRUKER BIOSPIN Technical Manual Version 001... -
Page 49: Engineering Design
Figure 5.8: IPSO AQS ACQ Built from 5 TX-Controllers JTAG Structure The board has a JTAG interface with three chains that can be used for program- ming and testing. Table 5.43: JTAG Structure on the DPP1 Connector U5, Adr=0 JTAG Bridge JTAG Chains... - Page 50 Description 50 (55) BRUKER BIOSPIN Technical Manual Version 001...
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Page 51: Figures
Figure 1.1. Top View of the DPP1 ................5 2 Installation and Handling Figure 2.1. IPSO Functional Signal Flow ..............10 Figure 2.2. Ports on the Front Panel of the DPP1 ........... 11 3 Reference Numbers 4 Product Status and Modifications 5 Description Figure 5.1: DPP1 Block Diagram ................17... - Page 52 Figures 52 (55) BRUKER BIOSPIN Technical Manual Version 001...
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Page 53: Tables
Tables 1 Introduction 2 Installation and Handling 3 Reference Numbers Table 3.1. Parts and Assemblies for the DPP1, H12513F1 ........13 Table 3.2. Accessories ..................13 4 Product Status and Modifications Table 4.1. PCI Interrupt Selection ................ 15 Table 4.2. - Page 54 Table 5.31: Type of External Memory ..............39 Table 5.32: Bit Allocation at the EMIF Bus ............. 40 Table 5.33: Type of FIFO‘s Used on the DPP1 ............40 Table 5.34. Memory Region of EMIF Bus .............. 41 Table 5.35: Address Allocation of the Registers ............. 41 Table 5.36: Control Register: Bit Fields ..............
- Page 55 End of Document Technical Manual Version 001 BRUKER BIOSPIN 55 (55)
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