Teledyne SP Devices ADQ8-8C Manual
  1. Manuals
  2. Brands
  3. Teledyne SP Devices Manuals
  4. Measuring Instruments
  5. ADQ8-8C
  6. Manual

Teledyne SP Devices ADQ8-8C Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
Manual ADQ8-8C
This manual describes how to get the full potential out of Teledyne SP Devices'
digitizer ADQ8-8C. The manual includes these steps:
•
Set up the analog front-end
•
Master the triggers
•
Control the acquisition
•
Manage the sampling clock
•
Understanding data transfer to host PC
•
Using GPIO
Teledyne Signal Processing Devices Sweden AB | Teknikringen 6, SE-583 30 Linköping, Sweden | www.spdevices.com
Regional sales offices | www.spdevices.com/contact
ADQ8-8C Manual
17-2000 C 2020-09-17
1(50)

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the ADQ8-8C and is the answer not in the manual?

Questions and answers

Related Manuals for Teledyne SP Devices ADQ8-8C

Summary of Contents for Teledyne SP Devices ADQ8-8C

  • Page 1 ADQ8-8C Manual 17-2000 C 2020-09-17 1(50) Manual ADQ8-8C This manual describes how to get the full potential out of Teledyne SP Devices’ digitizer ADQ8-8C. The manual includes these steps: • Set up the analog front-end • Master the triggers •...

  • Page 2: Table Of Contents

    1.2.5 System clocks..........................6 1.2.6 Analog signal range ........................7 Digitizer Studio overview....................8 SETTING UP THE ANALOG FRONT-END ..............9 ADQ8-8C AFE block diagram ..................9 Set input impedance ...................... 9 Set analog input range....................9 Set analog DC-offset....................10 Adjusting the digital gain and offset ................
  • Page 3 CLOCK......................... 32 Clock domains ......................32 Flexible clock network....................32 ADQ8-8C-PCIe front panel connectors................ 34 ADQ8-8C-MTCA front panel SMA connector .............. 34 Internal clock reference....................34 External clock reference ....................34 Clock reference phase tuning ..................35 Internal clock generator ....................35 External clock.......................
  • Page 4 ADQ8-8C Manual 17-2000 C 2020-09-17 4(50) PCI Express interface ....................48 Using several units....................... 48 8.2.1 Using several digitizers from a single application..............48 8.2.2 Using several digitizers from a several applications..............48 REFERENCES ......................49 17-2000 C...

  • Page 5: Introduction

    Data format The ADC components of ADQ8-8C has 10 bits resolution, while the data format inside the ADQ8-8C and out to the host PC is 16 bits. The 16 bits from the ADCs are MSB aligned in this 16 bit data word.

  • Page 6: Calibration

    This effectively doubles the ENOB for a unipolar signal. 1.2.4 Sampling clock frequency The ADQ8-8C is designed for the specified 1 GHz clock frequency only. A different sampling rate can be achieved by using the sample skip function, Section 5.11.

  • Page 7: Analog Signal Range

    ADQ8-8C Manual 17-2000 C 2020-09-17 7(50) Section 5.1 for more details on the clock system. 1.2.6 Analog signal range The analog signal range ( ) is symmetrical around zero. The value of the ACTUAL_ANALOG_RANGE analog signal range it is depending on the gain setting. With for example a range of, 500 mV , the ana- log input signal can vary from –250 mV to +250 mV and the range can be moved from [–0 mV...

  • Page 8: Digitizer Studio Overview

    8(50) 1.3 Digitizer Studio overview The application software Digitizer Studio is an easy way to operate the ADQ8-8C. Digitizer Studio is a graphical interface. The different blocks of the ADQ digitizer are represented by several views in Digi- tizer Studio. These blocks are linked as in Figure 2.

  • Page 9: Setting Up The Analog Front-End

    The MTCA.4 version of ADQ8-8C–VG is always 50 terminated to ground. 2.3 Set analog input range On ADQ8-8C–VG, the input range is variable. The requested input signal range is sent to the API, which reads available settings and return the best selection. The actual value of each range is available...

  • Page 10: Set Analog Dc-Offset

    ADQ8-8C Manual 17-2000 C 2020-09-17 10(50) is the actual calibrated range of the device returned from ACTUAL_ANALOG_RANGE SetInputRange The maximum digital code 2^15 represents an analog signal with a level ACTUAL_ANALOG_RANGE / 2 at the input. A specific analog signal...

  • Page 11: Signal Quality Enhancement

    ADQ8-8C Manual 17-2000 C 2020-09-17 11(50) SIGNAL QUALITY ENHANCEMENT 3.1 Digital Baseline Stabilizer The Digital Baseline Stabilizer, DBS, is designed for pulse data measurement where high accuracy rel- ative a known baseline is required. The key features of DBS are: •...

  • Page 12: Trigger

    ADQ8-8C Manual 17-2000 C 2020-09-17 12(50) TRIGGER 4.1 Trigger block diagram 34  "&  (   34   $  % &   '() 34 % &     * #     '()    * # ...

  • Page 13: Introduction

    ADQ8-8C Manual 17-2000 C 2020-09-17 13(50) 4.2 Introduction The digitizer can be triggered in various ways with a number of different internal and external trigger sources. Selected events in the trigger module can also be output to trigger external equipment. The...

  • Page 14: Timestamp

    Example 3: Assume an ADQ8-8C sampling with a clock frequency at 1 GSPS. The pretrigger is set to 16 samples and the external trigger is used. The following parameters are returned:...
  • Page 15 ADQ8-8C Manual 17-2000 C 2020-09-17 15(50) 1. The timestamp counter is reset at power-up. This methods does not, however, have absolute preci- sion, since the timing of the power up is not defined. In a multi-board system, the timestamp will dif- fer between the boards.

  • Page 16: Blocking Triggers For Synchronization

    ADQ8-8C Manual 17-2000 C 2020-09-17 16(50) +,   -./ %   +,   %01     & '                  DESCRIPTION USER COMMAND External trigger input signal on front panel connector.
  • Page 17 ADQ8-8C Manual 17-2000 C 2020-09-17 17(50) Figure 9 illustrates how the triggers are accepted or rejected in the window mode. /0  12.       "3  /0  45 63  7  "3 ...

  • Page 18: Block Triggers Once

    ADQ8-8C Manual 17-2000 C 2020-09-17 18(50) '  $ ) *& !&  % !   + ,  % !   +,  % !   +,  % !   + , DESCRIPTION USER COMMAND The trigger blocker in window or gate mode allows triggers during a SetupTriggerBlocking 4.5.1 certain period. Example of rejected triggers outside the window.

  • Page 19: Trigger Jitter

    The RMS value of such a process is /sqrt(12). TRIGGER_CLOCK_PERIOD The highest resolution is achieved with an external trigger connected to the TRIG connector. ADQ8-8C has a trigger clock at 4 GSPS, of 250 ps and a trigger jitter of TRIGGER_CLOCK_PERIOD 72 ps RMS (theoretical value), Section 4.6.4.

  • Page 20: Synchronous Trigger

    ADQ8-8C Manual 17-2000 C 2020-09-17 20(50) 4.6.3 Synchronous trigger A synchronous trigger is phase locked to the clock of the digitizer. The trigger source needs access to the clock reference of the digitizer. There are three ways to achieve this synchronization: 1.

  • Page 21: External Trigger Inputs

    ADQ8-8C Manual 17-2000 C 2020-09-17 21(50) DisArmTrigger (“software trigger”) SetTriggerMode ArmTrigger SWTrig 6. Read data and analyze the situation 4.8 External Trigger Inputs An external trigger is a dedicated signal on a dedicated input to the ADQ. There are several inputs for...

  • Page 22: External Trigger Sync Connector

    ADQ8-8C Manual 17-2000 C 2020-09-17 22(50) *# ./    +-        #  (- DESCRIPTION USER COMMAND The input is available on an SMA connector on the front panel. The input impedance can be set as 50  (default) or high SetTriggerInputImpedance 4.8.3...

  • Page 23: External Trigger In The Backplane

    ADQ8-8C Manual 17-2000 C 2020-09-17 23(50) However, in a high fan-out situation, where a trigger source has to drive many nodes, the load can be too high. The trigger input can then be set in a high impedance mode and a bussed connection can be...

  • Page 24: Mtca.4 Interface

    ADQ8-8C Manual 17-2000 C 2020-09-17 24(50) %  * +, - +, - !+ , !+ ,% !+ , % * * DESCRIPTION USER COMMAND Backplane Trigger bus and DSTAR connections Set direction for each port in the backplane SetDirectionPXI...

  • Page 25: Level Trigger

    ADQ8-8C Manual 17-2000 C 2020-09-17 25(50) %  * -./  ./ -.0  .0 -.  . -.  . % * * DESCRIPTION USER COMMAND Backplane MLVDS bus Set direction for each port in the backplane SetDirectionMLVDS Output: Select output port for trigger output SetupTriggerOutput 4.12...

  • Page 26: 1Setting The Level Trigger Level

    ADQ8-8C Manual 17-2000 C 2020-09-17 26(50)      )    * $ DESCRIPTION USER COMMAND When the signal passes the trigger level, a trigger event is generated and SetupLevelTrigger 4.10.1 the first record is captured.

  • Page 27: Internal Trigger

    ADQ8-8C Manual 17-2000 C 2020-09-17 27(50)    DESCRIPTION USER COMMAND The level trigger has a hysteresis function to avoid false triggering on 4.10.3 noise. When the signal passes below the RESET_LEVEL_CODE, the ADQ may trigger again.

  • Page 28: 2Frame Sync Output On Sync Connector

    ADQ8-8C Manual 17-2000 C 2020-09-17 28(50) 4.12.2 Frame sync output on SYNC connector The frame sync feature enables grouping of trigger signals into frames or blocks or lines. The name for this feature relate to the actual application. This function can, for example, be used in scanning three- dimensional measurements where a record is the first dimension, the trigger is the second and the frame sync is the third dimension.

  • Page 29: Large Scale Integration Trigger Support

    Figure 20: External routing of internal trigger. 4.13 Large scale integration trigger support The ADQ8-8C supports integration into a large scale PXIe chassis for single shot applications, Figure 21. The function is described in the manual [6]. This section is only a short introduction.

  • Page 30: 1Distributing Trigger

    ADQ8-8C Manual 17-2000 C 2020-09-17 30(50) 4.13.1 Distributing trigger The trigger is distributed to the boards via the SYNC input and output. The trigger distribution is daisy chained, so there is no limit to the number of boards. The cable in...
  • Page 31 ADQ8-8C Manual 17-2000 C 2020-09-17 31(50) 123 &0 # &#$ 123 "  $ $ .#   # $ 0 $ $  /. 123 "  $ $ .#   # $ 0  $$#  /.

  • Page 32: Clock

    ADQ8-8C Manual 17-2000 C 2020-09-17 32(50) CLOCK 5.1 Clock domains Different parts of the digitizer system operate on different clocks. The core of the clocking system is the clock reference. This is the phase and frequency reference of the digitizer system. It is possible to use different clock reference sources to meet the requirements of different applications.
  • Page 33 The digitizer supports its specified sample rate only. This sample rate can be tuned to allow phase locking to external equipment. To reduce the sample-rate, a sample skip function is available. Block diagrams of the clock network for ADQ8-8C-PXIe and ADQ8-8C-MTCA are given in Figure 24 Figure 25...

  • Page 34: Adq8-8C-Pcie Front Panel Connectors

    The input impedance is 50  to match the cable impedance. The front panel MCX connector is used for clock reference output. 5.4 ADQ8-8C-MTCA front panel SMA connector The front panel SMA connector is used for external clock reference input, direct external sampling clock input or clock reference output.

  • Page 35: Clock Reference Phase Tuning

    ADQ8-8C Manual 17-2000 C 2020-09-17 35(50) may be necessary. To support that, the ADQ offers several options to accept an external clock refer- ence. A long-term phase stability to other equipment is then guaranteed. The connector on the front panel accepts a clock reference from external equipment. The clock refer- ence quality is improved in a jitter cleaning circuitry.

  • Page 36: Gpio

    ADQ8-8C Manual 17-2000 C 2020-09-17 36(50) GPIO The General Purpose Input and Output (GPIO) are digital signals available from the front panel of the digitizer. The GPIO is an optional use of the TRIG and SYNC connectors. The user assigns a function to these pins, either in the firmware through the ADQ Development Kit or from software.

  • Page 37: Adq8-8C-Pxie Gpio On Sync Connectors

    17-2000 C 2020-09-17 37(50) 6.2 ADQ8-8C–PXIe GPIO on SYNC connectors On the ADQ8-8C–PXIe form factor, the sync input pin and output pins are split into two connectors. This means that the sync pin is not bi-directional when used as GPIO, Figure...

  • Page 38: Gpio In Adq Development Kit

    ADQ8-8C Manual 17-2000 C 2020-09-17 38(50) 6.6 GPIO in ADQ Development Kit The GPIO signals from TRIG and SYNC are available in the ADQ Development Kit for real-time interac- tion with the signal flow. 17-2000 C 2020-09-17 38(50)

  • Page 39: Acquisition Control

    ADQ8-8C Manual 17-2000 C 2020-09-17 39(50) ACQUISITION CONTROL The acquisition control consists of two partly independent parts; • Acquisition process: acquisition of data in a record into the DRAM of the digitizer • Transfer process: transfer data from the DRAM of the digitizer to host PC.

  • Page 40: Triggered Streaming Acquisition

    The acquisition mode triggered streaming is described in [7]. 7.4 Acquisition mode multi-record ADQ8-8C supports acquisition mode multi-record. This mode is suitable for most user-scheduled single shot or multi-shot applications. It is also suitable for control and surveillance applications where the long pre-trigger makes it possible to see what preceded an event.

  • Page 41: Re-Arm Time

    ADQ8-8C Manual 17-2000 C 2020-09-17 41(50) ," ," )  + + +- ," )  )  Figure 30: Multi-record organization of memory.    %    $  %   Figure 31: Multi-record timing. 7.5 Re-arm time The re-arm time a the time after a record has been completely acquired when the digitizer cannot receive a new trigger.

  • Page 42: User Scheduled Data Transfer Mode

    ADQ8-8C Manual 17-2000 C 2020-09-17 42(50) )&  )&       *+ ,    -    )&  )&      "    *.+ "   )&          * +    Figure 32: Re-arm timing.
  • Page 43 ADQ8-8C Manual 17-2000 C 2020-09-17 43(50) 2#' 3 2# # # )   " 001 %  # # %" # "" !  2) # # !  2) # # -"  $ * + , * + ##  " #"  "  ...

  • Page 44: Transfer Buffers

    ADQ8-8C Manual 17-2000 C 2020-09-17 44(50) '  *  '  *  $ '  *  7 '  *       Figure 34: Timing of user-scheduled data transfer.

  • Page 45: Record Header

    ADQ8-8C Manual 17-2000 C 2020-09-17 45(50) .    . +  "/ 0 "2 1  1     .    .    . +  "/ 0 "2 1  1  1  2345       .

  • Page 46: User Id

    ADQ8-8C Manual 17-2000 C 2020-09-17 46(50) FIFO fill factor is indicated. This is useful when tuning a data-driven process to avoid FIFO overflow and still get maximum efficiency from the experiment. For very long records, the maximum fill factor during the record is given.

  • Page 47: Over-Range And Under-Range

    ADQ8-8C Manual 17-2000 C 2020-09-17 47(50) 7.10 Over-range and under-range The over/under-range bit in the header indicates that over-range or under-range occurred at one or several samples within the record and at any stage in the signal chain. The result of the over-range is...

  • Page 48: Host Pc Connection

    ADQ8-8C Manual 17-2000 C 2020-09-17 48(50) HOST PC CONNECTION 8.1 PCI Express interface The MTCA, and PXIE versions of the digitizer use PCI Express generation 1 and 2 electrical interface to communicate with the host PC. The PCIe version of the digitizer support up to 8 lanes and the MTCA version support up to 4 lanes.
  • Page 49 ADQ8-8C Manual 17-2000 C 2020-09-17 49(50) REFERENCES 17-1997 ADQ8-8C Datasheet 14-1351 ADQAPI Reference guide 08-0214 ADQAPI User guide 18-2059 ADQUpdater user guide 20-2382 Digitizer Studio manual 19-2246 ADQ8 Daisy-Chain Board synchronization 20-2465 ADQ8 Triggered streaming 17-2000 C 2020-09-17 49(50)
  • Page 50 Teledyne SP Devices. In no event shall Teledyne SP Devices be liable for any damages arising out of or related to this docu- ment or the information contained in it.

Table of Contents