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Evaluation Board Assembly Instructions
The QFN−16 evaluation board is designed for
characterizing devices in a 50 W laboratory environment
using high bandwidth equipment. Each signal trace on the
board has a via at the DUT pin, which provides an option of
placing a termination resistor on the board bottom,
depending on the input/output configuration (see Table 1,
Configuration for Device: NB6N11S). Table 4 contains the
Bill of Materials for this evaluation board.
The QFN16EVB was designed to accommodate a custom
QFN−16 socket. Therefore, some external components are
installed on the bottom side of the board.
Solder the Device on the Evaluation Board
The soldering of a device to the evaluation board can be
accomplished by hand soldering or solder reflow techniques
using solder paste. Make sure pin 1 of the device is located
properly and all the pins are aligned to the footprint pads.
Solder the QFN−16 device to the evaluation board. As
mentioned earlier, many QFN16EVBs are dedicated with a
device already installed, and can be ordered from
onsemi.com at the specific device web page.
Connecting Power and Ground
On the top side of the evaluation board, solder the four
surface mount test point clips (anvils) to the pads labeled
V
, V
/DUTGND, SMAGND, and ExPad. ExPad is
CC
EE
connected to the exposed flag of the QFN package. For
proper
operation,
the
recommended to be tied to V
supply of the device.
The positive power supply connector is labeled V
Depending on the device, the negative power supply
nomenclature is labeled either GND or V
NB6N11SMNGEVB
Figure 5. Evaluation Board Layout
exposed
flag
is
typically
/DUTGND, the negative
EE
. To help avoid
EE
http://onsemi.com
confusion with the use of this board, the negative supply
connector is labeled V
ground for the SMA connectors and is not to be confused
with the device ground, V
DUTGND can be connected in single-supply applications.
The power pin layout and typical connection of the
evaluation board is shown in Figure 6.
It is recommended to add bypass capacitors to reduce
unwanted noise from the power supplies. Connect 0.1 mF
capacitors from V
Output Loading/Termination
ECL/PECL/LVPECL
Most ECL outputs are open emitter and need to be DC
loaded and AC terminated to V
If no internal resistors are provided on the device, 0402 chip
resistor pads are provided on the bottom side of the
evaluation board to terminate the ECL driver. Solder the
chip resistors to the bottom side of the board between the
appropriate input device pads and the ground pads. If
internal resistors are provided, the VT pins should be wired
to SMAGND. (More information on termination is provided
in AND8020).
For standard ECL lab setup and test, a split (dual) power
supply is recommended enabling the 50 W internal
impedance in the oscilloscope, or other measuring
instrument, to be used as an ECL output load/termination.
By offsetting V
CC
(SMAGND is the system ground, 0V); V
V
/DUTGND is −3.0 V, −1.3 V or −0.5 V; see Table 2,
EE
.
Power Supply Levels).
CC
3
Bottom View
/DUTGND. SMAGND is the
EE
/DUTGND. SMAGND and
EE
and V
/DUTGND to SMA_GND.
CC
EE
Outputs
− 2.0 V via a 50 W resistor.
CC
= +2.0 V, SMAGND = V
CC
− 2.0 V,
CC
is 2.0 V, and
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