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Texas Instruments TPA3124D2 Instructions Manual
Texas Instruments TPA3124D2 Instructions Manual

Texas Instruments TPA3124D2 Instructions Manual

15-w stereo class-d

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FEATURES
1
• 10-W/Ch Into an 8-Ω Load From a 24-V Supply
234
• 15-W/Ch into a 4-Ω Load from a 22-V Supply
• 30-W/Ch into a 8-Ω Load from a 22-V Supply
• Operates From 10 V to 26 V
• Can Run From +24 V LCD Backlight Supply
• Efficient Class-D Operation Eliminates Need
for Heat Sinks
• Four Selectable, Fixed-Gain Settings
• Internal Oscillator (No External Components
Required)
• Single-Ended Analog Inputs
• Thermal and Short-Circuit Protection With
Auto Recovery
• Space-Saving Surface Mount 24-Pin TSSOP
Package
• Advanced Power-Off Pop Reduction
Left Channel
Right Channel
10 V to 26 V
Shutdown Control
Mute Control
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DLP is a registered trademark of Texas Instruments.
2
System Two, Audio Precision are trademarks of Audio Precision, Inc.
3
All other trademarks are the property of their respective owners.
4
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
15-W STEREO CLASS-D AUDIO POWER AMPLIFIER
SIMPLIFIED APPLICATION CIRCUIT
1 F
m
LIN
RIN
1 F
m
1 F
m
BYPASS
AGND
AVCC
SD
MUTE
APPLICATIONS
• Flat Panel Televisions
• DLP
®
TVs
• CRT TVs
• Powered Speakers
DESCRIPTION
The TPA3124D2 is a 15-W (per channel), efficient,
class-D audio power amplifier for driving stereo
speakers in a single-ended configuration; or, a mono
speaker in a bridge-tied-load configuration. The
TPA3124D2 can drive stereo speakers as low as 4 Ω.
The efficiency of the TPA3124D2 eliminates the need
for an external heat sink when playing music.
The gain of the amplifier is controlled by two gain
select pins. The gain selections are 20, 26, 32, and
36 dB.
The patented start-up and shutdown sequences
minimize pop noise in the speakers without additional
circuitry.
TPA3124D2
0.22 F
m
BSR
33 H
ROUT
0.22 F
PGNDR
PGNDL
0.22 F
LOUT
33 H
BSL
0.22 F
m
PVCCL
PVCCR
VCLAMP
1 F
m
GAIN0
GAIN1
TPA3124D2
SLOS578 – MAY 2008
470 F
m
m
m
m
m
470 F
m
10 V to 26 V
4-Step Gain Control
S0267-02
Copyright © 2008, Texas Instruments Incorporated

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Summary of Contents for Texas Instruments TPA3124D2

  • Page 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DLP is a registered trademark of Texas Instruments.
  • Page 2 High-voltage analog power supply. Not internally connected to PVCCR or PVCCL Connect to ground. Thermal pad should be soldered down on all applications to secure the Thermal pad Die pad device properly to the printed wiring board. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3124D2...
  • Page 3 Low-level input current MUTE, V = 0 V, V = 30 V GAIN0, GAIN1, V = 0 V, V = 24 V °C Operating free-air temperature –40 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3124D2...
  • Page 4 Δt mute Mute delay Time from mute input switches high until outputs muted Δt unmute Unmute delay Time from mute input switches low until msec outputs unmuted Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3124D2...
  • Page 5 AVDD PGNDL DETECT AVDD/2 AGND CONTROL BIAS THERMAL VCLAMP MUTE MUTE CONTROL OSC/RAMP BYPASS BYPASS GAIN1 CONTROL GAIN0 DETECT PVCCR ROUT – VCLAMP PGNDR AVDD AVDD AVDD/2 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3124D2...
  • Page 6 = 2.5 W 0.01 0.01 = 1 W = 1 W 0.001 0.001 f − Frequency − Hz f − Frequency − Hz G003 G004 Figure 3. Figure 4. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3124D2...
  • Page 7 −80 0.01 = 24 V −90 −100 0.001 10k 20k 0.01 f − Frequency − Hz − Output Power − W G008 G007 Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3124D2...
  • Page 8 = 470 µF Gain Gain Phase Phase −100 −100 −200 −200 100k 100k f − Frequency − Hz f − Frequency − Hz G011 G012 Figure 11. Figure 12. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3124D2...
  • Page 9 = 8 Ω (SE) Gain = 20 dB Gain = 20 dB − Output Power − W − Output Power − W G015 G016 Figure 15. Figure 16. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3124D2...
  • Page 10 −70 −80 −80 −90 −90 −100 −100 10k 20k 10k 20k f − Frequency − Hz f − Frequency − Hz G019 G025 Figure 19. Figure 20. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3124D2...
  • Page 11 = 8 Ω (BTL) Gain = 20 dB − Supply Voltage − V − Output Power − W G023 G024 Figure 24. Dashed line represents thermally limited region. Figure 23. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3124D2...
  • Page 12 TPA3124D2 may be used as a bridge-tied-load (BTL) amplifier. The traditional class-D modulation scheme, which is used in the TPA3124D2 BTL configuration, has a differential output where each output is 180 degrees out of phase and changes from ground to the supply voltage, V .
  • Page 13 For design purposes, the input network (discussed in the next section) should be designed assuming an input impedance of 8 kΩ, which is the absolute minimum input impedance of the TPA3124D2. At the higher gain settings, the input impedance could increase as high as 72 kΩ.
  • Page 14 It is important to use a high-quality capacitor in this application. A rating of at least X7R is required. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3124D2...
  • Page 15 Figure 28. SE Filter Configuration Power-Supply Decoupling, C The TPA3124D2 is a high-performance CMOS audio amplifier that requires adequate power-supply decoupling to ensure that the output total harmonic distortion (THD) is as low as possible. Power-supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power-supply leads.
  • Page 16 N-channel power MOSFET gate-drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3124D2...
  • Page 17 MUTE Operation The MUTE pin is an input for controlling the output state of the TPA3124D2. A logic high on this terminal causes the outputs to run at a constant 50% duty cycle. A logic low on this pin enables the outputs. This terminal may be used as a quick disable/enable of outputs when changing channels on a television or transitioning between different audio sources.
  • Page 18 PRINTED-CIRCUIT BOARD (PCB) LAYOUT Because the TPA3124D2 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuit board (PCB) should be optimized according to the following guidelines for the best possible performance.
  • Page 19 PVCCR PGNDR 0.68 F Shutdown Control –OUT Mute Control 1.0 F 1.0 F 10 F 0.1 F S0294-02 Figure 33. Schematic for Bridge-Tied-Load (BTL) Configuration (8-Ω Speaker) Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3124D2...
  • Page 20 This is because it takes an analog input signal and converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some analyzers. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3124D2...
  • Page 21 20 Hz - 20 kHz Generator (a) Basic Class-AB Power Supply filt Analyzer Signal Class-D APA filt 20 Hz - 20 kHz Generator (b) Traditional Class-D Figure 34. Audio Measurement Systems Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): TPA3124D2...
  • Page 22 TPA3124D2 SLOS578 – MAY 2008........................................www.ti.com SE Input and SE Output (TPA3124D2 Stereo Configuration) The SE input and output configuration is used with class-AB amplifiers. A block diagram of a fully SE measurement circuit is shown in Figure 35. SE inputs normally have one input pin per channel. In some cases, two pins are present;...
  • Page 23 SLOS578 – MAY 2008 DIFFERENTIAL INPUT AND BTL OUTPUT (TPA3124D2 Mono Configuration) Many of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied-load (BTL) outputs. Differential inputs have two input pins per channel and amplify the difference in voltage between the pins.
  • Page 24 PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) TPA3124D2PWPR HTSSOP 2000 330.0 16.4 6.95 16.0 Pack Materials-Page 1...
  • Page 25 PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) TPA3124D2PWPR HTSSOP 2000 350.0 350.0 43.0 Pack Materials-Page 2...
  • Page 26 GENERIC PACKAGE VIEW PWP 24 PowerPAD TSSOP - 1.2 mm max height PLASTIC SMALL OUTLINE 4.4 x 7.6, 0.65 mm pitch This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224742/B www.ti.com...
  • Page 27 TYPICAL 2.40 1.65 4222709/A 02/2016 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice.
  • Page 28 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
  • Page 29 EXAMPLE STENCIL DESIGN PWP0024B PowerPAD TSSOP - 1.2 mm max height PLASTIC SMALL OUTLINE (2.4) BASED ON 0.125 THICK 24X (1.5) STENCIL 0.05 ) TYP 24X (0.45) (5.16) SYMM BASED ON 0.125 THICK STENCIL 22X (0.65) SYMM METAL COVERED SEE TABLE FOR BY SOLDER MASK DIFFERENT OPENINGS (5.8)
  • Page 30 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated...