Avago MC68HC11 Application Brief

Interfacing the MC68HC11 to the HCTL-2020
Application Brief M-023
Introduction
This application brief describes two interfaces for the
HCTL-2020 to the MC68HC. One is a port interface and
the other is a bus interface.
;******************************************************************************
;THIS SUBROUTINE IS USED TO READ DATA FROM THE HCTL-2020 ;FOR THE PORT
INTERFACE.
;THE SUBROUTINE RETURNS THE 6 BIT DATA FROM THE HCTL-;2020 IN REGISTER IX.
;* DENOTES ACTIVE LOW SIGNALS.
;******************************************************************************
RD2020: PSHA
PSHB
LDAA#00
STAA$007
LDAA#0FA
STAA$004
LDAA$003
LDAB#0FB
STAB$004
LDAB$003
XGDX
;THE HCTL-2020
LDAA#0FF
STAA$004
PULB
PULA
RTS
;******************************************************************************
;THIS SUBROUTINE IS USED TO RESET THE HCTL-2020 IN THE ;PORT INTERFACE.
;******************************************************************************
RST2020: PSHA
LDAA#0EF
STAA$004
LDAA#0FF
STAA$004
PULA
RTS

;SAVE REG A ON STACK.
;PUT PORT C IN INPUT MODE.
;SEL LO AND OE* LO.
;HIGH BYTE OF DATA IN REG. A.
;SEL HI AND OE* LO.
;LO BYTE IN REG. B.
;REGISTER IX HAS THE 6 BIT VALUE FROM
;SEL HI AND OE* HI.
;RESTORE REG B FROM STACK.
;RESTORE REG A FROM STACK.
;RST*LO.
;RST*HI.
Port Interface
The connections are shown in Figure , the schematic
titled "Port Interface". Port C is used to read the data in
and 3 pins on port B are used for the control signals to
the HCTL-2020. The E clock from the 68HCE9 is used to
clock the HCTL-2020. In this interface it is assumed that
the 68HCE9 is in the single chip mode.
The subroutines to read from the HCTL-2020 and to reset
the HCTL-2020 follow.