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Summary of Contents for artisan V490
- Page 1 sales@artisantg.com artisantg.com (217) 352-9330 | Visit our website - Click HERE...
- Page 2 V490 16-CHANNEL MULTI-RANGE DIGITIZER Technical Manual July 18, 2019...
- Page 3 Highland Technology, Inc. may make changes and improvements to the product(s) and/or programs described in this publication at any time without notice. The V490 has finite failure rates associated with its hardware, firmware, design, and documentation. Do not use the product in applications where a failure or defect in the instrument may result in injury, loss of life, or property damage.
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Page 4: Table Of Contents
Table of Contents Introduction ........................5 Specifications: V490 Analog Input Module ..............6 Overview ........................8 Channel Circuits ...................... 8 Signal Processing..................... 9 Connectors and Installation ..................11 ... - Page 5 Interpolation ......................50 Noise Performance ....................52 Versions ........................53 Customization ......................53 Hardware and Firmware Revision History ............... 53 12.1 Hardware Revision History ................53 12.2 Firmware Revision History ................
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Page 6: Introduction
Introduction This is the manual for the V490, a 16-channel fast analog-to-digital converter VME module. Features of the V490 include: 16 channels of differential analog input acquisition. Each channel is independently programmable for input range, sample rate, operating modes, and digital lowpass filtering. -
Page 7: Specifications: V490 Analog Input Module
Specifications: V490 Analog Input Module FUNCTION 16-channel differential analog-to-digital converter DEVICE TYPE 16-bit VME register-based slave: A24:A16:D16:D32; Implements 256 16-bit registers at switch selectable addresses in the VME 16 or 24 bit addressing spaces RANGES Programmable per channel ±10.24 mV ± 40.96 mV ± 160 mV ± 640 mV ±... - Page 8 CONNECTORS Two D25 female, each 8 channels One D9 male analog test One SMB trigger i/o INDICATORS LEDs indicate VME access, CPU activity, error conditions Additional LED is user programmable PACKAGING 6U single-wide VME module CONFORMANCE ANSI/VITA 1-1994 (R2002) VME bus spec; does not support byte writes Bandwidth Specifications: Range...
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Page 9: Overview
Overview The V490 includes 16 independent differential-input analog-to-digital converters. 3.1 Channel Circuits Each channel includes BIST/CAL relay Input protection Input attenuator Variable-gain differential amplifier 100 KHz analog anti-aliasing lowpass filter 16-bit A/D converter Digital signal processing... -
Page 10: Signal Processing
3.2 Signal Processing In the standard V490, all sixteen ADCs are triggered at a constant 500 KHz rate. Each resulting data stream is digitally lowpass filtered and the result posted to a "realtime" VME register at the 500 KHz rate. Users may read this register at any time. - Page 11 The MTRIG global trigger signal can come from a variety of internal and external sources; see section 8. CAUTION: V490 differential inputs have approximately 500 K ohms impedance to ground. If connected to floating sources, users should provide a DC path to ground to prevent leakage currents and hum from producing excess common-mode voltages.
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Page 12: Connectors And Installation
Connectors and Installation 4.1 Address DIP Switches The V490 appears as 256 16-bit registers in the VME 16 or 24-bit addressing spaces. The base address of the 256 registers is set by dip switches. Four 4-position rocker-type dipswitches are provided near the top edge of the board. -
Page 13: Installation
It supports 32-bit data transfers using the P1 and P2 connectors, or may be used in 16-bit mode using only the P1 backplane connector. The V490 passes all interrupt and bus grant signals, so may be used with backplane grant jumpers installed or not installed. -
Page 14: D25 Input Connectors
4.3 D25 Input Connectors Two front-panel female D-25 connectors are provided. Pinout is as follows: J1 Pin Function J2 Pin Function J1-1 ch 0+ J2-1 ch 8+ J1-14 ch 0- J2-14 ch 8- J1-2 ch 1+ J2-2 ch 9+ J1-15 ch 1- J2-15 ch 9-... -
Page 15: D9 Calibration Connector
CMOS, or 5-volt CMOS levels. As an output, it provides 3.3 volt CMOS trigger pulses. See section 8. The V490 is capable of accepting external triggers, or of operating multiple modules in master/slave trigger modes, emulating asynchronously triggered, ADC-... - Page 16 Highland can furnish SMB-BNC cables, multi-station trigger connector bussing assemblies, and electrical or fiberoptic trigger fanouts.
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Page 17: Operation
Operation 5.1 LEDs There are four front-panel LED indicators. The blue VME led flashes whenever the module is accessed from the VME bus. The green CPU led flashes about once a second to indicate CPU activity The red ERR led will flash to indicate errors: Two blinks Channel Configuration Error Three blinks... -
Page 18: Quick Start
See section 4.1. The as-shipped default is address 0xC000 in the 16- bit address space. With crate power off, insert the V490 into any crate slot and firmly secure its mounting screws. Do not hot-plug VME modules. Power up. After a few seconds, the V490 green "CPU" LED should flash, and the other LEDs should be off. - Page 19 Channel ranges and filter settings can be changed by writing to the channel control and filter control registers; see section 6.13.
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Page 20: Vme Registers
Read-write + macro registers (RWM) can be written by the user, but may also be changed by the V490 in response to a user executed MACRO command. A macro handshake protocol is defined in Section 6.8. VMEbus response time (DS0* to DTACK*) averages about 125 ns. -
Page 21: Vme Register Map
6.1 VME Register Map Reg Name REG# Offset Function VXI MFR 0x00 Highland ID: reads 65262, 0xFEEE VXI TYPE 0x02 V490 module ID, 22490, 0x57DA SERIAL 0x06 unit serial number ROM ID 0x08 firmware ID, typically 22490 decimal ROM REV 0x0A firmware revision, typically ASCII "B"... - Page 22 Reg Name REG# Offset Function BOUNCE 0x36 trigger debounce control 0x38 500 KHz trigger divisor CTL0 0x40 channel 0 control FILT0 0x42 channel 0 filtering FIFO0 0x44 channel 0 FIFO status FDIV0 0x46 channel 0 FIFO rate divisor RDAT0 0x48 channel 0 realtime data 0x4A reserved...
- Page 23 Reg Name REG# Offset Function FDIV3 0x76 channel 3 FIFO rate divisor RDAT3 0x78 channel 3 realtime data 0x7A reserved FDAT3A 0x7C channel 3 FIFO data A FDAT3B 0x7E channel 3 FIFO data B CTL4 0x80 channel 4 control FILT4 0x82 channel 4 filtering FIFO4...
- Page 24 Reg Name REG# Offset Function CTL7 0xB0 channel 7 control FILT7 0xB2 channel 7 filtering FIFO7 0xB4 channel 7 FIFO status FDIV7 0xB6 channel 7 FIFO rate divisor RDAT7 0xB8 channel 7 realtime data 0xBA reserved FDAT7A 0xBC channel 7 FIFO data A FDAT7B 0xBE channel 7 FIFO data B...
- Page 25 Reg Name REG# Offset Function FDAT10A 0xEC channel 10 FIFO data A FDAT10B 0xEE channel 10 FIFO data B CTL11 0xF0 channel 11 control FILT11 0xF2 channel 11 filtering FIFO11 0xF4 channel 11 FIFO status FDIV11 0xF6 channel 11 FIFO rate divisor RDAT11 0xF8 channel 11 realtime data...
- Page 26 Reg Name REG# Offset Function FDIV14 0x126 channel 14 FIFO rate divisor RDAT14 0x128 channel 14 realtime data 0x12A reserved FDAT14A 0x12C channel 14 FIFO data A FDAT14B 0x12E channel 14 FIFO data B CTL15 0x130 channel 15 control FILT15 0x132 channel 15 filtering FIFO15...
- Page 27 Reg Name REG# Offset Function TONE27 0x1D6 single-channel BIST data PERR 0x1E0 power supply error flags EP17 0x1E2 +17 power supply voltage 0x1E4 +8.8 0x1E6 0x1E8 +3.3 0x1EA +2.048 0x1EC +1.25 0x1EE EM17 0x1F0 UTEST 0x1FC user read/write test register HTEST 0x1FE always reads 0xABCD...
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Page 28: Module Overhead Registers
6.2 Module Overhead Registers A number of read-only overhead registers are provided. VXI MFR: always reads 0xFEEE, Highland's registered VXI module ID code. VXITYPE: always reads 22490 decimal to identify a V490 module SERIAL: module serial number. DASH: module version (dash) number. -
Page 29: Uled - User Led Control
ULED pattern 0x0000 turns the user LED off. Pattern 0xFFFF turns it steady on. 6.5 MODE - Calibration Bus Control The V490 includes an internal calibration bus and the optional BIST test voltage generator. The MODE register controls routing of signals between the front-panel D9 connector, the cal bus, and the BIST source. -
Page 30: Calid, Ycal, Dcal - Calibration Status Registers
YCAL and DCAL display the last date of module calibration. YCAL is the year, as an integer, such as 2010 decimal. The high byte of DCAL is month 1-12, and the low byte is day 1-31. The recommended factory recalibration interval for the V490 is one year. -
Page 31: Macro, Paramx - Macro Controls
6.8 MACRO, PARAMx - Macro Controls The macro control register allows the execution of microprocessor routines which perform calibration and test tasks. Some macros also take a parameter in the PARAM0 register. PARAM1 and PARAM2 are currently unused. To execute a macro, verify that the MS bit (bit 15) of the MACRO register is clear, then write any required parameter into PARAM0 and then write a macro code to the MACRO register. -
Page 32: Vmetrig - Vme Trigger Register
6.10 VMETRIG - VME Trigger Register Writing anything to the VMETRIG register creates a module internal VME Trigger pulse. This register always reads back all zeroes. See section 8. 6.11 TRIGGER, BOUNCE, M - Global Trigger Controls The TRIGGER register selects the module operating modes that control simultaneous triggering of ADC data in a single module or across multiple modules. -
Page 33: Channel Registers
6.13 Channel Registers Each of the 16 A/D channels has a block of 7 associated registers. 6.13.1 Channel Control Register Each of the 16 input channels has a channel control register, CTL0 through CTL15. RN2 RN1 The RN bits select the input range for this channel, with the three RN bits encoded 0 through 6 decimal. -
Page 34: Filter Control Register
6.13.2 Filter Control Register Each of the 16 input channels has a user-writable filter control register, FILT0 through FILT15. The low byte controls the digital lowpass filter in the realtime data path, the path from the ADC to the RDATn realtime data register. The high byte controls the filter from the ADC into the FIFO, data from which appears at the FDATnA and FDATnB registers. - Page 35 F Code Cutoff Frequency 800 Hz 1 KHz 1.6 KHz 2 KHz 4 KHz 5 KHz 8 KHz 10 KHz 16 KHz 20 KHz 40 KHz 50 KHz reserved reserved 100 KHz Selection 31, 100 KHz, disables digital filtering and uses only the 100 KHz 5-pole analog filter ahead of the ADC.
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Page 36: Fifo Status Register
example a 4 KHz or lower filter for a 10 KHz sample rate. For Bessel filters, a filter cutoff frequency of 0.25 or less of the sample rate is appropriate. 6.13.3 FIFO Status Register Each of the 16 ADC channels has a FIFOn register which reports the state of the channel FIFO buffer. -
Page 37: Channel Realtime Data Registers
6.13.5 Channel Realtime Data Registers Each of the 16 input channels has a realtime data register RDATn. This register is loaded with lowpass-filtered data sampled at the 500 KHz ADC sample rate, and may be read at any time. The value is interpreted as a signed 16-bit integer which spans the full bipolar range of the current ADC range. -
Page 38: Realtime Considerations
6.14 Realtime Considerations When programming the V490, some VME register writes are serviced in FPGA hardware and some are processed through the on-board microprocessor. Registers tagged # in the register listing are hardware processed and their functions take place immediately when a register is written. -
Page 39: Bist
BIST All V490 units are capable of connecting one or more channel inputs to the front- panel D9 test connector. This allows users to apply known voltages to the channels and verify calibration. This facility is controlled by the MODE and RELAYS registers, as noted in sections 6.3 and 6.5. -
Page 40: Single-Channel Self-Test
CER indicates insufficient common-mode rejection on any range. Full BIST also runs the power supply self-test, reporting supply voltages, updating the VPERR error flags register, and counting any supply errors in BERN. See 7.4. 7.2 Single-channel Self-Test To test a single channel, verify that the MS bit of the MACRO register is clear, then write the channel number (0..15) to the PARAM0 register, then write 0x8408 to the MACRO register. - Page 41 TONE25 positive input 8000 TONE26 negative input -8000 TONE27 CMRR...
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Page 42: Background Bist Mux Function
7.3 Background BIST MUX function On V490-2 modules, when a BIST macro operation is not active, users may control the BIST voltage generator, which allows a selection of signals to be applied to the internal calibration bus. The MODE register controls signal routing when an automatic BIST sequence is not active;... - Page 43 The selected test bus voltages will be accurate to about ±0.25%. Selections 0, 13, 14, and 15 apply the same voltage to the differential CAL+ and CAL- bus lines and short the lines to one another with a low-offset solid-state relay.
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Page 44: Power Supply Bist
7.4 Power Supply BIST The V490 has provision for monitoring its internal power supply voltages. The power supplies are checked when the full BIST test (macro 0x8401) is executed. These tests can also be invoked with the 0x8409 macro. The PERR register flags power supply voltage errors, and the EP17..EM17 registers report actual supply voltages. -
Page 45: Local And Global Triggering
Local and Global Triggering Each V490 channel is capable of emulating a classic ADC architecture: preamp, lowpass filter, triggered ADC, FIFO. The actual implementation uses a 16-bit ADC that runs continuously at 500 KHz, a digital filter, and a digital interpolator, with FIFO data sampled at the instant a trigger is received. - Page 46 SMB as the master trigger source. SLAVE MTRIG is received from the SMB trigger connector, from a user trigger pulse or from another V490 which is in master mode. SLAVE TERM Like 5 above, but the SMB trigger input signal is also electrically terminated, 50 ohms to 1.6 volts.
- Page 47 MTRIG source in trigger modes 2 and 4. The resulting trigger frequency is 500K/(M+1). In configuring a master/slave system, the V490 modules are preferentially physically contiguous in the VME crate, with the master on the left and the terminating slave in the rightmost slot.
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Page 48: Typical Performance
Typical Performance 9.1 Analog Filter The analog anti-aliasing filter before the A/D converter is a 5-pole transitional Gaussian lowpass with a 3 dB point of 100 KHz. It is down about 60 dB at 400 KHz, the first major alias. The combination of pre-ADC analog filtering and post- ADC digital filtering is basically alias free. -
Page 49: Digital Filters
9.2 Digital Filters Each channel has two independent 8-pole programmable digital filters, one for the realtime data path and one for the FIFO data path. Each is selectable to have Bessel (best phase response) or Butterworth (best frequency rolloff) response, and each is programmable in steps from 1 Hz to 50 KHz. - Page 50 The graph below compares the step responses of 1KHz Bessel and Butterworth filters, as digitized and FIFO buffered by a V490. The Butterworth has superior frequency rolloff at the expense of time-domain overshoot. The Butterworth is actually a closer approximation of a mathematically ideal "brickwall" lowpass filter.
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Page 51: Interpolation
Sample From an external, asynchronous trigger, the equivalent ADC sample-and-hold aperture jitter typically measures about 4.1 nanoseconds RMS. This represents the statistical timing error of the V490 from an external trigger, as compared to an ideal triggered sample-and-hold and ADC. - Page 52 The V490 was externally triggered at 333 KHz, and the analog input to both channels was a 20 KHz sine wave. Again, the interpolation algorithm allows the input signal to be accurately sampled at external trigger times.
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Page 53: Noise Performance
9.4 Noise Performance The following graph shows equivalent shorted-input RMS noise, expressed in realtime register LSBs, as a function of channel range and filter bandwidth. To convert these values to volts, multiply by the specified range full-scale value and divide by 32768. For example, on the 40 millivolt range, with 1 KHz filtering selected, noise is 0.6 bits, or 0.75 microvolts RMS. -
Page 54: Versions
Versions The following are the standard V490 versions: V490-1 16-channel VME multi-range digitizer V490-2 16-channel VME multi-range digitizer with BIST Customization Consult factory for information about additional custom versions. Hardware and Firmware Revision History 12.1 Hardware Revision History Revision D... -
Page 55: Accessories
For Rev B Hardware (Interim release of the firmware for the V490 rev B) Uses FPGA 22C491A Partially functional: no filtering/FIFO, no power supply BIST The firmware is provided as a plug-in EPROM chip which can be field upgraded. This chip is labeled "22E490-C".
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