Download
Share
Print this page
  1. Manuals
  2. Brands
  3. THine Manuals
  4. Extender
  5. THCV245 A
  6. Manual

THine THCV245 A Manual

Serdes transmitter with bi-directional transceiver
Hide thumbs

Advertisement

Quick Links

Download this manual
THCV245A_Rev.0.90_E
1
General Description
THCV245A is designed to support 1080p60 2Mpixel
uncompressed video data over 15m 100ohm
differential STP or single-end 50ohm Coaxial cable
with 4 in-line connectors between camera and
®
processor by V-by-One
THCV245A supports a MIPI CSI-2. Each CSI-2 data
lane can transmit up to 1.2Gbps/lane. Virtual channel
is supported.
THCV245A is particularly targeted to medical and
other applications requiring low power consumption.
One high-speed V-by-One® HS lane can transmit up
to 1080p60fps. The maximum serial data rate is
4Gbps/lane. 2nd output lane supports HDR large
amount of data or data copy-and-distribution
experience.
THCV245A is capable to control and monitor
camera module from remote ECU via GPIO, UART or
1Mbps 2-wire serial interface.
Several fault and error detection function including
CRC provides hardware functional safety design.
3
Block Diagram
Copyright©2020 THine Electronics, Inc.
Preliminary
THCV245A
SerDes transmitter with bi-directional transceiver
HS.
MIPI CSI-2
Rx 4-lane
RD3p
RD3n
RD1p
RD1n
RCKp
RCKn
RD0p
RD0n
RD2p
RD2n
CKI
Settings
Controls
GPIO
2-wire
serial I/F
2
Features
MIPI CSI-2 with 1,2 or 4-lane input
MIPI D-PHY supports 80Mbps~1.2Gbps
MIPI Virtual channel supported
Video formats: RAW8/10/12/14/16/20,
YUV422/420, RGB888/666/565, JPEG, User-
defined generic 8-bit
®
V-by-One
®
V-by-One
Reference clock input CKI range 10~40MHz
shareable with video source CMOS sensor
Wide range IO voltage from 1.7V to 3.6V
Additional spread spectrum to reduce EMI
2-wire serial interface 1Mbps bridge function
Remote GPIO/UART control and monitoring
Error detection including CRC and notification
Low Current Consumption
QFN40 5x5mm 0.4mm pitch Exp-pad package
THCV245A
OSC
1/67
HS 400Mbps~4Gbps x2lane
HS standard version1.5
V-by-One® HS
Tx 2 lane
TX0N
TX0P
TX1N
TX1P
Sub-Link
TCMN
TCMP
THine Electronics, Inc.
Security C

Advertisement

loading
Need help?

Need help?

Do you have a question about the THCV245 A and is the answer not in the manual?

Questions and answers

Summary of Contents for THine THCV245 A

  • Page 1 V-by-One® HS THCV245A Rx 4-lane Tx 2 lane RD3p RD3n TX0N TX0P RD1p RD1n TX1N RCKp TX1P RCKn RD0p RD0n RD2p RD2n Sub-Link TCMN Settings TCMP Controls GPIO 2-wire serial I/F THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. 1/67 Security C...
  • Page 2 2-wire serial interface ..........................32 6.17.1 2-wire serial I/F slave Device ID ....................32 6.17.2 2-wire serial Read/Write access to local Register ................33 6.18 2-wire serial I/F Watch Dog Timer ......................34 THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 2/67...
  • Page 3 11.4 2-wire serial Master/Slave AC Specifications ..................64 Package ..............................66 Notices and Requests ..........................67 MIPI is a licensed trademark of MIPI, Inc. in the U.S. and other jurisdictions. THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 3/67...

  • Page 4: Pin Configuration

    30 29 28 27 26 25 24 23 22 21 RD3P THCV245A VDDA RD3N TX0N RD1P 41 EXPGND TX0P RD1N TX1N RCKP TX1P RCKN TEST RD0P TCMN RD0N TCMP RD2P PDN1 RD2N VDDB THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 4/67...
  • Page 5 Exposed Pad Ground : Must be tied to Ground *type symbol MI=MIPI Input, CO=CML Output CB=CML Bi-directional input/output B=1.8~3.3V CMOS Bi-directional input/output, I=1.8~3.3v CMOS Input, O=1.8~3.3v CMOS Output P=Pow er, G=Ground THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 5/67...

  • Page 6: Functional Description

    On the other hand, additional clock buffer may become another EMI emission source as trade-off. CMOS Sensor THCV245 A MCLK can be long (good) large structure available (bad) rather high EMI emission Figure 2. Reference clock supply clock buffer method (optional) THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 6/67...
  • Page 7 MIPI Data Lane Enable 0x102D R_RX_DATALANE_EN 0:Disable 1'h0 1:Enable, follow ing R_RX_LANE_SEL_EN MIPI Valid Data Lane number select 00:1Lane (lane0 Enable) 0x102D [1:0] R_RX_LANE_SEL_EN 2'h3 01,10:2Lane (lane<1:0> Enable) 11:4Lane (lane<3:0> Enable) THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 7/67...
  • Page 8 R_LOCKN0_SEL 2'h0 00:Sub-Link, 01:LOCKN pin input, 10:forced Low , 11:forced High V-by-One® HS LOCKN for lane1 assignment 0x101E [1:0] R_LOCKN1_SEL 2'h0 00:Sub-Link, 01:LOCKN pin input, 10:forced Low , 11:forced High THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 8/67...
  • Page 9 Main-Link MPRF format CMOS Sensor Original THCV245A THCV242 Preserved Processor Data packet Data packet In ECU or (format, (format, controller payload, etc.) payload, etc.) Figure 4. MPRF (Main-Link PRivate Format) THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 9/67...
  • Page 10 Y[3](1st)/Y[3](2nd) Cb(U)[3]/Cr(V)[3] Cb(U)[3]/Cr(V)[3] RAW[3] (2nd) Cr(V)[3] Y[3](2nd) V-by-One®HS_D[2] Y[2](1st)/Y[2](2nd) Cb(U)[2]/Cr(V)[2] Cb(U)[2]/Cr(V)[2] RAW[2] (2nd) Cr(V)[2] Y[2](2nd) V-by-One®HS_D[1] Y[1](1st)/Y[1](2nd) Cb(U)[1]/Cr(V)[1] Cb(U)[1]/Cr(V)[1] RAW[1] (2nd) Cr(V)[1] Y[1](2nd) V-by-One®HS_D[0] Y[0](1st)/Y[0](2nd) Cb(U)[0]/Cr(V)[0] Cb(U)[0]/Cr(V)[0] RAW[0] (2nd) Cr(V)[0] Y[0](2nd) THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 10/67...
  • Page 11 RAW[1] (2nd) V-by-One®HS_D[2] RAW[2] (3rd) R[2] R[2] (2nd) RAW[4] RAW[4] (2nd) RAW[0] (2nd) V-by-One®HS_D[1] RAW[1] (3rd) R[1] R[1] (2nd) RAW[3] RAW[3] (2nd) V-by-One®HS_D[0] RAW[0] (3rd) R[0] R[0] (2nd) RAW[2] RAW[2] (2nd) THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 11/67...
  • Page 12 RAW[0] (2nd) RAW[6] (2nd) RAW[2] (2nd) V-by-One®HS_D[1] RAW[5] RAW[5] (2nd) RAW[1] (2nd) RAW[3] (2nd) RAW[5] (2nd) RAW[1] (2nd) V-by-One®HS_D[0] RAW[4] RAW[4] (2nd) RAW[0] (2nd) RAW[2] (2nd) RAW[4] (2nd) RAW[0] (2nd) THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 12/67...
  • Page 13 Y[2](1st) Cr(V)[2] RAW[2] (4th) Cr(V)[2] (4th) Y[2] (4th) V-by-One®HS_D[1] Y[1] (2nd) Y[1](1st) Cr(V)[1] RAW[1] (4th) Cr(V)[1] (4th) Y[1] (4th) V-by-One®HS_D[0] Y[0] (2nd) Y[0](1st) Cr(V)[0] RAW[0] (4th) Cr(V)[0] (4th) Y[0] (4th) THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 13/67...
  • Page 14 R[2] (4th) RAW[4] (2nd) RAW[4] (4th) RAW[0] (4th) V-by-One®HS_D[1] RAW[1] (7th) R[1] (2nd) R[1] (4th) RAW[3] (2nd) RAW[3] (4th) V-by-One®HS_D[0] RAW[0] (7th) R[0] (2nd) R[0] (4th) RAW[2] (2nd) RAW[2] (4th) THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 14/67...
  • Page 15 RAW[6] (4th) RAW[2] (4th) V-by-One®HS_D[1] RAW[5] (2nd) RAW[5] (4th) RAW[1] (4th) RAW[3] (4th) RAW[5] (4th) RAW[1] (4th) V-by-One®HS_D[0] RAW[4] (2nd) RAW[4] (4th) RAW[0] (4th) RAW[2] (4th) RAW[4] (4th) RAW[0] (4th) THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 15/67...
  • Page 16 V-by-One® HS setting 00 : Reserved 0x101B [5:4] R_NHSEL 01 : Reserved 2'h3 10 : V-by-One® HS standard Low Radiation Emission mode 11 : V-by-One® HS standard High Immunity Resistance mode THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 16/67...
  • Page 17 Low Frequency mode format decoder like THCV236-Q. Table 15. V-by-One® HS Low Frequency Mode setting Addr(h) Bits Register w idth Description Default V-by-One® HS Low FeqModeEnable 0x101B R_LFQEN 0:Normal 1'h0 1:Low Frequency Mode THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 17/67...
  • Page 18 Another alternative is simply to use 160Mbps and higher MIPI data-rate because cases to use below 160Mbps must be the cases of [nmp]=4 so that MIPI data-rate can be arranged to be higher by using [nmp]=1 or 2 configuration. THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 18/67...
  • Page 19 Pixel clock frequency made by PLL is calculated as below. Actual Pixel clock, F(OUT) frequency must be equal or greater than ideal target Pixel clock, F(target) by 8% accuracy as below formula for most cases. THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 19/67...
  • Page 20 F(OUT) setting is not equal to F(target) if Spread Spectrum function is activated. F is supposed to be more than absolute value of applied SSCG modulation rate, |R_SPREAD|, under the condition specified on PLL constraints table. THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 20/67...
  • Page 21 0x00 0x44 0x01 1080p120fps RAW 891Mbps x4lane 2lane RAW12HF Map2 37.125 0x20 0x00 0x00 0x00 0x44 0x01 1080p120fps YUV422 1200Mbps x4lane 2lane YUV422HF Map1 0x32 0x00 0x00 0x00 0x44 0x01 THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 21/67...
  • Page 22 Register w idth Description Default PLL Auto Setting control invalid indicator 0x112F C_PLL_SET_NG 0: PLL Auto Setting control valid or PLL Manual setting mode 1: PLL Auto Setting control invalid THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 22/67...
  • Page 23 30kHz +/-0.5% are exemplified below. Table 22. V-by-One® HS output SSCG R_DIVVAL setting examples (MHz) (hex.) (dec.) (kHz) F(CKI) R_DIVVAL R_DIVVAL fmod 37.125 4'hC(0xC) 24.2 4'h8(0x8) 26.4 4'h8(0x8) 23.4 THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 23/67...
  • Page 24 CRC monitor like THCV242. Table 23. V-by-One® HS CRC setting Addr(h) Bits Register w idth Description Default V-by-One® HS CRC generator ON/OFF (ON default) 0x1054 R_CRC_OFF 0:CRC output ON 1'h0 1:CRC output OFF THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 24/67...
  • Page 25 Pixel Clock @R_PHMODE = 2'b00 DATA DATA @R_PHMODE = 2'b01 DATA PH3 1pixel DATA @R_PHMODE = 2'b10/11 DATA DATA Figure 6. MIPI Packet Header V-by-One® HS output bridge timing alternative THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 25/67...
  • Page 26 When MIPI PH(Packet Header) is bridged to V-by-One® HS output with described schemes above, MIPI Virtual Channel information in PH is bridged to V-by-One® HS at the same time. Virtual Channel is supported. THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 26/67...
  • Page 27 Internally generated ( For example, R_VSYNC_POL=0 ) V-by-One® HS VSYNC calculatedVS-HTOTAL = R_VS_WIDTH_PIX x 16 x PCLK calculatedVS-HTOTAL x R_VS_OFFSET(=m) calculatedVS-HTOTAL x R_VS_WIDTH_LINE(=n) Figure 8. Internally generated VSYNC THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 27/67...
  • Page 28 HSYNC mode1 2 x PCLK 2 x PCLK 2 x PCLK Internally R_HS_MODE=11 ( For example, R_HSYNC_POL=0 ) generated HSYNC mode2 Figure 9. Internally generated HSYNC in Vertical active period THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 28/67...
  • Page 29 ( For example, R_HS_MODE=10 ) V-by-One® HS HSYNC calculatedVS-HTOTAL = R_VS_WIDTH_PIX x 16 x PCLK calculatedVS-HTOTAL x R_HS_VB_NUM(=k) in V blanking period Figure 10. Internally generated HSYNC in Vertical blanking period THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 29/67...
  • Page 30 (FE3) (FE4) BYTE3 @R_FS_FE_SYNCEN=01 / R_VS_MODE=0 / R_VSYNC_POL=1 Vsync BYTE0 BYTE1 BYTE2 (FS1) (FS2) (FS3) (FS4) (FE1) (FE2) (FE3) (FE4) BYTE3 Figure 11. MIPI Short Packet V-by-One® HS bridge timing THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 30/67...
  • Page 31 Preliminary THCV245A_Rev.0.90_E m ipi Short Packet Vx1 Short Packet Figure 12. MIPI Short Packet V-by-One® HS bridge bit mapping THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 31/67...
  • Page 32 0: 2WIRE slv device addr. is set by AIN pin 8'd0 1: 2WIRE slv device addr. is set by follow ing register [6:0] [6:0]2WIRE slave device address value for register control THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 32/67...
  • Page 33 Figure 13. Host to THCV245A local register access configuration Figure 14. 2-wire serial I/F write to THCV245A local register protocol Figure 15. 2-wire serial I/F read to THCV245A local register protocol THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 33/67...
  • Page 34 1: Interrupt (error is detected) Interrupt mask: Internal register CheckSum error 0x0061 0x00E1 R_INTM_CKSUM_ERR 1'b0 0: Interrupt mask Interrupt clear: Internal register CheckSum error 0x0062 0x00E2 R_INTC_CKSUM_ERR 1: Interrupt clear THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 34/67...
  • Page 35 Sublink SSR Enable 0x0016 R_SLINK_SSR_EN 0:Disable 1'b1 1:Enable 0x0016 [1:0] R_SLINK_SSR_TIM_UP Sublink SSR interval setting 2'd0 Sublink SSR interval time=64×(256× R_SLINK_SSR_TIM_UP<1:0> 0x0017 [7:0] R_SLINK_SSR_TIM_DN +R_SLINK_SSR_TIM_DN<7:0>+1)×tOSC 8'd249 *No SSR when R_SLINK_SSR_TIM_UP=0 and R_SLINK_SSR_TIM_DN=0 THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 35/67...
  • Page 36 2Byte access to 0x00FE, being independent of “Word Address Bank MSB setting” (0x00FE bit[6:4]). This procedure enables users to reset Word Address Bank MSB setting on 1Byte Word Address access and Word Address Byte number setting itself. THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 36/67...
  • Page 37 Triggered access by Sub-Link Master Access from/to HOST MSSEL=1 MSSEL=0 AIN = User Select Figure 17. Host MPU to 2-wire slave devices connected to Sub-Link Slave via THCV245A access configuration THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 37/67...
  • Page 38 When R_2WIRE_CLKSEN = 0, Sub-Link Master device informs HOST MPU that Sub-Link Slave register access or remote side 2-wire serial register access has completed by interruption (detectable on INT pin) without clock stretching. Figure 18. Sub-Link Master 2-wire slave clock stretching operation THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 38/67...
  • Page 39 16×{R_2WIRE_SCL_HW<7:0>+1} * tOSC SCL Low w idth [tLOW] setting on Sub-Link Slave side. 0x00CA [7:0] R_2WIRE_SCL_LW Output SCL Low w idth is defined as below . 8'd31 16×{R_2WIRE_SCL_LW<7:0>+1} * tOSC THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 39/67...
  • Page 40 0x0018 0x0098 R_SLINK_WD_EN 0:Disable 1'b1 1:Enable 0x0018 0x0098 [3:2] reserved 0x0018 0x0098 [1:0] R_SLINK_WD_TIM_UP Sublink WDT time parameter 2'd0 Sublink WDT time =64×(256×R_SLINK_WD_TIM_UP<1:0> + 0x0019 0x0099 [7:0] R_SLINK_WD_TIM_DN 8'd187 R_SLINK_WD_TIM_DN<7:0>+1) ×tOSC THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 40/67...
  • Page 41 Sub-Link Slave side factor  remote 2-wire access on Sub-Link end Detectable interrupts as Sub-Link Slave are as follows.  Sub-Link Slave 2-wire master bus clear end  Sub-Link Slave 2-wire NACK detection THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 41/67...

  • Page 42: Gpio Setting

    As default setting with THCV242 or THCV244 as Sub-Link Master communication (THCV245A as Sub-Link Slave), GPIO1/0 Sub-Link Polling bridges output from THCV242 or THCV244-GPIO Through Mode and GPIO3/2 Sub-Link Polling bridges input to THCV242 or THCV244-GPIO Through Mode respectively. THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 42/67...
  • Page 43 Remote UART bridge is supported with Sub-Link Polling GPIO input/output. Remote UART Tx and Rx bridge baud rate is supposed to be designed against Sub-Link Polling interval to accommodate deterministic jitter caused by intermittent Sub-Link communication timing. THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 43/67...
  • Page 44 0x1121 [3:0] R_GPIO_INT_DETECT 0:No Interrupt 1:Interrupt (detect for asserted or negated of GPI Input) Interrupt Clear for GPI [3]:GPIO3, [2]:GPIO2, [1]:GPIO1, [0]:GPIO0 0x1122 [3:0] R_GPIO_INTC_DETECT 0:Interrupt No Clear 1:Interrupt Clear THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 44/67...
  • Page 45 MIPI FRAMESYNC FS/FE position error 4'b1000 reserved 4'b1001 MIPI Control state error 4'b1010 MIPI FS 4'b1011 MIPI FE 4'b1100 reserved 4'b1101 reserved 4'b1110 Main-Link Data Handle error 4'b1111 PLL auto configuration setting error THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 45/67...
  • Page 46 MIPI R_RX_ECC_ERR_CRCT_CNT[15:0] R_ECC_ERR_CRCT_CNT_CLR ECC2bit error count by every Line MIPI R_RX_ECC_ERR_DBLE_CNT[15:0] R_ECC_ERR_DBLE_CNT_CLR Sub-link Feald BET error count Sub-Link R_SLINK_FBETERR_NUM_*[15:0] R_SLINK_FBETERR_CLR *H:Enable L:Disable, which is defferent polarity from other mask registers THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 46/67...
  • Page 47 [IO] INT CMOS/OpenDrain Select 0x1041 R_INT_CMOSEN 0:OpenDrain 1'h0 1:CMOS INT interrupt function is supposed to be cleared before start monitoring any desired status because INT status may have been changed before monitoring activation. THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 47/67...
  • Page 48 _EXTERNAL _SLAVESIDE Module Register Interrupt signal Register Register Interrupt monitor by Sub-Link Master Access from/to HOST MSSEL=1 MSSEL=0 AIN = User Select Figure 20. Interrupt configuration external of Sub-Link module. THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 48/67...
  • Page 49 1'h0 Hbackporch pixel number = "R_HBP_V" x4 BIST Hbackporch pixel number setting 0x1071 [7:0] R_HBP_V[7:0] 8'h28 Hbackporch pixel number = "R_HBP_V" x4 0x1072 [6:0] R_VBP_V BIST Vbackporch line number 7'h10 THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 49/67...
  • Page 50 Horizontal RGBW ramp × reserved × Vertical RGBW ramp × reserved × ○ 16×16 pi×el checker reserved × ○ Frame reserved × ○ Sub pixel checker reserved × reserved × reserved × THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 50/67...
  • Page 51 [5:4] 10 : GPIO2 BETOUT 01 : GPIO2 LATEN 11,00 : Don't Care 8'h06 [3:2] 10 : GPIO1 BETOUT 01 : GPIO1 LATEN 11,00 : Don't Care [1:0] 10 : GPIO0 BETOUT 01 : GPIO0 LATEN 11,00 : Don't Care THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 51/67...
  • Page 52 R_GPIO_TDRV 4'h0 0: Normal Drive(4mA) 1: Strong Drive(8mA) CMOS IO Drive Strength Select [6]:INT, [3]:CKO, [1]:SDA, [0]:SCL 0x1047 [6:0] R_IO_DRV[7:0] [5], [4], [2]:ReservedL 7'h00 0: Normal Drive(4mA) 1: Strong Drive(8mA) THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 52/67...
  • Page 53 CKO reference clock buffer output can be configurable by 2-wire access to internal register. Table 50. CKO setting Addr(h) Bits Register w idth Description Default CKO output source select 0x1076 R_CKOSTOP 1'h1 0:CKI, 1: Low fix THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 53/67...

  • Page 54: Soft Reset

    00 Disable(Disable Auto Soft Reset) 01 1*256*tOSC (typ.3.2us) 02 2*256*tOSC (typ.6.4us) 0x105C [7:0] R_TX_CTERM 8'h55 03 3*256*tOSC (typ.9.6us) ： ： FE 254*256*tOSC (typ.812.8us) FF 255*256*tOSC (typ.816us) THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 54/67...
  • Page 55 R_PLL_SET_MODE=0 and R_PLL_SET_MODE=1, R_SPREAD R_DISABLE_SSCG The registers that may trigger V-by-One® HS automatic Soft Reset are as follows. R_NHSEL R_LFQEN R_ML0_PRE R_ML1_PRE R_ML0_DRV R_ML1_DRV R_COL_SEL R_COL_MAN[1:0] R_OUTPUT_FMT R_HFSEL R_BITMAP_SEL THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 55/67...

  • Page 56: Power On Sequence

    Required w ait from CKI input to PLL Enable 1000 Required w ait from PLL Lock Time to CML output F(CKI) tTPLL0 V-by-One® HS Reset Release to CML Out Delay THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 56/67...
  • Page 57 Figure 23. Re-Lock Sequence Table 54. Lock / Re-Lock Sequence specification Symbol Parameter Unit tTNP0 LOCKN=H to Training pattern output delay 1200 tTNP1 LOCKN=L to Data pattern output delay F(OUT) THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 57/67...

  • Page 58: Absolute Maximum Ratings

    Recommended Operating Conditions Symbol Parameter Condition Unit 3.3V Drive VDDH Supply Voltage (VDDIO, VDDB) 2.5V Drive 1.8V Drive VDD12 Supply Voltage 1.2V (VDDM, VDDOP, VDDL, VDDA) Operating Ambient Temperature degC THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 58/67...

  • Page 59: Consumption Current

    MIPI = 600Mbps x1Lane Sub-Link : active V-by-One® HS = 750Mbps x1Lane Main-link :1080p60fps PDN0=1, PDN1=1 ICCW12_18 MPRF(RAW) MIPI = 891Mbps x2Lane Sub-Link : active V-by-One® HS = 2227.5Mbps x1Lane THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 59/67...
  • Page 60 Vterm-en HS mode for HS termination enable mipi D-PHY differential input impedance HS mode mipi D-PHY Single-end input high thres. LP mode mipi D-PHY Single-end input low thres. LP mode THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 60/67...
  • Page 61 R_ML*_PRE[1:0]=01 VDDA- 1.5*VTOD R_ML*_PRE[1:0]=10 VDDA- 2*VTOD ITOZH CML Output Leak Current High R_TX_SNRST=1 ITOZL CML Output Leak Current Low R_TX_SNRST=1 R_TX_SNRST=0 ITOS CML Output Short Circuit Current or PDN0=0 VDDA=1.20v THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 61/67...
  • Page 62 R_BDCZ_TERM_TX/ RX [1:0]=2'b10 CML Bi-Directional Buffer R_BDCZ_TERM_TX/ RX RTERM Termination Registance [1:0]=2'b01 R_BDCZ_TERM_TX/ RX [1:0]=2'b00 R_BDCZ_DRIVE_TX/ RX [1:0]=2'b10 CML Bi-Directional Buffer R_BDCZ_DRIVE_TX/ RX IDRIVE Drive Current [1:0]=2'b01 R_BDCZ_DRIVE_TX/ RX [1:0]=2'b00 THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 62/67...
  • Page 63 Figure 25. CML Transmitter tTRF 11.3 CML B-directional Buffer AC Specifications Table 64. CML B-directional Buffer AC Specifications Symbol Parameter Condition Unit REG0x0076/F6 tBUI Bi-Directional CML Buffer Unit Interval 128.7 137.5 172.7 = 0x15 THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 63/67...
  • Page 64 Fall time of both SDA and SCL signals bus capacitance : 400pF tSU;STO Setup time for STOP condition 0.26 *1 Please adjust Pull-up resistor and bus capacitance to meet the spec value. THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 64/67...
  • Page 65 Preliminary THCV245A_Rev.0.90_E Figure 26. 2-wire serial interface timing diagram THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 65/67...
  • Page 66 0.90 Max 0.65 0.20 5.00 0.05 Max 1 PIN INDEX TOP VIEW SIDE VIEW EXPOSED PAD OPENING 3.70 0.075 PIN1 ID 0.20 R 0.40 0.40 0.20 Unit : mm BOTTOM VIEW THine Electronics, Inc. Copyright©2020 THine Electronics, Inc. Security C 66/67...
  • Page 67 THine Electronics, Inc. (“THine”) is not responsible for possible errors and omissions in this material. Please note even if errors or omissions should be found in this material, THine may not be able to correct them immediately.