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Figure 3-41
Invalid Loop Bandwidth Selection
3.2.6.5
Input Impedance
Figure 3-42 depicts bit synchronizer input impedance selection (Input Z). Low input impedance (LO
Z) is 75 ohms. High input impedance (HI-Z) is 4K ohms.
Figure 3-42
Bit Synchronizer Input Impedance Selection
3.2.7 BERT Control Panel
Figure 3-43 depicts the BERT Control Panel. BERT Status indicates BERT OFF,
SYNC
or
LOSS
status.
The Seconds indicator counts and indicates the BERT test interval in seconds. Current BER displays
the current BER. AVG BER indicates the average BER for the test interval. Total Errors indicates the
total number of bit errors during the test interval.
A2538-003/01 March 2020
32
SEMCO Proprietary Information
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