1. Manuals
  2. Brands
  3. SiTime Manuals
  4. Power Tool
  5. SiT15 Series
  6. Manual

SiTime SiT15 Series Manual

Optimized drive settings for 32 khz crystal inputs of low power mcus
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
Optimized SiT15xx Drive Settings for
32 kHz Crystal Inputs of Low Power MCUs
1
Introduction ............................................................................................................................................ 2
2
MCU 32 kHz Oscillator Operating Modes .............................................................................................. 2
3
SiT15xx Output Drive Levels ................................................................................................................. 4
3.1
NanoDrive Reduced Swing Mode ................................................................................................. 4
3.2
Full-Swing LVCMOS Drive ............................................................................................................ 5
4
Energy Micro EFM32 ............................................................................................................................. 6
5
STMicroelectronics STM32 .................................................................................................................... 6
6
Renesas Electronics RL78G13 .............................................................................................................. 7
7
Texas Instruments MSP430F2x ............................................................................................................ 7
8
NXP LPC11xx ........................................................................................................................................ 8
9
Freescale Kinetis L4x/L5x ...................................................................................................................... 8
10
Appendix A: Programming the EnergyMicro EFM32 LFXO .............................................................. 9
10.1
EFM32 Clock Management Unit ................................................................................................... 9
10.2
Configuring the LFXO ................................................................................................................. 12
11
11.1
Low-speed External Clock Oscillator .......................................................................................... 13
11.2
External Clock Source (LSE bypass) .......................................................................................... 14
11.3
Clock Security System on LSE ................................................................................................... 14
11.4
Clock-out Capability .................................................................................................................... 14
11.5
Configuring LSE .......................................................................................................................... 15
12
12.1
XT1 Oscillator .............................................................................................................................. 16
12.2
Configuration XT1 ....................................................................................................................... 16
13
13.1
The MSP430 LFXT Oscillator ..................................................................................................... 18
13.2
Clock-out Capability .................................................................................................................... 20
13.3
Low-power Modes ....................................................................................................................... 20
14
Appendix E: Programming the NXP LPC1100 RTC Oscillator ....................................................... 21
14.1
Configuring of the RTC Oscillator ............................................................................................... 21
14.2
Clock Output Capability ............................................................................................................... 21
15
15.1
Programming Model .................................................................................................................... 28
15.2
Clock Output Capability ............................................................................................................... 34
The Smart Timing Choice™

Table of Contents

1
Oct 2014
SiT-AN10037 Rev 1.3

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the SiT15 Series and is the answer not in the manual?

Questions and answers

Summary of Contents for SiTime SiT15 Series

  • Page 1: Table Of Contents

    Oct 2014 Optimized SiT15xx Drive Settings for 32 kHz Crystal Inputs of Low Power MCUs Table of Contents Introduction ............................2 MCU 32 kHz Oscillator Operating Modes ....................2 SiT15xx Output Drive Levels ......................... 4 NanoDrive Reduced Swing Mode ....................4 Full-Swing LVCMOS Drive ......................

  • Page 2: Introduction

    SiT15xx Optimized Drive Settings 1 Introduction Embedded microcontroller (MCU) based systems have historically relied on a low frequency 32.768 kHz quartz resonator driven oscillator for time keeping and failure recovery functions. TempFlat™ MEMS SiT153x oscillators and SiT155x temperature compensated oscillators (TCXOs) are a new generation of smaller footprint 32.768 devices that offer a cost effective, more reliable, improved frequency stability alternative to quartz-based 32.768 kHz oscillators.
  • Page 3 SiT15xx Optimized Drive Settings 32.768 kHz 32.768 kHz Oscillator Oscillator (Enabled) (Enabled) 250-800 mV XOUT XOUT CLK OUT SiT153x (Mode-1) Oscillator ON and driven by SiT153x NanoDrive output. C1 (Mode-1) Oscillator ON and driven by external quartz resonator and C2 are optional and can be removed for additional power savings 32.768 kHz 32.768 kHz Oscillator...

  • Page 4: Sit15Xx Output Drive Levels

    SiT15xx Optimized Drive Settings 3 SiT15xx Output Drive Levels The SiT15xx devices support two distinct output drive modes. 1. NanoDrive™ reduced swing, factory programmable 2. Rail-to-rail full-swing LVCMOS 3.1 NanoDrive Reduced Swing Mode In NanoDrive mode, the SiT15xx output driver achieves various voltage swings and common- mode bias voltages similar to drive levels sustained by various implementations of a 32 kHz quartz crystal driven Pierce oscillator.

  • Page 5: Full-Swing Lvcmos Drive

    SiT15xx Optimized Drive Settings VOH = 1.1V = 0.7V VOL = 0.4V Figure 3: Scope capture of a SiT15xxAI-H4-D14-32.768 output waveform in to a 15 pF load. 3.2 Full-Swing LVCMOS Drive SiT15xx families can be programmed to generate full-swing LVCMOS levels. Figure 4 shows the waveform of SiT15xxAI-H4-DCC-32.768, 1.8V VDD at room temperature in to a 15 pF load.

  • Page 6: Energy Micro Efm32

    SiT15xx Optimized Drive Settings 4 Energy Micro EFM32 The EFM32 family of microcontrollers is based on the ARM Cortex-M0, M3 or M4 processor core targeted for low power operation. The EFM32 incorporates a low frequency crystal driven oscillator (LFXO) for clocking on-chip peripherals (including RTC) and potentially the CPU core. The LFXO can operate from a 32.768 kHz quartz crystal connected across the LFXTAL_N and LFXTAL_P pins or an external clock source on the LFXTAL_P pin.

  • Page 7: Renesas Electronics Rl78G13

    SiT15xx Optimized Drive Settings 6 Renesas Electronics RL78G13 The R5F100LE is a 16-bit MCU based on the RL78 core. The MCU includes a low frequency crystal oscillator (XT1) that can be used for clocking peripherals (including RTC) and the core if necessary.

  • Page 8: Nxp Lpc11Xx

    SiT15xx Optimized Drive Settings 8 NXP LPC11xx The LPC1100 MCUs are Cortex-M0 based MCUs running at speeds up to 50 MHz. The Cortex- M0 processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of embedded applications. The MCU has several low power modes that enable to reach low power consumption with high performance in portable applications: Sleep Mode, Deep Sleep Mode, Power-Down Mode, and Deep Power-Down Mode.

  • Page 9: Appendix A: Programming The Energymicro Efm32 Lfxo

    SiT15xx Optimized Drive Settings 10 Appendix A: Programming the EnergyMicro EFM32 LFXO 10.1 EFM32 Clock Management Unit All on-chip oscillators are controlled by a Clock Management Unit (CMU). The CMU provides the capability to configure and turn on/off the clock on an individual basis to all peripheral modules.
  • Page 10 SiT15xx Optimized Drive Settings Table 11: CMU_OSCENCMD - Oscillator Enable/Disable Command Register Offset Bit Position 0x02C Reset Access Name Table 12: OSCENCMD - The [31:3] Field Descriptions Name Reset Access Description To ensure compatibility with future devices, Reserved 31:10 always write bits to 0. LFXODIS LFXO Disable Disables the LFXO.
  • Page 11 SiT15xx Optimized Drive Settings Table 13: CMU_STATUS - Status Register Offset Bit Position 0x02C Reset Access Name Table 14: CMU_STATUS - The [14:8] Field Descriptions Name Reset Access Description To ensure compatibility with future devices, always write 31:15 Reserved bits to 0. CALBSY Calibration Busy Calibration is on-going...

  • Page 12: Configuring The Lfxo

    SiT15xx Optimized Drive Settings 10.2 Configuring the LFXO Below is a code snippet of LFXO configuration from IAR Embedded Workbench IDE: 1. Enable the LFXO oscillator by setting the LFXOEN bit in the CMU_OSCENCMD[8] (Table 11) 2. Wait until the LFXORDY bit in the CMU_STATUS[9] (Table 13) is set. Applicable only for the XTAL mode, otherwise skip this step.

  • Page 13: Appendix B: Programming The Stmicroelectronics Stm32 Lse Oscillator

    SiT15xx Optimized Drive Settings 11 Appendix B: Programming the STMicroelectronics STM32 LSE Oscillator 11.1 Low-speed External Clock Oscillator The low-speed external (LSE) crystal oscillator can be switched on/off by setting/clearing the LSEON bit in the RCC_CSR[8] register. Table 15: Control/Status Register (RCC_CSR) LPWR WWDG IWDG...

  • Page 14: External Clock Source (Lse Bypass)

    SiT15xx Optimized Drive Settings CSSF RDYF RDYF RDYF RDYF RDYF RDYF RDYF 11.2 External Clock Source (LSE bypass) It is possible to connect an external clock source to OSC32_IN pin of the LSE oscillator. This feature is selected by setting the LSEBYP and LSEON bits in the RCC_CSR (Table 15). The external clock signal (square, sine or triangle) with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left unconnected (Hi-Z).

  • Page 15: Configuring Lse

    SiT15xx Optimized Drive Settings Table 17: Configuration Register (RCC_CFGR) MCOPRE[2:0] Res. MCOSEL[2:0] Res. PPRE2[2:0] PPRE1[2:0] Reserved PLLDIV[1:0] PLLMUL[3:0] Res. PPRE2[2:0] PPRE1[2:0] Reserved HPRE1[3:0] SWS[1:0] SW[1:0] Note: If the LSE or LSI is used as RTC clock source, the RTC continues to work in Stop and Standby low power modes, and can be used as wake-up source.

  • Page 16: Appendix C: Programming The Renesas Electronics Rl78G13 Xt1 Oscillator

    SiT15xx Optimized Drive Settings 12 Appendix C: Programming the Renesas Electronics RL78G13 XT1 Oscillator 12.1 XT1 Oscillator The XT1 oscillator is a circuit with low gain in order to achieve low-power consumption. There are AMPHS1[2], AMPHS0[1] fields in the CMC register (Table 20) that enables to choose optimal gain for a crystal.
  • Page 17 SiT15xx Optimized Drive Settings Table 20: CMC Register Symbol EXCLK OSCSEL EXCLKS OSCSELS AMPHS1 AMPHS0 AMPH EXCLK OSCSEL High-speed system clock pin X1/P121 pin X2/EXCLK/P122 pin operation mode Input port mode Input port X1 oscillation mode Crystal/ceramic resonator connection Input port mode Input port External clock input mode Input port...

  • Page 18: Appendix D: Programming The Texas Instruments Msp430 Low Frequency Oscillator

    SiT15xx Optimized Drive Settings 13 Appendix D: Programming the Texas Instruments MSP430 low frequency oscillator 13.1 The MSP430 LFXT Oscillator The LFXT1 oscillator supports ultra-low current consumption using a 32768 Hz watch crystal in LF mode (XTS = 0) or a high frequency crystal in HF mode. A watch crystal connects with the XIN and XOUT pins without any other external components.
  • Page 19 SiT15xx Optimized Drive Settings Table 22: BCSCTL3, Basic Clock System Control Register 3 Name XT2Sx LFXT1Sx XCAPx XT2OF LFXT1OF State rw-0 rw-0 rw-0 rw-0 rw-0 rw-1 r-(1) XT2 range select. These bits select the frequency range for XT2. XT2Sx Bits 7-6 0.4- to 1-MHz crystal or resonator 1- to 3-MHz crystal or resonator 3- to 16-MHz crystal or resonator...

  • Page 20: Clock-Out Capability

    SiT15xx Optimized Drive Settings 13.2 Clock-out Capability The microcontroller can be easily configured to clock external on-board peripherals from one of its pins. For this you need configure the PxSEL and PxSEL2 function registers that are used to select the pin function. A pin has to be configured as an output by setting needed in PxDIR. Below is code from IAR Embedded Workbench that configures it: P2SEL = P2SEL | 0x01;...

  • Page 21: Appendix E: Programming The Nxp Lpc1100 Rtc Oscillator

    SiT15xx Optimized Drive Settings 14 Appendix E: Programming the NXP LPC1100 RTC Oscillator 14.1 Configuring the RTC Oscillator The system clock block generates all clocks for the chip. The system block incorporates the low frequency RTC 32k oscillator. It provides a clock for the RTC block that resides in a separate always-on voltage domain with battery back-up.
  • Page 22 SiT15xx Optimized Drive Settings // 6) Set the RTC oscillator clock source as the clock source for the // LPC_SYSCTL->SYSPLLCLKSEL = 0x3; // 7) updated clock source for PLL LPC_SYSCTL->SYSPLLCLKUEN = 0; LPC_SYSCTL->SYSPLLCLKUEN = 1; // update clock source for the main clock domain LPC_SYSCTL->MAINCLKUEN = 0;...
  • Page 23 SiT15xx Optimized Drive Settings Table 27: System Clock Control SYSAHBCLKCTRL Symbol Value Description Reset Value This bit is read-only and always reads as 1. It configures the always-on clock for the AHB, APB bridges the Cortex-M0 core clocks, SYSCON, reset control, SRAM0, and the PMU.
  • Page 24 SiT15xx Optimized Drive Settings Symbol Value Description Reset Value Enables clock for SSP0. SSP0 Disable Enable Enables clock for USART0. USART0 Disable Enable Enables clock for ADC. Disable Enable Enables clock to the USB register interface. Disable Enable Enables clock for WWDT. WWDT Disable Enable...
  • Page 25 SiT15xx Optimized Drive Settings Symbol Value Description Reset Value Enables clock to GPIO GROUP1 interrupt register interface. GROUP1INT Disable Enable Enables clock for I2C1. I2C1 Disable Enable Enables clock for SRAM1 located at 0x2000 0000 to 0x2000 0800. RAM1 Disable Enable Enables USB SRAM/SRAM2 block located at 0x2000 4000 to 0x2000 4800.
  • Page 26 SiT15xx Optimized Drive Settings Table 29: Digital Pin Control Register IOCON (PIO0_1) Symbol Value Description Reset Value Selects pin function. PIO0_1 CLKOUT FUNC CT32B0_MAT2 USB_FTOGGLE 0x4..0x7 Selects function mode (on-chip pull-up/pull-down resistor control). Inactive (no pull-down/pull-up resistor enabled). MODE Pull-down resistor enabled. Pull-up resistor enabled.
  • Page 27 SiT15xx Optimized Drive Settings Table 30: CLKOUT Clock Source Select CLKOUTSEL Symbol Value Description Reset Value CLKOUT clock source IRC oscillator Crystal oscillator (SYSOSC) Watchdog oscillator Main clock 31:2 Reserved Table 31: CLKOUT Clock Divider CLKOUTDIV Symbol Value Description Reset Value CLKOUT clock divider values Disable CLKOUT clock divider.

  • Page 28: Appendix F: Programming The Freescale Kinetis L4X And L5X System Oscillator

    SiT15xx Optimized Drive Settings Table 34: Main Clock Source Update Enable Register MAINCLKUEN Symbol Value Description Reset Value Enable main clock source update No change Update clock source 31:1 Reserved Table 35: CLKOUT Clock Source Update Enable Register CLKOUTUEN Symbol Value Description Reset Value...
  • Page 29 SiT15xx Optimized Drive Settings Table 36: OSC Control Register (OSCx_CR) Symbol Value Description External Reference Enable. Enables external reference clock (OSCERCLK). ERCLKEN External reference clock is inactive. External reference clock is enabled. Reserved This read-only field is reserved and always has the value 0. External Reference Stop Enable.
  • Page 30 SiT15xx Optimized Drive Settings Table 33: MCG Control 2 Register (MCG_C2) Symbol Value Description Loss of Clock Reset Enable. Determines whether an interrupt or a reset request is made following a loss of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is set.
  • Page 31 SiT15xx Optimized Drive Settings Table 34: MCG Status Register (MCG_S) Symbol Value Description Reserved. This field is reserved. This read-only field is reserved and always has the value 0. Reserved Interrupt request is generated on a loss of OSC0 external reference clock. Generate a reset request on a loss of OSC0 external reference clock.
  • Page 32 SiT15xx Optimized Drive Settings Table 35: System Options Register 2 (SIM_SOPT2) Symbol Value Description This field is reserved. This read-only field is reserved and always has the 31-28 Reserved value 0. UART0 clock source select. Selects the clock source for the UART0 transmit and receive clock.
  • Page 33 SiT15xx Optimized Drive Settings Table 40: MCG Control 4 Register (MCG_C4) Symbol Value Description DCO Maximum Frequency with 32.768 kHz Reference. The DMX32 bit controls whether the DCO frequency range is narrowed to its maximum frequency with a 32.768 kHz reference. The following table identifies settings for the DCO frequency range.

  • Page 34: Clock Output Capability

    SiT15xx Optimized Drive Settings Below is the code example from CodeWarrior Development Studio showing configuration to be run with SiT1533AI-H4 in Mode-1. // 1) Enable external reference clock (OSCERCLK) and disable all the built-in load capacitors OSC0_CR = 0xA0; // 2) Configure MCG_C2. Set low frequency range for the crystal oscillator, low power mode and select external reference MCG_C2 &= ~(0x3C);...
  • Page 35 SiTime product and any product documentation.

Table of Contents