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Curtiss-Wright SCRAMNet+ SC150e Hardware Reference Manual

Pci, pmc & cpci bus (universal signaling)
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SC150e PCI, PMC & CPCI Bus
(Universal Signaling)
Hardware Reference
Document No. D-T-MR-PCPMCPE#-A-1-A4

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  • Page 1 SC150e PCI, PMC & CPCI Bus (Universal Signaling) Hardware Reference Document No. D-T-MR-PCPMCPE#-A-1-A4...
  • Page 3 PCI Industrial Computer Manufacturer’s Group Curtiss-Wright Controls, Inc., is an Associate Level member of PICMG and as such may use the PICMG and CompactPCI logos. Any reference made within this document to equipment from other vendors does not constitute an endorsement of their product(s).
  • Page 4 This product is intended for use in industrial, laboratory, or military environments. This product uses and emits electromagnetic radiation, which may interfere with other radio and communication devices. The user may be in violation of FCC regulations if this device is used in other than the intended market environments.

  • Page 5: Table Of Contents

    3.2 SCRAMNet+ SC150e Cards ....................3-1 3.2.1 SCRAMNet+ SC150e PCI Card................3-1 3.2.2 SCRAMNet+ SC150e PMC Card................3-2 3.2.3 SCRAMNet+ SC150e CPCI Card ................. 3-3 3.3 LED Status Indicators....................... 3-4 3.3.1 Insert LED ......................3-4 3.3.2 Carrier Detect LED....................3-4 3.4 Software ...........................
  • Page 6 4.7.3 Auxiliary Connection on SC150e PCI and CPCI..........4-14 4.7.4 Auxiliary Connection on SC150e PMC............... 4-14 4.8 Internal Configuration ......................4-15 4.8.1 SCRAMNet+ SC150e Control/Status Registers (CSR) ........4-15 4.8.2 SCRAMNet on DEC Computers ................. 4-16 4.8.3 EEPROM Initialization..................4-16 4.8.4 Node Identification ....................
  • Page 7 Figure 2-4 Incoming Interrupt........................2-8 Figure 3-1 SCRAMNet+ SC150e PCI Card....................3-1 Figure 3-2 SCRAMNet+ SC150e PMC Card....................3-2 Figure 3-3 SCRAMNet+ SC150e CPCI Card ....................3-3 Figure 3-4 Ring with Bypass Switches......................3-6 Figure 3-5 Node Inclusion and Isolation ......................3-6 Figure 4-1 PCI Layout (card revision B1)......................
  • Page 8 TABLES Table 4-1 PCI Auxiliary Connection Pinout ....................4-14 Table 4-2 PMC Auxiliary Connection Pinout ....................4-15 Table 4-3 SCRAMNet+ SC150e Control/Status Registers ................4-15 Table 4-4 EEPROM Table ........................... 4-16 Table 4-5 EEPROM Initialization ........................ 4-16 Table 4-6 Byte Ordering Comparisons......................4-17 Table 4-7 PCI_MAP0/PCI _MAP1 Swapping Options ................

  • Page 9: Introduction

    This document is a reference manual for the SCRAMNet+ SC150e PCI, PMC and CompactPCI network interface cards (NIC). It provides a physical and functional description of the SCRAMNet+ SC150e NIC and describes how to unpack, set up, install and operate the hardware. Hereafter in this manual “CompactPCI” is referred to as “CPCI.”...

  • Page 10: Related Information

    PROGREF) - A collection of routines to assist SCRAMNet users with application development. SCRAMNet Network Utilities User Manual (Doc. Nr. C-T-MU-UTIL) - A user’s • manual for the SCRAMNet Classic, SCRAMNet-LX, and SCRAMNet+ SC150e hardware diagnostic software, SCRAMNet+ SC150e EEPROM initialization software, and the SCRAMNet Network Monitor. •...

  • Page 11: Quality Assurance

    INTRODUCTION 1.3 Quality Assurance Curtiss-Wright Controls’ policy is to provide our customers with the highest quality products and services. In addition to the physical product, the company provides documentation, sales and marketing support, hardware and software technical support, and timely product delivery. Our quality commitment begins with product concept, and continues after receipt of the purchased product.

  • Page 12: Technical Support

    World Wide Web address: www.cwcembedded.com 1.5 Ordering Process To learn more about Curtiss-Wright Controls’ products or to place an order, please use the following contact information. Hours of operation are from 8:00 a.m. to 5:00 p.m. Eastern Standard/Daylight Time. •...

  • Page 13: Scramnet Overview

    SCRAMNet+ SC150e memory is automatically sent to the same SCRAMNet+ SC150e memory location in all nodes on the network. This is why it is also referred to as replicated shared memory. A good analogy is the COMMON AREA used by the FORTRAN programming language.

  • Page 14: Figure 2-1 Functional Diagram

    SCRAMNET OVERVIEW Figure 2-1 Functional Diagram Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 15: Control/Status Registers (Csrs)

    The Transmit FIFO is a message holding area for native messages waiting to be transmitted. Each host write to SCRAMNet+ SC150e memory may constitute a write to the Transmit FIFO. (Data Filtering and HIPRO features may interfere with this.) Each write to the Transmit FIFO contains 21 bits of address (A22-A2), 32 bits of data, and one bit of interrupt information.

  • Page 16: Receiver Fifo

    2.4 Network Ring The SCRAMNet+ SC150e Network is a ring topology network. Data is transmitted at a rate of 150 Mbits/s over dual fiber-optic cables. Together, the two lines produce the incoming data clock. Due to the network speed and message packet size, the network can accommodate over 1,800,000 message packets passing by each node every second.

  • Page 17: Auxiliary Control Ram (Acr)

    Channeling is based on a user-controlled switch setting and may be toggled to the desired position by writing to a bit in the SCRAMNet+ SC150e CSR. When access to the ACR is enabled, shared memory is not accessible by the host and the ACR byte is viewed as the least significant byte (LSB) of every shared-memory four - byte address.

  • Page 18: Interrupts

    • SCRAMNet+ SC150e network errors detected on the local node. SCRAMNet+ SC150e interrupts usually require a device driver to interface with the node processor. The driver is required primarily to permit the host processor to handle interrupts from the SCRAMNet device.

  • Page 19: Figure 2-3 Outgoing Interrupt

    • The data is stored in that location • The SCRAMNet+ SC150e address of the memory location is placed on the Interrupt FIFO queue, and • An interrupt is sent to the processor. NETWORK ERRORS The Interrupt on (Network) Errors mode is enabled by setting CSR0[7] ON.

  • Page 20: Forced Interrupt

    ACR Transmit Interrupt bit. A third condition, Receive Interrupt Override CSR8[10], is used to designate all incoming network traffic as interrupt messages. The network message interrupt bit does not need to be set. Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 21: External Triggers

    SC150e memory producing a data change are transmitted to the network. EXAMPLE: If location 1000 in SCRAMNet+ SC150e memory contains the value ‘20’ and the host processor writes the value ‘20’ to location 1000, then no network traffic will be generated.

  • Page 22: High Performance (Hipro) Mode

    32 bits is received. HIPRO WRITE The SCRAMNet+ SC150e network message is based on 32-bit longword data. This means if any 8-bit field of the 32-bit buffer is changed, the entire 32-bit message is transmitted. If a host is limited to only 8-bit or 16-bit data bus transactions the network throughput is quartered or halved, respectively.

  • Page 23: Write-Me-Last Mode

    This can be useful for synchronization. This means that when the host performs a write to the SCRAMNet+ SC150e shared memory, the data is not immediately written to the host node’s memory, but is first sent to the other nodes on the network.
  • Page 24 SCRAMNET OVERVIEW This page intentionally left blank Copyright 2007 2-12 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 25: Product Overview

    3. PRODUCT OVERVIEW 3.1 Overview The SCRAMNet+ SC150e cards are backwards compatible with SCRAMNet+ and the original SCRAMNet Classic product with the exception of the GOLD RING communication protocol. The SCRAMNet+ SC150e products use an enhanced architecture where shared memory read operations bypass the SCRAMNet ASIC for improved performance.

  • Page 26: Scramnet+ Sc150E Pmc Card

    PRODUCT OVERVIEW The SCRAMNet+ SC150e PCI card offers the following features: • Single-Slot PCI solution • Designed in accordance with the PCI specification 2.1. • 32-bit PCI interface, maximum bus speed of 33 MHz. • Uses the V363EPC PCI Bridge chip from QuickLogic Corp.

  • Page 27: Scramnet+ Sc150E Cpci Card

    PRODUCT OVERVIEW 3.2.3 SCRAMNet+ SC150e CPCI Card Figure 3-3 SCRAMNet+ SC150e CPCI Card The SCRAMNet+ SC150e CPCI board offers the following features: • 3U Single-Slot CPCI solution, which includes 6U faceplate • Designed in accordance with the PCI specification 2.1 and CompactPCI Core Specification, PICMG 2.0 R3.0.

  • Page 28: Led Status Indicators

    3.3 LED Status Indicators 3.3.1 Insert LED The green Insert LED is ON when the node is inserted into the SCRAMNet+ SC150e Network ring. A node is inserted when it is electrically placed on the network for the purpose of transmitting and receiving messages. This LED is labeled “I” on the faceplate.

  • Page 29: Options

    With power at the node, the bypass switch is under software control. By setting a bit in one of the SCRAMNet+ SC150e node’s control registers, the switch can be placed in the “inserted” mode. The control signals are passed by an electrical connection between the node and the bypass switch using the 8-Pin Mini-DIN connector provided with the bypass switch.

  • Page 30: Quad Switch

    AUX CONNECTOR NETWORK REPEATER SERIAL INTERFACE MEDIA CONVERTER MANUAL SWITCH SCRAMNet+ SCRAMNet+ SCRAMNet+ SCRAMNet+ VME (3U, 6U, 9U) SBUS - GIO - REHOST EISA - ISA - PCI/PMC SelBUS Figure 3-5 Node Inclusion and Isolation Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 31: Fiber-Optic Cables

    3.6.3 Fiber-Optic Cables Fiber-optic cables may be purchased from Curtiss-Wright Controls or third parties. The recommended fiber-optic cable is 62.5/125 micron core multi-mode fiber-optic cable with ST connectors. See Appendix A for part numbers for the fiber-optic cables.
  • Page 32 PRODUCT OVERVIEW This page intentionally left blank Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 33: Installation

    Enable DEC_IGNORE (CSR10[0]) 4.2 Unpack the Card Perform the following steps: 1. Remove the SCRAMNet+ SC150e card, enclosed in its anti-static bag, from the anti-static carton. CAUTION: Exercise care regarding the static environment. Use an anti-static mat connected to a wristband when handling or installing the SCRAMNet+ SC150e card.

  • Page 34: Figure 4-1 Pci Layout (Card Revision B1)

    INSTALLATION EEPROM WRITE ENABLE J303 EEPROM READ ENABLE J304 Figure 4-1 PCI Layout (card revision B1) Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 35: Figure 4-2 Pci Layout (Card Revision C1 Or Higher)

    INSTALLATION EEPROM EEPROM READ WRITE ENABLE ENABLE J304 J303 Figure 4-2 PCI Layout (card revision C1 or higher) Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 36: Figure 4-3 Pmc Layout

    INSTALLATION Connectors (P1, P2) EEPROM WRITE ENABLE J303 EEPROM READ ENABLE J304 Figure 4-3 PMC Layout Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 37: Figure 4-4 Cpci Layout

    INSTALLATION EEPROM WRITE ENABLE J303 EEPROM READ ENABLE J304 Figure 4-4 CPCI Layout Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 38: External Configuration

    To enable EEPROM READ install a 2-pin header on the left pair of the read jumper as viewed from the fiber-optic connector end of the card as shown in Figure 4-1 through Figure 4-3. Factory default: ENABLED Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 39: Install The Card

    Installing any type of card in a non-standard PMC slot may result in serious damage to the host machine. 1. Remove the bulkhead cover plate where the SCRAMNet+ SC150e host card will 2. (SC150e PMC only) Mount the PMC card on a motherboard, adapter, or carrier card as shown in Figure 4-7.

  • Page 40: Cpci Card Installation

    The basic SCRAMNet+ SC150e Network communication architecture consists of SCRAMNet+ SC150e cards tied together by paired sets of fiber-optic cable in a ring configuration. The maximum recommended distance between each node of the network using standard fiber optic media is approximately 300 meters. The maximum node separation using long link fiber optic media is 3,500 meters.

  • Page 41: Fiber-Optic Cables

    The optional paired fiber-optic cables are shipped in a separate carton. The fiber-optic cables are to be attached to the connectors on the SCRAMNet+ SC150e card or on the Cabinet Kit, as appropriate. Remove the rubber boots on the fiber-optic transmitters and receivers as well as the ones on the fiber-optic cables.

  • Page 42: Fiber-Optic Connection

    NOTE: It does not matter if Tx or Tx is connected to the next node’s Rx or Rx long as both Tx cables are connected to both of the next node’s Rx connectors. Figure 4-9 Fiber-Optic Connections Copyright 2007 4-10 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 43: Fiber Optic Bypass Switch Option

    4.7 Fiber Optic Bypass Switch Option 4.7.1 Configuration and Connection with SC150e PCI and CPCI Figure 4-10 and Figure 4-11 show the layout for the SCRAMNet+ SC150e PCI and CPCI, which differs from the standard connection shown in Appendix A, Figure A-2.

  • Page 44: Configuration And Connection With Sc150E Pmc

    INSTALLATION 4.7.2 Configuration and Connection with SC150e PMC Figure 4-12 and Figure 4-13 show the layout for the SCRAMNet+ SC150e PMC and differs from the standard connection shown in Appendix A, Figure A-2. Make Fiber Optic Bypass Switch connections as described in Figure 4-12 and Figure 4-13.

  • Page 45: Figure 4-13 Bypass State (Power Off)

    INSTALLATION Figure 4-13 Bypass State (Power Off) Copyright 2007 4-13 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 46: Auxiliary Connection On Sc150E Pci And Cpci

    The Auxiliary Connection is used for communication with the Fiber Optic Bypass Switch. The 3-pin male connection described in Figure 4-15 is defined in Table 4-2. (The view is looking into the connector). Figure 4-15 PMC Faceplate With Auxiliary Connection Copyright 2007 4-14 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 47: Internal Configuration

    4.8.1 SCRAMNet+ SC150e Control/Status Registers (CSR) Table 4-3 is a listing of the SCRAMNet+ SC150e Control/Status Registers. If using software other than that supplied by Curtiss-Wright Controls the offsets in the first two columns must be added to the 0x800000 CSR base address.

  • Page 48: Scramnet On Dec Computers

    The EEPROM is used to store the initial power-up register values. The EEPROM can be programmed either over the host backplane or by most PROM programmers. An EEPROM initialization (EPI) program is included in the Curtiss-Wright Controls Software Utilities Package for most systems.

  • Page 49: Node Identification

    (32-bit) 12345678 12345678 The SCRAMNet-LX, SCRAMNet+ and SCRAMNet+ SC150e product lines use the big- endian ordering philosophy as the default for data passing. These cards do not have a built-in byte-ordering conversion function. However, SCRAMNet+ and SCRAMNet+ SC150e cards permit byte-swapping options via the V3 registers PCI_MAP0 and PCI_MAP1.

  • Page 50: Dma Operation

    DMA operation. See section 1.2 in this manual for information on how to access the V363EPC User Manual. 4.11 Maintenance No routine maintenance is required for the SCRAMNet+ SC150e general-purpose nodes beyond that which is required for host computer systems. SCRAMNet+ SC150e network fiber-optic cabling connectors should be inspected periodically. 4.12 Troubleshooting Problem:...

  • Page 51: Operation

    SC150e shared-memory configuration. Typically, SCRAMNet+ SC150e memory is installed and linked to a host global common block through the host operating system. Once the link is complete, any program can reference SCRAMNet+ SC150e memory as a standard common-block variable reference.

  • Page 52: Figure 5-1 Memory Sharing With Virtual Paging

    Relative address + Virtual page offset = Network address For example: 12340 + 400000 = 412340 This network address is transmitted to all SCRAMNet+ SC150e nodes and is written to that address. In nodes where the address does not exist in SCRAMNet+ SC150e memory, the write is ignored.

  • Page 53: Memory Considerations

    The ability for a computer to write a copy of data to a local fast memory for quicker access later must be turned off during a SCRAMNet+ SC150e memory read. Since other nodes may be changing the data, it is critical that the processor read the data directly from SCRAMNet+ SC150e memory.

  • Page 54: Initialization

    OPERATION 5.3 Initialization The initialization of the SCRAMNet+ SC150e node from a cold boot is determined by the settings of the EEPROM. No fiber-optic cable connections are required to perform a read/write to the local host’s SCRAMNet+ SC150e memory. When the control registers CSR0 and CSR2 are set to zero the SCRAMNet+ SC150e memory is available for access.

  • Page 55: Message Contents

    Bits A0 and A1 are always zero for a longword boundary. DATA VALUE This 32-bit field contains the data value in SCRAMNet+ SC150e memory that is currently being updated around the ring. When the PLUS mode is enabled, data size may vary up to 256 bytes or 1024 bytes depending on the option selected.
  • Page 56 To maintain a PLUS mode transmission, step 1 requires that new data is written to the SCRAMNet+ SC150e card at a rate greater than or equal to 16.7 MB/sec (this is a 32-bit write every 240 ns). Any delay in the host data write will result in failure of step 1, and a premature end to the PLUS mode transmission.

  • Page 57: Performance

    DATA TRANSFER While the SCRAMNet+ SC150e Network appears as a shared-memory system, it is still a data network. The SCRAMNet+ SC150e Network includes a series of FIFO buffers to collect data changes until they are transmitted to the other nodes. The Transmit FIFO and the Interrupt FIFO are both 1024 messages in length.

  • Page 58: Throughput

    CSR0[4] back to zero so that shared-memory can again be accessed. The ACR actions are still in effect, but the ACR bytes can no longer be accessed while the ACR Enable bit is zero. Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...
  • Page 59 OPERATION In order for the ACR values to take effect for interrupt action, the following SCRAMNet+ SC150e CSR actions should be considered for the type of interrupt operation desired: • Host Interrupt Enable CSR0[3] to receive network interrupts • Network Interrupt Enable CSR0[8] to transmit network interrupts •...

  • Page 60: Interrupt Controls

    OPERATION 5.7 Interrupt Controls SCRAMNet+ SC150e allows a processor to receive interrupts from and/or transmit interrupts to any other processors on the network, including the originating processor. Table 5-3 indicates the various sources for interrupt control. 5.7.1 Interrupt Options Table 5-3 Interrupt Controls...

  • Page 61: Interrupt Conditions

    Only those nodes which have the Receive Interrupt Enable ACR[0] bit set for that address will generate an interrupt signal to their host processor. The host issues a write to SCRAMNet+ SC150e shared memory. If Override Transmit Interrupt Enable CSR0[9] or ACR Transmit Interrupt Enable ACR[1] is set and Network Interrupt Enable CSR0[8] is set, then the interrupt message is transmitted (INT = 1).

  • Page 62: Figure 5-2 Transmit Interrupt Logic

    OPERATION HOST TRANSMIT ENABLE WRITE CSR0[1] MUST BE ACTIVE CSR0[9] OVERRIDE TIE ACR[1] CSR0[8] NETWORK INTERRUPT ENABLE TRANSMIT TRANSMIT INTERRUPT SLOT TO NON-INTERRUPT NETWORK SLOT TO NETWORK Figure 5-2 Transmit Interrupt Logic Copyright 2007 5-12 SCRAMNet+ SC150e HARDWARE REFERENCE...
  • Page 63 CSR0 or CSR8. MASKED OR SELECTED INTERRUPT The masked- or selected-interrupt method requires choosing SCRAMNet+ SC150e shared-memory locations on each node to receive and/or transmit interrupts. These shared-memory locations may also be used to generate signals to external triggers. The procedure for selecting shared-memory locations for interrupts and/or external triggers is explained in paragraph 5.6: Auxiliary Control RAM.

  • Page 64: Figure 5-3 Receive Interrupt Logic

    PLACE HOST ADDRESS INTO ENABLE INTERRUPT FIFO CSR1[14] INTERRUPTS ENABLED RECEIVE ENABLE CSR0[0] MUST BE ACTIVE GENERATE WRITE CSR1 NO INTERRUPT INTERRUPT TO TO HOST TO RE-ARM HOST Figure 5-3 Receive Interrupt Logic Copyright 2007 5-14 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 65: Network Error

    CSR1. Details are included in the SCRAMNet Network Programmer’s Reference Guide and the appropriate DLL Reference Guide for the host computer interface. Copyright 2007 5-15 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 66: Interrupt Handling

    The Interrupt FIFO is accessed via CSR4 and CSR5. CSR5 contains the most significant seven bits of the 23-bit SCRAMNet+ SC150e interrupt address and CSR4 contains the remaining 16 bits of the interrupt address. (The 23-bit address allows for future expansion of memory).

  • Page 67: External Triggers

    Trigger 1 will be generated for any host write to SCRAMNet+ SC150e memory. Trigger 2 will be generated by a network write to the SCRAMNet+ SC150e memory. Pin 7 of the Auxiliary Connector is connected to TRIG1 logically OR’ed with TRIG2.

  • Page 68: General Purpose Counter/Timer

    Only one mode may be selected at a time since they use the same counter/timer register (CSR13) for output. 5.10.3 Presetting Values The counter/timer register counts upward and may be preset with a value to arrive at the desired interrupt interval. Copyright 2007 5-18 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 69: Modes Of Operation

    Many implementations of shared memory tend to rewrite data values to memory that have not actually changed. In order to reduce network traffic, the SCRAMNet+ SC150e card has the ability to compare the new value with the old value of data and avoid sending unchanged data values out on the network.

  • Page 70: Figure 5-4 Data Filter Logic

    OPERATION DATA FILTER LOGIC NOTHING WRITE HOST DATUM SAME DATUM WRITE TO MEMORY READ SHARED MEMORY NETWORK RING NETWORK RING NETWORK LOGIC Figure 5-4 Data Filter Logic Copyright 2007 5-20 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 71: Hipro Mode

    5.11.2 HIPRO Mode WRITE The SCRAMNet+ SC150e network message is based on 32-bit longword data. If a host processor is only capable of 8- or 16-bit data transactions, then the SCRAMNet+ SC150e bandwidth is quartered or halved, respectively. For each 32-bit data transaction from the host, two 16-bit data transactions, or four 8-bit transactions will occur on the bus each requiring a SCRAMNet+ SC150e network write.

  • Page 72: Figure 5-5 Monitor And Bypass Mode

    Insert Enable CSR0[15] Enable Wire Loopback CSR2[7] Fiber Optic Bypass Switch (Optional) Media Circuitry Conv Conv MECHSWITCH Internal PLL and Data Recovery INSERT ENABLE WIRE LOOPBACK ENABLE ENABLE Figure 5-5 Monitor and Bypass Mode Copyright 2007 5-22 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 73: Figure 5-6 Wire Loopback Mode

    Insert Enable CSR0[15] Enable Wire Loopback CSR2[7] Fiber Optic Bypass Switch (Optional) Media Circuitry Conv Conv MECHSWITCH Internal PLL and Data Recovery INSERT ENABLE WIRE LOOPBACK ENABLE ENABLE Figure 5-6 Wire Loopback Mode Copyright 2007 5-23 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 74: Figure 5-7 Mechanical Switch Loopback Mode

    Enable Wire Loopback CSR2[7] Mechanical Switch Override CSR8[11] Fiber Optic Bypass Switch (Optional) Media Circuitry Conv Conv MECHSWITCH Internal PLL and Data Recovery INSERT ENABLE WIRE LOOPBACK ENABLE ENABLE Figure 5-7 Mechanical Switch Loopback Mode Copyright 2007 5-24 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 75: Figure 5-8 Fiber-Optic Loopback Mode

    Disable Fiber-optic Loopback CSR2[6] Mechanical Switch Override CSR8[11] Fiber Optic Bypass Switch (Optional) Media Circuitry Conv Conv MECHSWITCH Internal PLL and Data Recovery INSERT ENABLE WIRE LOOPBACK ENABLE ENABLE Figure 5-8 Fiber-optic Loopback Mode Copyright 2007 5-25 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 76: Table 5-11 Node Insert Mode

    NOTE: Do not enable the Wire Loopback and Fiber-optic Loopback and/or Mechanical Switch loopback modes simultaneously. A node in Wire Loopback mode and Insert Node will create a break in the network ring that will disable all nodes. Copyright 2007 5-26 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 77: Holdoff Mode

    SC150e memory faster than the network can absorb the data. If a CPU is capable of writing to the SCRAMNet+ SC150e memory on the PCI bus at such a rate that the Transmit FIFO becomes full (1024 deep), data could be lost. In the event that the Transmit FIFO becomes full, the hardware will automatically extend the next write cycle until the Transmit FIFO empties at least one message.

  • Page 78: Write-Me-Last Mode

    When the host performs a write to the SCRAMNet+ SC150e shared-memory, it is not immediately written to the host memory, but is first sent to the other SCRAMNet+ SC150e nodes on the network. Set CSR2[8] and CSR2[9] to enable the Write-Me-Last mode. If desired, this mode can also be used to generate interrupts to the originating node by setting CSR2[10] as well.

  • Page 79: Figure 5-10 Quad Switch

    OPERATION Figure 5-10 Quad Switch Copyright 2007 5-29 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 80: Figure 5-11 Interrupt Service Routine

    Bit 15 contains the Interrupt FIFO Not Empty status. If an interrupt has been received by the host processor from the SCRAMNet+ SC150e Network interrupt logic, then the Interrupt Service Routine will be invoked. Interrupts will be disabled until re- armed by writing to CSR1.
  • Page 81 A. A – SPECIFICATIONS APPENDIX A SPECIFICATIONS TABLE OF CONTENTS A.1 SC150e PCI............................A-1 A.1.1 Hardware Specifications...................... A-1 A.1.2 Card Dimensions ......................... A-2 A.2 SC150e PMC............................A-3 A.2.1 Hardware Specifications...................... A-3 A.2.2 Card Dimensions ......................... A-4 A.3 SC150e CPCI ............................A-5 A.3.1 Hardware Specifications......................

  • Page 83: Appendix A - Specifications

    4 MB Memory..........217,808 hours 8 MB Memory..........186,721 hours Internal clock speeds: SCRAMNet+ SC150e Card crystal.... 150 MHz, +/-100 ppm 26.66 ns timer is a divide-by-four:..... 37.5 MHz 1.706 μs timer is a divide-by-256: ..... 585.9 KHz Specifications on the crystal demonstrate the precision and stability of the main clock from which all other clocks are derived.

  • Page 84: Card Dimensions

    SPECIFICATIONS A.1.2 Card Dimensions 4.20 6.875 Figure A-1 PCI Dimensions Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 85: Sc150E Pmc

    4 MB Memory..........217,276 hours 8 MB Memory..........189,130 hours Internal clock speeds: SCRAMNet+ SC150e Card crystal.... 150 MHz, +/-100 ppm 26.66 ns timer is a divide-by-four:..... 37.5 MHz 1.706 μs timer is a divide-by-256: ..... 585.9 KHz Specifications on the crystal demonstrate the precision and stability of the main clock from which all other clocks are derived.

  • Page 86: Card Dimensions

    SPECIFICATIONS A.2.2 Card Dimensions 2.91” 5.86” Figure A-2 PMC Dimensions Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 87: Sc150E Cpci

    4 MB Memory..........187,740 hours 8 MB Memory..........185,809 hours Internal clock speeds: SCRAMNet+ SC150e board crystal ..150 MHz, +/-100 ppm 26.66 ns timer is a divide-by-four:..... 37.5 MHz 1.706 μs timer is a divide-by-256: ..... 585.9 KHz Specifications on the crystal demonstrate the precision and stability of the main clock from which all other clocks are derived.

  • Page 88: Card Dimensions

    SPECIFICATIONS A.3.2 Card Dimensions 3.937″ 6.299″ Figure A-3 CPCI Dimensions Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 89: Performance

    08M = 8 MB Transmission Media. 20 = Standard FO Media 30 = Long Link FO Media Variable. Used for product variations and/or modifications Contact Curtiss-Wright Controls, Inc., regarding the availability of SC150e Card options. Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 90: Fiber-Optic Cables

    The recommended fiber-optic cable is 62.5/125 micron core multi-mode fiber with ST connectors. Contract Curtiss-Wright Controls, Inc., regarding the availability of fiber- optic cables. The part number for Curtiss-Wright Controls’ 62.5/125 micron fiber-optic cables is in the form: H-PR-WST23000-0 (paired 62.5/125 micron cable, 3 meters)

  • Page 91: Fiber Optic Bypass Switch

    SPECIFICATIONS A.7 Fiber Optic Bypass Switch Figure A-4 Fiber Optic Bypass Switch Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 92: Fiber Optic Bypass Switch Dimensions

    SPECIFICATIONS A.7.1 Fiber Optic Bypass Switch Dimensions Figure A-5 Housing Dimensions Copyright 2007 A-10 SCRAMNet+ SC150e HARDWARE REFERENCE...
  • Page 93 TABLES Table B-1 CSR0 - General SCRAMNet+ SC150e Enable and Reset (Read/Write)........B-2 Table B-2 CSR1 - SCRAMNet+ SC150e Error Indicators (Read Only with Write/Reset for interrupts)..B-4 Table B-3 CSR2 - Node Control (Read/Write) ....................B-6 Table B-4 CSR3 - Node Information (READ ONLY)...................B-8 Table B-5 CSR4 - Interrupt Address (LSP) (READ ONLY) .................B-8...
  • Page 95 The registers are described using bit 0 as the Least Significant Bit (LSB). For example: Inserting 0xA7C3 in a 16-bit register would set bits 0, 1, 6, 7, 8, 9, 10, 13, and 15 ON. Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...
  • Page 96 CSR DESCRIPTIONS Table B-1 CSR0 - General SCRAMNet+ SC150e Enable and Reset (Read/Write) Bits Description Network Communications Mode - Bit 0 controls the receive enable, and Bit 1 controls the transmit enable. 00 None - In this mode, all communications between the node-shared memory and the network is inhibited.
  • Page 97 Fiber Optic Loopback CSR2[6] is disabled. This bit is invalid when the Enable Wire Loopback CSR2[7] is ON. *User access to Trigger 1 and Trigger 2 is not available on the PMC Card. Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...
  • Page 98 CSR DESCRIPTIONS Table B-2 CSR1 - SCRAMNet+ SC150e Error Indicators (Read Only with Write/Reset for interrupts) NOTE: Reading CSR1 will reset the latched error conditions by clearing bits 0, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, and 13.
  • Page 99 Fiber Optic Bypass Switch. A ‘0’ in this bit indicates that the bypass switch is installed while a ‘1’ indicates it is not installed. Fiber Optic Loopback CSR2[6] mode is dependent upon the Fiber Optic Bypass Switch being installed. Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...
  • Page 100 HIPRO will not work when writing two separate shortwords while using interrupts. Multiple Messages - This bit allows multiple native messages on the network. It is used in conjunction with CSR2[11], CSR2[12] and CSR2[15] to enable the BURST mode communication protocol (see below). Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...
  • Page 101 No Network Error Correction - This bit is used in conjunction with CSR2[12] and CSR2[14] to enable communication protocols: BURST or PLATINUM mode and the variable length message PLUS ( ) mode (see below). SCRAMNet+ SC150e Protocol Mode Definition CSR2[15] CSR2[14] CSR2[12]...
  • Page 102 Bits Description Node Number Count - These bits represent the total number of SCRAMNet+ SC150e nodes on the network. This value is dynamically determined by the hardware and ranges from 0 to 255 depending upon the number of nodes actually on the network.
  • Page 103 Bits Description 15-0 Not Used Table B-9 CSR8 - General SCRAMNet+ SC150e Extended Control Register Bits Description ID Multiplex - When set to ‘1’, CSR3 contains the T_AGE and RXID fields. Disable Holdoff - When set, this bit disables the Holdoff feature.
  • Page 104 CSR DESCRIPTIONS Table B-10 CSR9 - SCRAMNet+ SC150e Interrupt On-Error Mask* Bits Description Transmit FIFO Full Mask Transmit FIFO not Empty Mask Transmit FIFO 7/8 Full Mask Built In Self Test Stream (BIST) - Internal 82-bit BIST shift register output.
  • Page 105 CSR DESCRIPTIONS Table B-12 CSR11 - Reserved Bits Description 15-0 Not Used Table B-13 CSR12 - SCRAMNet+ SC150e Virtual Paging Register Bits Description Virtual Paging Enable. When ON, this bit enables Virtual Paging. Always zero VP_A12 VP_A13 VP_A14 VP_A15 VP_A16 Virtual Page number.
  • Page 106 RD_COUNT[8] programmed by CSR9[13] and CSR9[14]. RD_COUNT[9] RD_COUNT[10] RD_COUNT[11] RD_COUNT[12] RD_COUNT[13] RD_COUNT[14] RD_COUNT[15] Table B-15 CSR14 - Reserved Bits Description 15-0 Not Used Table B-16 CSR15 - Reserved Bits Description 15-0 Not Used Copyright 2007 B-12 SCRAMNet+ SC150e HARDWARE REFERENCE...
  • Page 107 C.6 CSR5 - Interrupt Address (MSW) and Status (READ Only*) ..............C-6 C.7 CSR6 - Reserved .............................C-6 C.8 CSR7 - Reserved .............................C-6 C.9 CSR8 - General SCRAMNet+ SC150e Extended Control Register ............C-7 C.10 CSR9 - SCRAMNet+ SC150e Interrupt-On-Error Mask ..............C-8 C.11 CSR10 - DEC_IGNORE ........................C-9 C.12 CSR11 - Reserved ..........................C-9...

  • Page 109: Csr0 - General Scramnet+ Sc150E Enable And Reset

    CSR SUMMARY C.1 CSR0 – General SCRAMNet+ SC150e Enable and Reset Function Name Receive Enable RX_ENB Transmit Enable TXEN Redundant TxRx Toggle Host Interrupt Enable Auxiliary Control RAM Enable ACRE Interrupt on Memory Mask Match Enable IMME Override RIE Flag...

  • Page 110: Csr1 - Error Indicators

    Bad Message Receiver Overflow Transmit Retry TXRTY Transmit Retry Time-out Redundant TxRx Fault General Purpose GPCTO Counter/Timer Overflow Redundant TxRx Link RTLAB 1=A/0=B Interrupts Armed - Write to IARM re-arm Fiber Optic Bypass Not Connected Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 111: Csr2 - Node Control

    WRITE ME LAST with SELF-INTERRUPT mode SCRAMNet Protocol Mode Definition CSR2[15] CSR2[14] CSR2[12] CSR2[11] Network No Error Multiple Variable Message Size Mode Correction Message Length Maximum BURST NO MEANING PLATINUM NO MEANING 1=1024, BURST 0=256 1=1024, PLATINUM 0=256 Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 112: Csr3 - Node Information

    (Valid After a Transmission from the Node) NID0 NID1 NID2 Node ID Number* NID3 NID4 NID5 NID6 NID7 When ID_MUX CSR[0] is set: Bits 7 - 0 are Transmit AGE Bits 15 - 8 are Receive ID. Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 113: Csr4 - Interrupt Address (Lsw

    CSR SUMMARY C.5 CSR4 – Interrupt Address (LSW) Function Name Always = 0 Always = 0 RFA2 RFA3 RFA4 RFA5 Interrupt FIFO Address Field (LSW) RFA6 RFA7 RFA8 RFA9 RFA10 RFA11 RFA12 RFA13 RFA14 RFA15 Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 114: Csr5 - Interrupt Address (Msw) And Status (Read Only

    ‘0’. A value of ‘0’ prevents host-generated data from leaving the Transmit FIFO C.7 CSR6 – Reserved A 16-bit, Read-Only Curtiss-Wright Controls reserved register. C.8 CSR7 – Reserved A 16-bit, Read-Only Curtiss-Wright Controls reserved register. Copyright 2007...

  • Page 115: Csr8 - General Scramnet+ Sc150E Extended Control Register

    CSR SUMMARY C.9 CSR8 – General SCRAMNet+ SC150e Extended Control Register Function Name 1 is CSR3=T_AGE & RXID fields ID_MUX Disable Holdoff feature DIS_HOLD Chip select to EEPROM CSR_CS0 Ext. Chip Select for AUX MICROWIRE CSR_CS1 peripheral MICROWIRE DOUT pin...

  • Page 116: Csr9 - Scramnet+ Sc150E Interrupt-On-Error Mask

    CSR SUMMARY C.10 CSR9 – SCRAMNet+ SC150e Interrupt-On-Error Mask Function Name Transmit FIFO Full mask M_TX_F_F Transmit FIFO Not Empty mask M_TX_F_E Transmit FIFO 7/8 Full Mask M_TX_F_AF Internal 82 bit BIST shift register output BIST_STREAM Receiver FIFO Full Mask...

  • Page 117: Csr10 - Dec_Ignore

    CSR SUMMARY C.11 CSR10 – DEC_IGNORE Function Name 1 = Non-DEC system DEC_IGNORE 0 = DEC system 15-1 Reserved C.12 CSR11 – Reserved A 16-bit, Read Only Curtiss-Wright Controls reserved register. Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...

  • Page 118: Csr12 - Scramnet+ Sc150E Virtual Paging Register

    CSR SUMMARY C.13 CSR12 – SCRAMNet+ SC150e Virtual Paging Register (Refer to Chapter 54, subsection 5.2.1, and Appendix B, page B-11 for additional information) Function Name Enables Virtual Paging when set Always ‘0’ VP_A12 VP_A13 VP_A14 VP_A15 Virtual Page Number...

  • Page 119: Csr14 - Reserved

    CSR SUMMARY C.15 CSR14 – Reserved A 16-bit, Read Only Curtiss-Wright Controls reserved register. C.16 CSR15 – Reserved A 16-bit, Read Only Curtiss-Wright Controls reserved register. C.17 Auxiliary Control RAM (R/W) Function Name Receive Interrupt Enable Transmit Interrupt Enable External Trigger 1 (Host Read/Write)*...
  • Page 120 CSR SUMMARY This page intentionally left blank Copyright 2007 C-12 SCRAMNet+ SC150e HARDWARE REFERENCE...
  • Page 121 D. D – CONFIGURATION AIDS APPENDIX D CONFIGURATION AIDS...
  • Page 123 CONFIGURATION AIDS SCRAMNet+ SC150e CONTROL/STATUS REGISTERS REFERENCE SHEET CSR 0 CSR 2 CSR 4 CSR 6 always 0 RX ENB available to host reserved always 0 TX ENB available to host reserved REDUND LINK TOGGLE available to host RFA 2...
  • Page 124 TX RETRY TIME-OUT reserved reserved REDUN TXRX FAULT MASK reserved reserved GP CTR/TIMER OVRFLO reserved reserved UTIL CTR MODES reserved reserved UTIL CTR MODES reserved reserved FO BYPASS NOT CNCTD MASK reserved RD COUNT 15 Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...
  • Page 125 CONFIGURATION AIDS SCRAMNet+ SC150e NETWORK CONFIGURATION DATA SHEET MEMORY NODE HOST MEMORY SCRAMNet ADDRESS ADDRESS MACHINE SIZE LEVEL SERIAL # & BUS & BUS Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...
  • Page 126 CONFIGURATION AIDS This page intentionally left blank Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...
  • Page 127 1. GLOSSARY GLOSSARY...
  • Page 129 Without this module, it could wait forever for a slave to respond if the master tries to transfer data to or from a nonexistent slave location. The bus timer prevents this by terminating the cycle. Copyright 2007 Glossary 1 SCRAMNet+ SC150e HARDWARE REFERENCE...
  • Page 130 DTB cycle, initiated by an interrupt handler, that reads a status/ID from an interrupter. An interrupt handler generates this cycle when it detects an interrupt request from an interrupter and it has control of the DTB. Copyright 2007 Glossary 2 SCRAMNet+ SC150e HARDWARE REFERENCE...
  • Page 131 -----------One of the four buses provided by the backplane. The priority interrupt bus allows interrupter modules to send interrupt requests to interrupt handler modules, and interrupt handler modules to acknowledge these interrupt requests. Copyright 2007 Glossary 3 SCRAMNet+ SC150e HARDWARE REFERENCE...
  • Page 132 (2) A asterisk following the name of signals that are edge-significant denotes the actions initiated by that signal occur on the falling edge. Copyright 2007 Glossary 4 SCRAMNet+ SC150e HARDWARE REFERENCE...
  • Page 133 If so, it stores the data and then acknowledges the transfer. The master then terminates the cycle. Copyright 2007 Glossary 5 SCRAMNet+ SC150e HARDWARE REFERENCE...
  • Page 134 GLOSSARY This page intentionally left blank Copyright 2007 Glossary 6 SCRAMNet+ SC150e HARDWARE REFERENCE...
  • Page 135 1. INDEX INDEX...

  • Page 137: Index

    3-5 ST ..............4-10 troubleshooting..........4-18 counter mode unpack ............... 4-1 override .............C-7 fiber optic bypass switch loopback ............5-26 register access............ 5-3 fiber optic bypass switch not connected ............B-5 Copyright 2007 Index 1 SCRAMNet+ SC150e HARDWARE REFERENCE...
  • Page 138 2-6 intercept............5-15 interrupts armed..........B-5, C-2 network interrupt enable ............B-3, C-1 network message error correction..........5-7 carrier detect............3-4 network ring 2-4, 2-11, 4-10, 4-18, 5-4, 5-5, 5-7, 5-26 insert..............3-4 Copyright 2007 Index 2 SCRAMNet+ SC150e HARDWARE REFERENCE...
  • Page 139 ........2-5, 5-8 four-byte word........... 2-5 read latency............3-1 location........2-5, 2-9, 5-8, 5-9 receive interrupt override .............B-9, C-7 receive interrupt enable temperature range ......... A-1, A-3, A-5 flag ..............C-1 Copyright 2007 Index 3 SCRAMNet+ SC150e HARDWARE REFERENCE...
  • Page 140 ........... A-1, A-3, A-5 mask ............B-10, C-8 wire loopback time-out .............C-8 enable ..........B-3, B-6, C-3 transmitter retry time-out internal circuitry ..........5-23 mask ..............B-10 write own slot enable ..............B-6 write posting ............A-7 utility Copyright 2007 Index 4 SCRAMNet+ SC150e HARDWARE REFERENCE...

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