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PCI Industrial Computer Manufacturer’s Group Curtiss-Wright Controls, Inc., is an Associate Level member of PICMG and as such may use the PICMG and CompactPCI logos. Any reference made within this document to equipment from other vendors does not constitute an endorsement of their product(s).
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This product is intended for use in industrial, laboratory, or military environments. This product uses and emits electromagnetic radiation, which may interfere with other radio and communication devices. The user may be in violation of FCC regulations if this device is used in other than the intended market environments.
This document is a reference manual for the SCRAMNet+ SC150e PCI, PMC and CompactPCI network interface cards (NIC). It provides a physical and functional description of the SCRAMNet+ SC150e NIC and describes how to unpack, set up, install and operate the hardware. Hereafter in this manual “CompactPCI” is referred to as “CPCI.”...
PROGREF) - A collection of routines to assist SCRAMNet users with application development. SCRAMNet Network Utilities User Manual (Doc. Nr. C-T-MU-UTIL) - A user’s • manual for the SCRAMNet Classic, SCRAMNet-LX, and SCRAMNet+ SC150e hardware diagnostic software, SCRAMNet+ SC150e EEPROM initialization software, and the SCRAMNet Network Monitor. •...
INTRODUCTION 1.3 Quality Assurance Curtiss-Wright Controls’ policy is to provide our customers with the highest quality products and services. In addition to the physical product, the company provides documentation, sales and marketing support, hardware and software technical support, and timely product delivery. Our quality commitment begins with product concept, and continues after receipt of the purchased product.
World Wide Web address: www.cwcembedded.com 1.5 Ordering Process To learn more about Curtiss-Wright Controls’ products or to place an order, please use the following contact information. Hours of operation are from 8:00 a.m. to 5:00 p.m. Eastern Standard/Daylight Time. •...
SCRAMNet+ SC150e memory is automatically sent to the same SCRAMNet+ SC150e memory location in all nodes on the network. This is why it is also referred to as replicated shared memory. A good analogy is the COMMON AREA used by the FORTRAN programming language.
The Transmit FIFO is a message holding area for native messages waiting to be transmitted. Each host write to SCRAMNet+ SC150e memory may constitute a write to the Transmit FIFO. (Data Filtering and HIPRO features may interfere with this.) Each write to the Transmit FIFO contains 21 bits of address (A22-A2), 32 bits of data, and one bit of interrupt information.
2.4 Network Ring The SCRAMNet+ SC150e Network is a ring topology network. Data is transmitted at a rate of 150 Mbits/s over dual fiber-optic cables. Together, the two lines produce the incoming data clock. Due to the network speed and message packet size, the network can accommodate over 1,800,000 message packets passing by each node every second.
Channeling is based on a user-controlled switch setting and may be toggled to the desired position by writing to a bit in the SCRAMNet+ SC150e CSR. When access to the ACR is enabled, shared memory is not accessible by the host and the ACR byte is viewed as the least significant byte (LSB) of every shared-memory four - byte address.
• SCRAMNet+ SC150e network errors detected on the local node. SCRAMNet+ SC150e interrupts usually require a device driver to interface with the node processor. The driver is required primarily to permit the host processor to handle interrupts from the SCRAMNet device.
• The data is stored in that location • The SCRAMNet+ SC150e address of the memory location is placed on the Interrupt FIFO queue, and • An interrupt is sent to the processor. NETWORK ERRORS The Interrupt on (Network) Errors mode is enabled by setting CSR0[7] ON.
ACR Transmit Interrupt bit. A third condition, Receive Interrupt Override CSR8[10], is used to designate all incoming network traffic as interrupt messages. The network message interrupt bit does not need to be set. Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...
SC150e memory producing a data change are transmitted to the network. EXAMPLE: If location 1000 in SCRAMNet+ SC150e memory contains the value ‘20’ and the host processor writes the value ‘20’ to location 1000, then no network traffic will be generated.
32 bits is received. HIPRO WRITE The SCRAMNet+ SC150e network message is based on 32-bit longword data. This means if any 8-bit field of the 32-bit buffer is changed, the entire 32-bit message is transmitted. If a host is limited to only 8-bit or 16-bit data bus transactions the network throughput is quartered or halved, respectively.
This can be useful for synchronization. This means that when the host performs a write to the SCRAMNet+ SC150e shared memory, the data is not immediately written to the host node’s memory, but is first sent to the other nodes on the network.
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SCRAMNET OVERVIEW This page intentionally left blank Copyright 2007 2-12 SCRAMNet+ SC150e HARDWARE REFERENCE...
3. PRODUCT OVERVIEW 3.1 Overview The SCRAMNet+ SC150e cards are backwards compatible with SCRAMNet+ and the original SCRAMNet Classic product with the exception of the GOLD RING communication protocol. The SCRAMNet+ SC150e products use an enhanced architecture where shared memory read operations bypass the SCRAMNet ASIC for improved performance.
PRODUCT OVERVIEW The SCRAMNet+ SC150e PCI card offers the following features: • Single-Slot PCI solution • Designed in accordance with the PCI specification 2.1. • 32-bit PCI interface, maximum bus speed of 33 MHz. • Uses the V363EPC PCI Bridge chip from QuickLogic Corp.
PRODUCT OVERVIEW 3.2.3 SCRAMNet+ SC150e CPCI Card Figure 3-3 SCRAMNet+ SC150e CPCI Card The SCRAMNet+ SC150e CPCI board offers the following features: • 3U Single-Slot CPCI solution, which includes 6U faceplate • Designed in accordance with the PCI specification 2.1 and CompactPCI Core Specification, PICMG 2.0 R3.0.
3.3 LED Status Indicators 3.3.1 Insert LED The green Insert LED is ON when the node is inserted into the SCRAMNet+ SC150e Network ring. A node is inserted when it is electrically placed on the network for the purpose of transmitting and receiving messages. This LED is labeled “I” on the faceplate.
With power at the node, the bypass switch is under software control. By setting a bit in one of the SCRAMNet+ SC150e node’s control registers, the switch can be placed in the “inserted” mode. The control signals are passed by an electrical connection between the node and the bypass switch using the 8-Pin Mini-DIN connector provided with the bypass switch.
3.6.3 Fiber-Optic Cables Fiber-optic cables may be purchased from Curtiss-Wright Controls or third parties. The recommended fiber-optic cable is 62.5/125 micron core multi-mode fiber-optic cable with ST connectors. See Appendix A for part numbers for the fiber-optic cables.
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Enable DEC_IGNORE (CSR10[0]) 4.2 Unpack the Card Perform the following steps: 1. Remove the SCRAMNet+ SC150e card, enclosed in its anti-static bag, from the anti-static carton. CAUTION: Exercise care regarding the static environment. Use an anti-static mat connected to a wristband when handling or installing the SCRAMNet+ SC150e card.
To enable EEPROM READ install a 2-pin header on the left pair of the read jumper as viewed from the fiber-optic connector end of the card as shown in Figure 4-1 through Figure 4-3. Factory default: ENABLED Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...
Installing any type of card in a non-standard PMC slot may result in serious damage to the host machine. 1. Remove the bulkhead cover plate where the SCRAMNet+ SC150e host card will 2. (SC150e PMC only) Mount the PMC card on a motherboard, adapter, or carrier card as shown in Figure 4-7.
The basic SCRAMNet+ SC150e Network communication architecture consists of SCRAMNet+ SC150e cards tied together by paired sets of fiber-optic cable in a ring configuration. The maximum recommended distance between each node of the network using standard fiber optic media is approximately 300 meters. The maximum node separation using long link fiber optic media is 3,500 meters.
The optional paired fiber-optic cables are shipped in a separate carton. The fiber-optic cables are to be attached to the connectors on the SCRAMNet+ SC150e card or on the Cabinet Kit, as appropriate. Remove the rubber boots on the fiber-optic transmitters and receivers as well as the ones on the fiber-optic cables.
NOTE: It does not matter if Tx or Tx is connected to the next node’s Rx or Rx long as both Tx cables are connected to both of the next node’s Rx connectors. Figure 4-9 Fiber-Optic Connections Copyright 2007 4-10 SCRAMNet+ SC150e HARDWARE REFERENCE...
4.7 Fiber Optic Bypass Switch Option 4.7.1 Configuration and Connection with SC150e PCI and CPCI Figure 4-10 and Figure 4-11 show the layout for the SCRAMNet+ SC150e PCI and CPCI, which differs from the standard connection shown in Appendix A, Figure A-2.
INSTALLATION 4.7.2 Configuration and Connection with SC150e PMC Figure 4-12 and Figure 4-13 show the layout for the SCRAMNet+ SC150e PMC and differs from the standard connection shown in Appendix A, Figure A-2. Make Fiber Optic Bypass Switch connections as described in Figure 4-12 and Figure 4-13.
The Auxiliary Connection is used for communication with the Fiber Optic Bypass Switch. The 3-pin male connection described in Figure 4-15 is defined in Table 4-2. (The view is looking into the connector). Figure 4-15 PMC Faceplate With Auxiliary Connection Copyright 2007 4-14 SCRAMNet+ SC150e HARDWARE REFERENCE...
4.8.1 SCRAMNet+ SC150e Control/Status Registers (CSR) Table 4-3 is a listing of the SCRAMNet+ SC150e Control/Status Registers. If using software other than that supplied by Curtiss-Wright Controls the offsets in the first two columns must be added to the 0x800000 CSR base address.
The EEPROM is used to store the initial power-up register values. The EEPROM can be programmed either over the host backplane or by most PROM programmers. An EEPROM initialization (EPI) program is included in the Curtiss-Wright Controls Software Utilities Package for most systems.
(32-bit) 12345678 12345678 The SCRAMNet-LX, SCRAMNet+ and SCRAMNet+ SC150e product lines use the big- endian ordering philosophy as the default for data passing. These cards do not have a built-in byte-ordering conversion function. However, SCRAMNet+ and SCRAMNet+ SC150e cards permit byte-swapping options via the V3 registers PCI_MAP0 and PCI_MAP1.
DMA operation. See section 1.2 in this manual for information on how to access the V363EPC User Manual. 4.11 Maintenance No routine maintenance is required for the SCRAMNet+ SC150e general-purpose nodes beyond that which is required for host computer systems. SCRAMNet+ SC150e network fiber-optic cabling connectors should be inspected periodically. 4.12 Troubleshooting Problem:...
SC150e shared-memory configuration. Typically, SCRAMNet+ SC150e memory is installed and linked to a host global common block through the host operating system. Once the link is complete, any program can reference SCRAMNet+ SC150e memory as a standard common-block variable reference.
Relative address + Virtual page offset = Network address For example: 12340 + 400000 = 412340 This network address is transmitted to all SCRAMNet+ SC150e nodes and is written to that address. In nodes where the address does not exist in SCRAMNet+ SC150e memory, the write is ignored.
The ability for a computer to write a copy of data to a local fast memory for quicker access later must be turned off during a SCRAMNet+ SC150e memory read. Since other nodes may be changing the data, it is critical that the processor read the data directly from SCRAMNet+ SC150e memory.
OPERATION 5.3 Initialization The initialization of the SCRAMNet+ SC150e node from a cold boot is determined by the settings of the EEPROM. No fiber-optic cable connections are required to perform a read/write to the local host’s SCRAMNet+ SC150e memory. When the control registers CSR0 and CSR2 are set to zero the SCRAMNet+ SC150e memory is available for access.
Bits A0 and A1 are always zero for a longword boundary. DATA VALUE This 32-bit field contains the data value in SCRAMNet+ SC150e memory that is currently being updated around the ring. When the PLUS mode is enabled, data size may vary up to 256 bytes or 1024 bytes depending on the option selected.
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To maintain a PLUS mode transmission, step 1 requires that new data is written to the SCRAMNet+ SC150e card at a rate greater than or equal to 16.7 MB/sec (this is a 32-bit write every 240 ns). Any delay in the host data write will result in failure of step 1, and a premature end to the PLUS mode transmission.
DATA TRANSFER While the SCRAMNet+ SC150e Network appears as a shared-memory system, it is still a data network. The SCRAMNet+ SC150e Network includes a series of FIFO buffers to collect data changes until they are transmitted to the other nodes. The Transmit FIFO and the Interrupt FIFO are both 1024 messages in length.
CSR0[4] back to zero so that shared-memory can again be accessed. The ACR actions are still in effect, but the ACR bytes can no longer be accessed while the ACR Enable bit is zero. Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...
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OPERATION In order for the ACR values to take effect for interrupt action, the following SCRAMNet+ SC150e CSR actions should be considered for the type of interrupt operation desired: • Host Interrupt Enable CSR0[3] to receive network interrupts • Network Interrupt Enable CSR0[8] to transmit network interrupts •...
OPERATION 5.7 Interrupt Controls SCRAMNet+ SC150e allows a processor to receive interrupts from and/or transmit interrupts to any other processors on the network, including the originating processor. Table 5-3 indicates the various sources for interrupt control. 5.7.1 Interrupt Options Table 5-3 Interrupt Controls...
Only those nodes which have the Receive Interrupt Enable ACR[0] bit set for that address will generate an interrupt signal to their host processor. The host issues a write to SCRAMNet+ SC150e shared memory. If Override Transmit Interrupt Enable CSR0[9] or ACR Transmit Interrupt Enable ACR[1] is set and Network Interrupt Enable CSR0[8] is set, then the interrupt message is transmitted (INT = 1).
OPERATION HOST TRANSMIT ENABLE WRITE CSR0[1] MUST BE ACTIVE CSR0[9] OVERRIDE TIE ACR[1] CSR0[8] NETWORK INTERRUPT ENABLE TRANSMIT TRANSMIT INTERRUPT SLOT TO NON-INTERRUPT NETWORK SLOT TO NETWORK Figure 5-2 Transmit Interrupt Logic Copyright 2007 5-12 SCRAMNet+ SC150e HARDWARE REFERENCE...
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CSR0 or CSR8. MASKED OR SELECTED INTERRUPT The masked- or selected-interrupt method requires choosing SCRAMNet+ SC150e shared-memory locations on each node to receive and/or transmit interrupts. These shared-memory locations may also be used to generate signals to external triggers. The procedure for selecting shared-memory locations for interrupts and/or external triggers is explained in paragraph 5.6: Auxiliary Control RAM.
PLACE HOST ADDRESS INTO ENABLE INTERRUPT FIFO CSR1[14] INTERRUPTS ENABLED RECEIVE ENABLE CSR0[0] MUST BE ACTIVE GENERATE WRITE CSR1 NO INTERRUPT INTERRUPT TO TO HOST TO RE-ARM HOST Figure 5-3 Receive Interrupt Logic Copyright 2007 5-14 SCRAMNet+ SC150e HARDWARE REFERENCE...
CSR1. Details are included in the SCRAMNet Network Programmer’s Reference Guide and the appropriate DLL Reference Guide for the host computer interface. Copyright 2007 5-15 SCRAMNet+ SC150e HARDWARE REFERENCE...
The Interrupt FIFO is accessed via CSR4 and CSR5. CSR5 contains the most significant seven bits of the 23-bit SCRAMNet+ SC150e interrupt address and CSR4 contains the remaining 16 bits of the interrupt address. (The 23-bit address allows for future expansion of memory).
Trigger 1 will be generated for any host write to SCRAMNet+ SC150e memory. Trigger 2 will be generated by a network write to the SCRAMNet+ SC150e memory. Pin 7 of the Auxiliary Connector is connected to TRIG1 logically OR’ed with TRIG2.
Only one mode may be selected at a time since they use the same counter/timer register (CSR13) for output. 5.10.3 Presetting Values The counter/timer register counts upward and may be preset with a value to arrive at the desired interrupt interval. Copyright 2007 5-18 SCRAMNet+ SC150e HARDWARE REFERENCE...
Many implementations of shared memory tend to rewrite data values to memory that have not actually changed. In order to reduce network traffic, the SCRAMNet+ SC150e card has the ability to compare the new value with the old value of data and avoid sending unchanged data values out on the network.
OPERATION DATA FILTER LOGIC NOTHING WRITE HOST DATUM SAME DATUM WRITE TO MEMORY READ SHARED MEMORY NETWORK RING NETWORK RING NETWORK LOGIC Figure 5-4 Data Filter Logic Copyright 2007 5-20 SCRAMNet+ SC150e HARDWARE REFERENCE...
5.11.2 HIPRO Mode WRITE The SCRAMNet+ SC150e network message is based on 32-bit longword data. If a host processor is only capable of 8- or 16-bit data transactions, then the SCRAMNet+ SC150e bandwidth is quartered or halved, respectively. For each 32-bit data transaction from the host, two 16-bit data transactions, or four 8-bit transactions will occur on the bus each requiring a SCRAMNet+ SC150e network write.
NOTE: Do not enable the Wire Loopback and Fiber-optic Loopback and/or Mechanical Switch loopback modes simultaneously. A node in Wire Loopback mode and Insert Node will create a break in the network ring that will disable all nodes. Copyright 2007 5-26 SCRAMNet+ SC150e HARDWARE REFERENCE...
SC150e memory faster than the network can absorb the data. If a CPU is capable of writing to the SCRAMNet+ SC150e memory on the PCI bus at such a rate that the Transmit FIFO becomes full (1024 deep), data could be lost. In the event that the Transmit FIFO becomes full, the hardware will automatically extend the next write cycle until the Transmit FIFO empties at least one message.
When the host performs a write to the SCRAMNet+ SC150e shared-memory, it is not immediately written to the host memory, but is first sent to the other SCRAMNet+ SC150e nodes on the network. Set CSR2[8] and CSR2[9] to enable the Write-Me-Last mode. If desired, this mode can also be used to generate interrupts to the originating node by setting CSR2[10] as well.
Bit 15 contains the Interrupt FIFO Not Empty status. If an interrupt has been received by the host processor from the SCRAMNet+ SC150e Network interrupt logic, then the Interrupt Service Routine will be invoked. Interrupts will be disabled until re- armed by writing to CSR1.
4 MB Memory..........217,808 hours 8 MB Memory..........186,721 hours Internal clock speeds: SCRAMNet+ SC150e Card crystal.... 150 MHz, +/-100 ppm 26.66 ns timer is a divide-by-four:..... 37.5 MHz 1.706 μs timer is a divide-by-256: ..... 585.9 KHz Specifications on the crystal demonstrate the precision and stability of the main clock from which all other clocks are derived.
4 MB Memory..........217,276 hours 8 MB Memory..........189,130 hours Internal clock speeds: SCRAMNet+ SC150e Card crystal.... 150 MHz, +/-100 ppm 26.66 ns timer is a divide-by-four:..... 37.5 MHz 1.706 μs timer is a divide-by-256: ..... 585.9 KHz Specifications on the crystal demonstrate the precision and stability of the main clock from which all other clocks are derived.
4 MB Memory..........187,740 hours 8 MB Memory..........185,809 hours Internal clock speeds: SCRAMNet+ SC150e board crystal ..150 MHz, +/-100 ppm 26.66 ns timer is a divide-by-four:..... 37.5 MHz 1.706 μs timer is a divide-by-256: ..... 585.9 KHz Specifications on the crystal demonstrate the precision and stability of the main clock from which all other clocks are derived.
08M = 8 MB Transmission Media. 20 = Standard FO Media 30 = Long Link FO Media Variable. Used for product variations and/or modifications Contact Curtiss-Wright Controls, Inc., regarding the availability of SC150e Card options. Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...
The recommended fiber-optic cable is 62.5/125 micron core multi-mode fiber with ST connectors. Contract Curtiss-Wright Controls, Inc., regarding the availability of fiber- optic cables. The part number for Curtiss-Wright Controls’ 62.5/125 micron fiber-optic cables is in the form: H-PR-WST23000-0 (paired 62.5/125 micron cable, 3 meters)
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TABLES Table B-1 CSR0 - General SCRAMNet+ SC150e Enable and Reset (Read/Write)........B-2 Table B-2 CSR1 - SCRAMNet+ SC150e Error Indicators (Read Only with Write/Reset for interrupts)..B-4 Table B-3 CSR2 - Node Control (Read/Write) ....................B-6 Table B-4 CSR3 - Node Information (READ ONLY)...................B-8 Table B-5 CSR4 - Interrupt Address (LSP) (READ ONLY) .................B-8...
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The registers are described using bit 0 as the Least Significant Bit (LSB). For example: Inserting 0xA7C3 in a 16-bit register would set bits 0, 1, 6, 7, 8, 9, 10, 13, and 15 ON. Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...
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CSR DESCRIPTIONS Table B-1 CSR0 - General SCRAMNet+ SC150e Enable and Reset (Read/Write) Bits Description Network Communications Mode - Bit 0 controls the receive enable, and Bit 1 controls the transmit enable. 00 None - In this mode, all communications between the node-shared memory and the network is inhibited.
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Fiber Optic Loopback CSR2[6] is disabled. This bit is invalid when the Enable Wire Loopback CSR2[7] is ON. *User access to Trigger 1 and Trigger 2 is not available on the PMC Card. Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...
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CSR DESCRIPTIONS Table B-2 CSR1 - SCRAMNet+ SC150e Error Indicators (Read Only with Write/Reset for interrupts) NOTE: Reading CSR1 will reset the latched error conditions by clearing bits 0, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, and 13.
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Fiber Optic Bypass Switch. A ‘0’ in this bit indicates that the bypass switch is installed while a ‘1’ indicates it is not installed. Fiber Optic Loopback CSR2[6] mode is dependent upon the Fiber Optic Bypass Switch being installed. Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...
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HIPRO will not work when writing two separate shortwords while using interrupts. Multiple Messages - This bit allows multiple native messages on the network. It is used in conjunction with CSR2[11], CSR2[12] and CSR2[15] to enable the BURST mode communication protocol (see below). Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...
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No Network Error Correction - This bit is used in conjunction with CSR2[12] and CSR2[14] to enable communication protocols: BURST or PLATINUM mode and the variable length message PLUS ( ) mode (see below). SCRAMNet+ SC150e Protocol Mode Definition CSR2[15] CSR2[14] CSR2[12]...
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Bits Description Node Number Count - These bits represent the total number of SCRAMNet+ SC150e nodes on the network. This value is dynamically determined by the hardware and ranges from 0 to 255 depending upon the number of nodes actually on the network.
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Bits Description 15-0 Not Used Table B-9 CSR8 - General SCRAMNet+ SC150e Extended Control Register Bits Description ID Multiplex - When set to ‘1’, CSR3 contains the T_AGE and RXID fields. Disable Holdoff - When set, this bit disables the Holdoff feature.
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CSR DESCRIPTIONS Table B-10 CSR9 - SCRAMNet+ SC150e Interrupt On-Error Mask* Bits Description Transmit FIFO Full Mask Transmit FIFO not Empty Mask Transmit FIFO 7/8 Full Mask Built In Self Test Stream (BIST) - Internal 82-bit BIST shift register output.
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CSR DESCRIPTIONS Table B-12 CSR11 - Reserved Bits Description 15-0 Not Used Table B-13 CSR12 - SCRAMNet+ SC150e Virtual Paging Register Bits Description Virtual Paging Enable. When ON, this bit enables Virtual Paging. Always zero VP_A12 VP_A13 VP_A14 VP_A15 VP_A16 Virtual Page number.
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RD_COUNT[8] programmed by CSR9[13] and CSR9[14]. RD_COUNT[9] RD_COUNT[10] RD_COUNT[11] RD_COUNT[12] RD_COUNT[13] RD_COUNT[14] RD_COUNT[15] Table B-15 CSR14 - Reserved Bits Description 15-0 Not Used Table B-16 CSR15 - Reserved Bits Description 15-0 Not Used Copyright 2007 B-12 SCRAMNet+ SC150e HARDWARE REFERENCE...
WRITE ME LAST with SELF-INTERRUPT mode SCRAMNet Protocol Mode Definition CSR2[15] CSR2[14] CSR2[12] CSR2[11] Network No Error Multiple Variable Message Size Mode Correction Message Length Maximum BURST NO MEANING PLATINUM NO MEANING 1=1024, BURST 0=256 1=1024, PLATINUM 0=256 Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...
(Valid After a Transmission from the Node) NID0 NID1 NID2 Node ID Number* NID3 NID4 NID5 NID6 NID7 When ID_MUX CSR[0] is set: Bits 7 - 0 are Transmit AGE Bits 15 - 8 are Receive ID. Copyright 2007 SCRAMNet+ SC150e HARDWARE REFERENCE...
‘0’. A value of ‘0’ prevents host-generated data from leaving the Transmit FIFO C.7 CSR6 – Reserved A 16-bit, Read-Only Curtiss-Wright Controls reserved register. C.8 CSR7 – Reserved A 16-bit, Read-Only Curtiss-Wright Controls reserved register. Copyright 2007...
CSR SUMMARY C.9 CSR8 – General SCRAMNet+ SC150e Extended Control Register Function Name 1 is CSR3=T_AGE & RXID fields ID_MUX Disable Holdoff feature DIS_HOLD Chip select to EEPROM CSR_CS0 Ext. Chip Select for AUX MICROWIRE CSR_CS1 peripheral MICROWIRE DOUT pin...
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Without this module, it could wait forever for a slave to respond if the master tries to transfer data to or from a nonexistent slave location. The bus timer prevents this by terminating the cycle. Copyright 2007 Glossary 1 SCRAMNet+ SC150e HARDWARE REFERENCE...
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DTB cycle, initiated by an interrupt handler, that reads a status/ID from an interrupter. An interrupt handler generates this cycle when it detects an interrupt request from an interrupter and it has control of the DTB. Copyright 2007 Glossary 2 SCRAMNet+ SC150e HARDWARE REFERENCE...
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-----------One of the four buses provided by the backplane. The priority interrupt bus allows interrupter modules to send interrupt requests to interrupt handler modules, and interrupt handler modules to acknowledge these interrupt requests. Copyright 2007 Glossary 3 SCRAMNet+ SC150e HARDWARE REFERENCE...
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(2) A asterisk following the name of signals that are edge-significant denotes the actions initiated by that signal occur on the falling edge. Copyright 2007 Glossary 4 SCRAMNet+ SC150e HARDWARE REFERENCE...
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If so, it stores the data and then acknowledges the transfer. The master then terminates the cycle. Copyright 2007 Glossary 5 SCRAMNet+ SC150e HARDWARE REFERENCE...
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GLOSSARY This page intentionally left blank Copyright 2007 Glossary 6 SCRAMNet+ SC150e HARDWARE REFERENCE...
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