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ARM Corstone SSE-300 Manual

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Arm® Corstone™ SSE-300 with Cortex®-M55
and Ethos™-U55 : Example Subsystem for MPS3
Revision: C
Application Note AN547
Non-Confidential
Copyright © 2020, 2021 Arm Limited (or its affiliates).
All rights reserved.
Issue C
DAI 0547C

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  • Page 1 Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 : Example Subsystem for MPS3 Revision: C Application Note AN547 Non-Confidential Issue C Copyright © 2020, 2021 Arm Limited (or its affiliates). DAI 0547C All rights reserved.
  • Page 2 Use of the word “partner” in reference to Arm's customers is not intended to create or refer to any partnership relationship with any other company. Arm may make changes to this document at any time and without notice.
  • Page 3 This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to.
  • Page 4 Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 : Issue C Example Subsystem for MPS3 - Application Note AN547 LICENCE GRANTS THE END USER LICENCE AGREEMENT FOR THE ARM SYSTEM OR SUBSYSTEM FOR AN ARM FPGA PROTOTYPING BOARD (“THE LICENCE”), LES-PRE-21902, DEFINES THE LICENCE GRANTS. DELIVERABLES Part A...

  • Page 5: Table Of Contents

    3.8.1 Manager Peripheral Expansion Low Latency Interface Memory Map (HMSTEXPPILL) ... 22 3.8.2 MSTEXPPIHL Peripheral Map ........................25 3.9 FPGA Utilization ..............................27 3.9.1 Total design utilization ............................27 4 Programmers Model ............................28 Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 5 of 64...
  • Page 6 10 Board Revision And Support ........................50 10.1 Identifying the MPS3 board revision ......................50 10.2 Bundle support for specific MPS3 board revisions.................. 50 Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 6 of 64...
  • Page 7 13.2 Debug support for Keil MDK ........................... 55 13.3 Trace support for Keil MDK ..........................57 13.4 Debug and Trace support for Arm Development Studio ............... 58 13.4.1 Establishing a Debug Session ........................58 13.4.2 Trace in Debug session ........................... 62 Copyright ©...

  • Page 8: Introduction

    The following subsections describe conventions used in Arm documents. 1.2.1 Glossary The Arm Glossary is a list of terms used in Arm documentation, together with definitions for those terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning differs from the generally accepted meaning.

  • Page 9: Typographical Conventions

    This is a reminder of something important that relates to the information you are reading. 1.3 Additional reading This document contains information that is specific to this product. See the following documents for other relevant information: Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 9 of 64...

  • Page 10: Feedback

    An explanation with as much information as you can provide. Include symptoms and diagnostic procedures if appropriate. 1.4.2 Feedback on content If you have comments on content, send an email to errata@arm.com and give: Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 10 of 64...

  • Page 11: Other Information

    The Arm Glossary is a list of terms used in Arm documentation, together with definitions for those terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning differs from the generally accepted meaning.

  • Page 12: Preface

    AN547 subsystem. The AN547 SMM is an FPGA image that is a Single Cortex-M55 FPGA implementation of the Corstone SSE-300 with Cortex-M55 and Ethos™-U55 Example Subsystem. The example subsystem uses SIE-300 and SIE-200 components with CMSDK peripherals to provide a reference design.

  • Page 13: Arm Ip Version Details

    A battery supplies power to the key storage area of the FPGA. Any keys stored in the FPGA might be lost when battery power is lost. If this happens you must return the board to Arm for reprogramming of the key.

  • Page 14: Overview

    Example Subsystem for MPS3 - Application Note AN547 3 Overview 3 Overview The AN547 SMM is a Single Cortex-M55 FPGA implementation of the Corstone SSE-300 with Cortex-M55 and Ethos-U55 Example Subsystem. The example subsystem uses SIE-300 and SIE-200 components with CMSDK peripherals to provide a reference design.

  • Page 15: Sse-300 Configuration

    Example Subsystem for MPS3 - Application Note AN547 3 Overview 3.2 SSE-300 Configuration The following tables show the configuration settings of the SSE-300 subsystem in the AN547 SMM. See the Arm® Corstone™ SSE-300 Example Subsystem Configuration and Integration Manual for full details of each configuration option.
  • Page 16 0x5A5A 0xFFFE PERIPHPPCEXP2DIS 0x5A5A 0xF000 PERIPHPPCEXP1DIS 0x5A5A 0xFE00 PERIPHPPCEXP0DIS 0x5A5A 0x1FCC MAINPPCEXP3DIS 0x5A5A 0x5A5A MAINPPCEXP2DIS 0x5A5A 0x5A5A MAINPPCEXP1DIS 0x5A5A 0xFFF1 MAINPPCEXP0DIS 0x5A5A 0xBE00 Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 16 of 64...

  • Page 17: Subsystem Static Input Values

    25'h0270FF CPU0CFGNSSTCALIB 25'h0270FF CPU0INITL1RSTDIS 1'b0 Table 3-2 : Subsystem static input values CPU0_INITSVTOR is the value for INITSVTOR0RST specified in the SSE-300 TRM. Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 17 of 64...

  • Page 18: Sie-300 Components

    See Arm ® SIE-200 System IP Technical Reference Manual and Arm® CoreLink™ SIE-300 AXI5 System IP for Embedded Technical Reference Manual. Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 18 of 64...

  • Page 19: Memory Map Overview

    The following figure shows the AN547 memory map and how it relates to the Armv8-M reference memory map. The figure includes IDAU security information for memory regions. See the Arm® CoreLink™ SIE-200 System IP for Embedded Technical Reference Manual for more information. 0x5000_0000...
  • Page 20 0x5FFF_FFFF 128MB Peripheral Peripheral Region 0x6000_0000 0x6FFF_FFFF 256MB External RAM DDR4 0x7000_0000 0x7FFF_FFFF 256MB External RAM DDR4 External 0x8000_0000 0x8FFF_FFFF 256MB DDR4 device Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 20 of 64...
  • Page 21 : Security Access is controlled by MPC. Note : Accesses to these addresses results in an AHB5 error response. Note : For security settings, control and features please refer to the Arm® Corstone™ SSE-300 Documentation. Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved.

  • Page 22: Expansion System Peripherals

    Manager Peripheral Expansion High Latency Interface HMSTEXPPIHL To support TrustZone-Arm v8M and allow Software to map these peripherals to Secure or Non-secure address space, all peripherals are mapped twice and either an APB PPC or an AHB PPC gates access to these peripherals.
  • Page 23 0x5180_0FFF QSPI Write 0x5180_1000 0x5180_1FFF 0x5180_2000 0x56FF_FFFF Reserved SRAM Memory Protection Controller 0x5700_0000 0x5700_0FFF (MPC) (Mem) QSPI Memory Protection Controller 0x5700_1000 0x5700_1FFF (MPC) Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 23 of 64...
  • Page 24 DDR4 Memory Protection Controller 0x5700_2000 0x5700_2FFF (MPC) 0x5700_3000 0x57FF_FFFF Reserved Table 3-3: MSTEXPPILL Secure Peripheral Map Reserved regions respond with RAZ/WI when accessed. Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 24 of 64...

  • Page 25: Mstexppihl Peripheral Map

    0x4930_8FFF UART5 - UART_F[3] 0x4930_9000 0x4930_9FFF Reserved 0x4930_A000 0x4930_AFFF CLCD Config Reg 0x4930_B000 0x4930_BFFF 0x4930_C000 0x4FFF_FFFF Reserved Table 3-4: MSTEXPPIHL Non-secure Peripheral Map Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 25 of 64...
  • Page 26 0x5930_AFFF CLCD Config Reg 0x5930_B000 0x5930_BFFF 0x5930_C000 0x5FFF_FFFF Reserved Table 3-5: MSTEXPPIHL Secure Peripheral Map Note Reserved regions respond with RAZ/WI when accessed. Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 26 of 64...

  • Page 27: Fpga Utilization

    Note : These numbers relate to the complete image, not individual IP blocks. The numbers must not be used to infer IP size, or the relative sizes of different IP blocks, because the implementation and system design can significantly differ. Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 27 of 64...

  • Page 28: Programmers Model

    The SMM provides access to 2GB of External DDR4 memory through the DDR4 controller. • Size: 2GB DDR4 (4GB fitted only 2GB accessible) • Address Range: 0x6000_0000 - 0xDFFF_FFFF Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 28 of 64...

  • Page 29: Ahb Gpio

    Bit [1] is SDA 0x004 SB_CONTROLC Write Clear serial control bits: Bit [0] is SCL Bit [1] is SDA Table 4-2 SBCon Register Map Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 29 of 64...

  • Page 30: Uart

    Bits [7:0] : contain the data from last command request read, valid only when bit 0 is set in CHAR_RAW. Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 30 of 64...

  • Page 31: Ethernet

    The SMM uses PL031 PrimeCell Real Time Clock Controller. A counter in the Controller is incremented every second. The RTC can therefore be used as a basic alarm function or long timebase counter. Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 31 of 64...

  • Page 32: Audio I S

    Right channel 0x014 RXBUF Receive Buffer FIFO Data Register. This is a read-only register. Bits [31:16] Left channel Bits [15:0] Right channel 0x018- RESERVED Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 32 of 64...

  • Page 33: Audio Configuration

    The SMM implements a simple SBCon interface based on I C. It configures the Cirrus Logic Low Power Codec with Class D Speaker Driver, CS42L52 part on the MPS3 board. Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 33 of 64...

  • Page 34: Fpga System Control And I/O

    FPGAIO->MISC Misc. control Bits [31:3] Reserved Bit [2] SHIELD1_SPI_nCS Bit [1] SHIELD0_SPI_nCS Bit [0] ADC_SPI_nCS Table 4-5 : System Control and I/O Registers Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 34 of 64...

  • Page 35: Serial Configuration Controller (Scc)

    Bits [31:0] DATA RW Bit [31] Start (generates interrupt on write to this bit) 0x0A8 SYS_CFGCTRL Bit [30] RW access Bits [29:26] Reserved Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 35 of 64...
  • Page 36 Primary part number in Binary Coded Bits [15:4] Decimal (BCD): Default value 0x547 = AN547 Bits [3:0] Reserved Table 4-6 : SCC Register memory map Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 36 of 64...

  • Page 37: Clock Architecture

    REFCLK24MHZ 32kHz CLK100HZ REFCLK24MHZ 100Hz CLK1HZ REFCLK24MHZ CFGCLK CFG_CLK Set by MCC SCC register clock from MCC Table 5-2 : Generated internal clocks Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 37 of 64...

  • Page 38: Sse-300 Clocks

    32MHz CPUclock AONCLK MAINCLK 32MHz Always On clock CNTCLK MAINCLK 32MHz Counter clock SLOWCLK CLK32KHZ 32KHz Slow clock Table 5-3 : SSE-300 clocks Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 38 of 64...

  • Page 39: Fpga Secure Privilege Control

    SMAINPPCEXPCLEAR[1] AHB PPC EXP 1 cfg_sec_resp SECRESPCFG cfg_non_sec MAINNSPPCEXP1[15:0] chg_ap MAINPPPCEXP1[15:0] MPC SSRAM secure_error_irq SMPCEXPSTATUS[2] Table 6-1 : Security Expansion signals connectivity Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 39 of 64...
  • Page 40 SBCon (I2C - Shield0) SBCon (I2C – Shield1) Reserved I2C DDR4 EPROM 15:9 Reserved Table 6-4 : Peripherals Mapping of APB PPC EXP 1 Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 40 of 64...
  • Page 41 User AHB interface 2 User AHB interface 3 Ethernet and USB 15:9 Reserved Table 6-6 : Peripherals Mapping of AHB PPC EXP 0 Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 41 of 64...
  • Page 42 AHB PPC EXP 1 Interface Number <n> Name Reserved DMA 1 DMA 2 DMA 3 15:4 Reserved Table 6-7 : Peripherals Mapping of AHB PPC EXP 1 Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 42 of 64...

  • Page 43: Interrupt Map

    UART 0 Receive Interrupt IRQ[34] UART 0 Transmit Interrupt FPGA System IRQ[35] UART 1 Receive Interrupt IRQ[36] UART 1 Transmit Interrupt IRQ[37] UART 2 Receive Interrupt Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 43 of 64...
  • Page 44 UART 5 Receive Interrupt IRQ[126] UART 5 Transmit Interrupt IRQ[127] UART 5 Combined Interrupt IRQ[130:128] Reserved Table 7-1 : Combined SSE-300 and FPGA System Interrupt Map Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 44 of 64...

  • Page 45: Uart Interrupts

    300 Example Subsystem. In addition, the TXOVERINT and EXOVRINT interrupt signals of all six UARTs, twelve signals in all, are logically ORed together to drive IRQ[47]. Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 45 of 64...

  • Page 46: Shield Support

    SH0_IO4 GPIO0_4 SH0_IO5 GPIO0_5 SH0_IO6 GPIO0_6 SH0_IO7 GPIO0_7 SH0_IO8 GPIO0_8 SH0_IO9 GPIO0_9 SH0_IO10 GPIO0_10 SPI3 SS – SH0_nCS Shield 0 SPI Chip Select Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 46 of 64...
  • Page 47 SBCON3 SDA – SH1_SDA Shield 1 I2C Data SH1_IO15 GPIO1_15 SBCON3 SCL – SH1_SCL Shield 1 I2C Clock Table 8-1 : Shield Alternative Function Pinout Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 47 of 64...

  • Page 48: Zip Bundle Description

    |-- DAI0547C_SSE300_with_Cortex-M55_and_Ethos-U55_FPGA_for_mps3.pdf |-- Software |-- selftest |-- apaaci |-- apclcd |-- apgpio |-- aplan |-- apleds |-- apmain |-- apmem |-- apqspi |-- aprtc Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 48 of 64...
  • Page 49 |-- aptsc |-- apuart |-- apusb |-- RTE |-- v2m_mps3 |-- an547_st.axf |-- move.bat |-- selftest_mpb.uvoptx |-- selftest_mpb.uvprojx |-- Licence.pdf |-- Release_Notes.txt |-- revision_history.txt Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 49 of 64...

  • Page 50: Board Revision And Support

    Only files modified within the directory name that align with the MPS3 board part number and revision are used by the MCC. Care must be taken to ensure that the correct directory contents are modified if required. Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 50 of 64...

  • Page 51: Using An547 On The Mps3 Board

    11.1 Pre-Requisites Before attempting to use the board, you must: • Read the Arm® MPS3 FPGA Prototyping Board Technical Reference Manual. In particular, become familiar with the description of the configuration and boot flow. You must be able to: •...

  • Page 52: Uart Serial Ports

    • 11.5 MPS3 USB Serial port drivers for Windows For information on installing drivers to support USB serial port on MPS3 see: https://community.arm.com/dev-platforms/w/docs/381/accessing-mps3-serial-ports-in-windows-10 Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 52 of 64...

  • Page 53: Mcc Memory Mapping

    64 MB DDR4 NS 0x0C00_0000 - 0x0FFF_FFFF 0x6C00_0000 - 0x6FFF_FFFF 0x7000_0000 - 0x73FF_FFFF 64 MB DDR4 S Table 11-1 : MCC memory map table Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 53 of 64...

  • Page 54: Software

    (the compiled an547_st.axf image is uncommented, which is therefore selected and selftest.axf is commented out) The MPS3 can now be booted according to the instructions in the Arm® MPS3 FPGA Prototyping Board Getting Started Guide that is supplied with the MPS3 board.

  • Page 55: Debug

    Table 13-1 : Debug Connectivity and Support 13.2 Debug support for Keil MDK Debug has been tested using Keil uVision 5.31 with Arm Keil ULINK™ Pro Armv8-M Debugger and CMSIS-DAP Armv8-M Debugger. Apply the following debug settings if using a ULINK Pro Armv8-M Debugger: •...
  • Page 56 Arm® Corstone™ SSE-300 with Cortex®-M55 and Ethos™-U55 : Issue C Example Subsystem for MPS3 - Application Note AN547 13 Debug Figure 13-1 :Keil MDK debug configuration Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 56 of 64...

  • Page 57: Trace Support For Keil Mdk

    It is planned to include trace support for SSE-300 in future versions of the Keil Tool. Please follow the announcements of tool and pack updates related to the platform. Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 57 of 64...

  • Page 58: Debug And Trace Support For Arm Development Studio

    Connected to the MPS3 using the 20-pin Cortex / 20-pin IDC / Mictor 38 port on the MPS3 as shown below: 20-pin Cortex 20-pin IDC Mictor 38 Figure 13-3 : MPS3 Board Debug Connector Locations Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 58 of 64...
  • Page 59 This will open the debug configuration window. Double left click on the Generic Arm C/C++ application, this will create a new configuration. In the connection tab, in the search bar, enter “MPS3”, and select the Cortex-M55 under Cortex-M Prototyping System (MPS3) Cortex-M55 (SSE-300 Subsystem) as shown in the example below.
  • Page 60 Next, in the Debugger tab, make sure that the run control is set to Connect only Figure 13-5 : Arm DS debug configurations - Debugger Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 60 of 64...
  • Page 61 Now click the Apply button followed by the Debug button to start your debug session. 3. Program execution at this stage can be either single-stepped or set to Run Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 61 of 64...

  • Page 62: Trace In Debug Session

    Follow steps in section 13.4.1 and before step 2. e. implement the following steps : 1. Click the Edit button next to “DTSL Options” shown below. Connect the debug probe to either 20-pin IDC / Mictor 38 for trace to work. Figure 13-7 : Arm DS debug configurations – DTSL Options Copyright ©...
  • Page 63 Example Subsystem for MPS3 - Application Note AN547 13 Debug 2. A new window will open, on the first tab select “DSTREAM 4GB Trace Buffer” as shown below: Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 63 of 64...
  • Page 64 Example Subsystem for MPS3 - Application Note AN547 13 Debug 3. On the Cortex-M55 tab, check the “Enable Cortex-M55 core trace” box and then click Apply and then OK Copyright © 2020, 2021 Arm Limited (or its affiliates). All rights reserved. Non-Confidential Page 64 of 64...

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