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D15
SW
24
2nd local
DIV
49.5MHz
2nd local
49.5MHz
6
4-6. Receiver DDS circuit
The 19.2MHz Internal reference clock produced by trans-
mitter unit (X56-312 A/3) is distributed to CN45 of the re-
ceiver unit (X55-310). It passes through Q39, Q30, and IC8,
and is input to IC7 (DDS-IC) pin6 as the Master clock. Ap-
proximately 6MHz signal is generated as the 1st-PLL Refer-
ence clock.
IC7 has a resolution of 32 bits for realizing the frequency
step minters than the 1st-PLL comparison frequency. The
generated Reference clock is output via Q12, CF1, and Q5.
CF1 is a Ceramic Filter. It is the BPF for removing unneces-
sary spurious noise included in the generated Reference
clock.
+5V
LPF
BPF
Q5
CF1
CIRCUIT DESCRIPTION /
CF2
CF3
D16
D19
SW
SW
4
6
8
IC12
1
Analog Wide
Analog Narrow
CF4
5DR
4
8
10
IC13
NXDN Narrow
NXDN Very-Narrow
Fig. 19 Demodulator circuits / 图 19 解调器电路
+5V
+5V
LPF
6
14
IC7
DDS
Q12
Fig. 20 Receiver DDS circuit / 图 20 接收机 DDS 电路
电路说明
CF5
CF7
D20
5NR
SW
10
QUAD
21
18
Q40
D17,18
DET
IC29 (A/2)
3DR
CF6
14
IC14
4-6. 接收机 DDS 电路
发射机单元 ( X56-312 A /3) 产生的 19.2M H z 内部基准时钟
被分配到接收机单元 (X55-310) 的 CN45。它通过 Q39、Q30 和
IC8，被输入到 IC7(DDS-IC) 针脚 6 作为主时钟。生成约 6MHz
信号，作为第 1 PLL 基准时钟。
I C7 具有 32 位的分辨率，用于实现小于第 1 P L L 比较频率
的频率步长。生成的基准时钟经 Q12、CF1 和 Q5 输出。CF1 是
一个陶瓷滤波器。它是消除所生成基准时钟中包含的不需要
的寄生噪声的 BPF。
+5V
LPF
LPF
5
1
IC8
NXR-800H
CN42
15
12
IC20
17
(A/2)
11 18
22
IC30
12
CN43
+5V
+5V
DIV
CN45
Q39
Q30
25
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