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GV Virtex-II DSP GVA-395 User Manual

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GVA-395
Virtex-II Hardware Accelerator
User's Manual
GV & Associates, Inc
23540 Oriente Way
Ramona, CA 92065
(760) 789-7015
www.gvassociates.com

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Summary of Contents for GV Virtex-II DSP GVA-395

  • Page 1 GVA-395 Virtex-II Hardware Accelerator User’s Manual GV & Associates, Inc 23540 Oriente Way Ramona, CA 92065 (760) 789-7015 www.gvassociates.com...
  • Page 2 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. GVA-395 INTRODUCTION AND GENERAL DESCRIPTION ...............4 1.1.1 GVA-395 DSP Demonstration Platform Block Diagram...............5 GVA-395 POWER CONFIGURATION .......................6 2.1.1 GVA-395 Power Configuration Table ....................6 INITIAL GVA-395 DIAGNOSTIC CHECK-OUT ..................6 XILINX FPGA CONFIGURATION ......................7 JTAG C ........................7...
  • Page 3 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 10.0 DP FPGA (U14) .............................20 10.1 DP FPGA (U14) I/O PCB I ..................20 AUGHTER NTERFACE 10.1.1.1 DP FPGA (U14) to PC11 and PC12 Interconnection Table ................ 20 10.2 DP FPGA HP L ................21...
  • Page 4 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 13.4 GVA-DA9762 125 MSPS 12 B D/A ......................39 13.4.1 Single-Ended Output Path ........................39 13.4.2 Differential Coupled Analog Output Path ...................39 13.4.3 GVA-DA9762 Analog Output Configuration..................39 13.4.3.1 GVA-DA9762 Analog Output Jumper Configuration Table ............... 39 13.4.3.2...
  • Page 5 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 1.0 GVA-395 Introduction and General Description The GVA-395 Modular DSP Development Platform consists of three Xilinx FPGAs. Two Virtex-II FPGAs are used for Analog Control (ACX and AC) and two Virtex-II FPGAs are used for Data Processing (DP and DPX) respectively. The DPX FPGA also serves as the primary FPGA for external communication.
  • Page 6 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 1.1.1 GVA-395 DSP Demonstration Platform Block Diagram 07/10/04...
  • Page 7 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 2.0 GVA-395 Power Configuration The GVA-395 Hardware Accelerator was delivered with Molex power connector. Care should be taken to insure that the proper power levels are applied to this power connector. The power configuration is shown in Table 2.1.1.
  • Page 8 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 4.0 Xilinx FPGA Configuration The three Xilinx FPGAs may be configured three ways. JTAG Cable Configuration To use the JTAG download cable, the jumper block must be installed on JP1 and jumper block on JP9 must be removed.
  • Page 9 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. Slave Serial Signal JP5 Connection CCLK DONE PROG INIT 4.4.1.1 EEPROM Slave Serial Programming Configuration Table 5.0 Flash EEPROM Configuration FPGA (U1) Normally, this FPGA will be configured by the serial prom (U3) which is programmed at the factory to perform the configurations operations described in Section 4.
  • Page 10 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 8.0 ACX FPGA (U10) ACX FPGA (U10) to Daughter I/O PCB Interface. . The data is then transferred to the Xilinx ACX FPGA (U10). The data may then be processed by the FPGA.
  • Page 11 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. Signal PC3 Pin No. ACX FPGA Pin Signal PC4 Pin No. ACX FPGA Pin AD2_DN0 AD3_DN0 AD2_DP0 AD3_DP0 AD2_DN1 AD3_DN1 AD2_DP1 AD3_DP1 AD2_DN2 AD3_DN2 AD2_DP2 AD3_DP2 AD2_DN3 AD3_DN3 AD2_DP3 AD3_DP3...
  • Page 12 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. Signal PC5 Pin No. ACX FPGA Pin Signal PC6 Pin No. ACX FPGA Pin DA0_DN0 DA1_DN0 DA0_DP0 DA1_DP0 DA0_DN1 DA1_DN1 DA0_DP1 DA1_DP1 DA0_DN2 DA1_DN2 DA0_DP2 DA1_DP2 DA0_DN3 DA1_DN3 DA0_DP3 DA1_DP3...
  • Page 13 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. Signal PC8 Pin No. ACX FPGA Pin Signal PC9 Pin No. ACX FPGA Pin DA2_DN0 DA3_DN0 AD26 DA2_DP0 DA3_DP0 AE26 DA2_DN1 DA3_DN1 AD28 DA2_DP1 DA3_DP1 AE28 DA2_DN2 DA3_DN2 AE25 DA2_DP2...
  • Page 14 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. ACX FPGA HP Logic Analyzer Mictor Connector Signal HC1 Pin No. ACX FPGA Pin No. No Connection No Connection No Connection No Connection HP0_SIG0 HP0_SIG1 HP0_SIG2 HP0_SIG3 HP0_SIG4 HP0_SIG5 HP0_SIG6...
  • Page 15 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. ACX FPGA 256K X 16 ZBT RAM Each Virtex-II FPGA has access to a 256K x 18 ZBT RAM. The access time for each Static RAM is 7.5 nanoseconds. Refer to the data sheet for the IDT71V3558 for more detailed information. The interconnection is shown in the table below.
  • Page 16 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. ACX FPGA- AC FPGA XBUS Configuration. Signal ACX Pin No. AC Pin No. Signal ACX Pin No. AC Pin No. XBUS0 AH11 AH11 XBUS50 AL12 AL12 XBUS1 XBUS51 AF14 AF14...
  • Page 17 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 9.0 AC FPGA (U12) AC FPGA (U12) to Daughter I/O PCB Interface. . The data is then transferred to the Xilinx AC FPGA (U12). The data may then be processed by the FPGA.
  • Page 18 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. AC FPGA HP Logic Analyzer Mictor Connector Signal HC1 Pin No. AC FPGA Pin No. No Connection No Connection No Connection No Connection HP1_SIG0 HP1_SIG1 HP1_SIG2 HP1_SIG3 HP1_SIG4 HP1_SIG5 HP1_SIG6...
  • Page 19 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. AC FPGA 256K X 16 ZBT RAM Each Virtex-II FPGA has access to a 256K x 18 ZBT RAM. The access time for each Static RAM is 7.5 nanoseconds. Refer to the data sheet for the IDT71V3558 for more detailed information. The interconnection is shown in the table below.
  • Page 20 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. AC FPGA - DP FPGA XBUS_A Configuration. Signal AC Pin No. DP Pin No. Signal AC Pin No. DP Pin No. XBUS_A0 AD25 XBUS_A50 AG33 XBUS_A1 AE24 XBUS_A51 AF33 XBUS_A2...
  • Page 21 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 10.0 DP FPGA (U14) 10.1 DP FPGA (U14) to Daughter I/O PCB Interface. . The data is then transferred to the Xilinx DP FPGA (U14). The data may then be processed by the FPGA.
  • Page 22 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 10.2 DP FPGA HP Logic Analyzer Mictor Connector Signal HC1 Pin No. DP FPGA Pin No. No Connection No Connection No Connection No Connection HP2_SIG0 HP2_SIG1 HP2_SIG2 HP2_SIG3 HP2_SIG4 HP2_SIG5...
  • Page 23 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 10.3 DP FPGA 1M X 16 ZBT RAM EDPh Virtex-II FPGA has Access to a 1M x 18 ZBT RAM. The Access time for DP Static RAM is 10 nanoseconds.
  • Page 24 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 10.5 DP USB Interface The Cypress CY7C68001 USB Controller (U19) is connected to both Virtex-II FPGAs (U14). An software and firmware interface design available. link design site (http://www.gvassociates.com/software.asp?prod=12). Additional documentation is also available.
  • Page 25 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 10.6 DP FPGA - DPX FPGA XBUS_B Configuration. Signal DP Pin No. DPX Pin No. Signal DP Pin No. DPX Pin No. XBUS_B0 AH11 AH11 XBUS_B50 AL12 AL12 XBUS_B1 XBUS_B51...
  • Page 26 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 11.0 DPX FPGA (U16) 11.1 DPX FPGA 4 X 1M X 16 ZBT RAM DPX Virtex-II FPGA has access to four 1M x 18 ZBT RAMs. The access time for DPX Static RAM is 10 nanoseconds.
  • Page 27 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 11.3 DPX USB Interface The Cypress CY7C68001 USB Controller (U21) is connected to both Virtex-II FPGAs (U14). An software and firmware interface design available. link design site (http://www.gvassociates.com/software.asp?prod=12). Additional documentation is also available.
  • Page 28 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 11.4 DPX FPGA LVDS Interface This is a 32 bit LVDS bus can be used to transfer data and control between the Virtex-II FGPA (U16) and two external connectors. The 32-bit bus is broken into a 16-bit receiver bus and a 16-bit transmitter bus. Each of these two buses has the appropriate termination resistors for the LVDS interface.
  • Page 29 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 12.0 EI FPGA (U18) 12.1 EI FPGA XE_BUS Configuration. There is a 43 bit local bus that can be used to transfer data and control between the two Virtex-II Xilinx FPGAs (U10, U12, U14, U16 &...
  • Page 30 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 12.2 External Spartan Interface FPGA Connectors This is a 48 bit bus can be used to transfer data and control between the External Interface Spartan II FGPA and three external connectors. This bus can be configured for LVTTL and provides a +5V tolerant I/O capability for the GVA-395.
  • Page 31 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 13.0 Optional Daughter I/O PCBs for Analog Control FPGA (U14) Descriptions 13.1 GVA-AD9430 170 MSPS 12 Bit A/D The analog input is injected via a 50-ohm SMA connector (P1). The analog input voltage should not exceed 1.5 Vp- p.
  • Page 32 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. Bit 1 Complement 13.1.2.1 GVA-AD9430 to GVA-395 PC Connection Interface Table AC FPGA AC FPGA AC FPGA AC FPGA Signal Name PC Pin No. PC #2 Pin No. PC #3 Pin No.
  • Page 33 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. AC FPGA AC FPGA AC FPGA AC FPGA Signal Name PC Pin No. PC #6 Pin No. PC #7 Pin No. PC #8 Pin No. PC #9 Pin No. D11-...
  • Page 34 Jumper on pin 2 and Jumper on pin 2 and Jumper on pin 2 and pin 3 pin 3 pin 3 13.2.3.1 GVA-AD9432 Analog Input Jumper Configuration Table * Pin 1 is the closest pin to GV & Associates logo on the PCB. 07/10/04...
  • Page 35 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. Signal Name Signal Description PC Pin Signal Name Signal Description PC Pin AD0_D0 AD Output Bit 0 DGND Digital Ground DGND Digital Ground AD0_D11 AD Output Bit 11 AD0_D1 AD Output Bit 1...
  • Page 36 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. AC FPGA AC FPGA AC FPGA AC FPGA Signal Name PC Pin No. PC #6 Pin No. PC #7 Pin No. PC #8 Pin No. PC #9 Pin No. AD0_D0...
  • Page 37 Jumper on pin 2 and Jumper on pin 2 and Jumper on pin 2 and pin 3 pin 3 pin 3 13.3.3.1 GVA-AD6645 Analog Input Jumper Configuration Table * Pin 1 is the closest pin to GV & Associates logo on the PCB. 07/10/04...
  • Page 38 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. Signal Name Signal Description PC Pin Signal Name Signal Description PC Pin AD_OVR AD Overflow Bit AD13 AD Output Bit 13 AD_DRY AD Output Data Ready AD11 AD Output Bit 11...
  • Page 39 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. AC FPGA AC FPGA AC FPGA AC FPGA Signal Name PC Pin No. PC #6 Pin No. PC #7 Pin No. PC #8 Pin No. PC #9 Pin No. (* = 0)
  • Page 40 Differential Coupled Jumper on pin 2 and Jumper on pin 2 and Analog Output pin 3 pin 3 13.4.3.1 GVA-DA9762 Analog Output Jumper Configuration Table * Pin 1 is the closest pin to GV & Associates logo on the PCB. 07/10/04...
  • Page 41 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. Signal Name Signal Description PC Pin Signal Name Signal Description PC Pin DA0_D0 DA Output Bit 0 DGND Digital Ground DGND Digital Ground DA0_D11 DA Output Bit 11 DA0_D1 DA Output Bit 1...
  • Page 42 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. AC FPGA AC FPGA AC FPGA AC FPGA Signal Name PC Pin No. PC #6 Pin No. PC #7 Pin No. PC #8 Pin No. PC #9 Pin No. DA0_D0...
  • Page 43 3 13.5.3.1 GVA-DA9772 Analog Output Jumper Configuration Table * Pin 1 is the closest pin to GV & Associates logo on the PCB. 13.5.4 GVA-DA9772 PLL Configuration Applications requiring input data rates below 6 MSPS must disable the PLL clock multiplier and provide an external reference clock .
  • Page 44 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. Signal Name Signal Description PC Pin Signal Name Signal Description PC Pin DA_D0 DA Output Bit 0 DA_D1 DA Output Bit 1 DA_D2 DA Output Bit 2 DA_D3 DA Output Bit 3...
  • Page 45 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. AC FPGA AC FPGA AC FPGA AC FPGA Signal Name PC Pin No. PC #2 Pin No. PC #3 Pin No. PC #4 Pin No. PC #5 Pin No. DA_D0...
  • Page 46 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. AC FPGA AC FPGA AC FPGA AC FPGA Signal Name PC Pin No. PC #6 Pin No. PC #7 Pin No. PC #8 Pin No. PC #9 Pin No. DA_D0...
  • Page 47 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 14.0 GVA-395 Configuration Jumper Settings The table below describes the various setup configuration for the GVA-395 JP10 Install Enables the configuration of the FPGAs via the JTAG Connector JP3. Installed...
  • Page 48 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 15.0 GVA-395 Test Point Description Description Flash EEPROM Write Enable Flash EEPROM Chip Enable Flash EEPROM Output Enable Flash EEPROM Reset Flash EEPROM Ready Ground +3.3V +2.5V +1.5V PT7711 Sync...
  • Page 49 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 16.0 Appendix A: GVA-395 Hardware Accelerator Schematic 07/10/04...
  • Page 50 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 17.0 Appendix B: GVA-395 Self Test FGPA Schematic 07/10/04...
  • Page 51 GV-395 Virtex-II DSP Hardware Accelerator Manual GV & Associates, Inc. 18.0 Appendix C: GVA-395 Flash EEPROM Download and System Clock Configuration Spartan-II Schematic 07/10/04...

This manual is also suitable for:

Gva-ad9432Gva-ad9430Gva-ad6645Gva-ad9762Gva-ad9772