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Camera Link Area-scan Camera Interface using the FPGA5
v2.2 R.Williams 28-04-05
The HERON-FPGA and HERON-IO families are ranges of HERON modules with FPGAs, often
combined with some interface capability. The HERON-FPGA family in particular provides an FPGA
along with a large number of signals routed to general-purpose connectors. These modules are suitable for
connecting to digital cameras, where the control of the camera and image capture can be performed by the
FPGA fitted to the module.
For the development of the FPGA function, HUNT ENGINEERING provides a Hardware Interface
Layer written in VHDL. This layer allows developers to focus on the application-specific parts of the
system. All of the module hardware should be accessed using parts from the library.
Through the Camera Link Area-scan Camera example HUNT ENGINEERING provides a structured
starting point for the development of an area-scan camera interface. The example includes several
components suitable for processing a stream of camera data. It is intended to be a generic tutorial, so does
not address any camera specific issues.
History
Rev 1.0
Rev 2.1
Rev 2.2
HUNT ENGINEERING is a trading style of HUNT ENGINEERING (U.K.) Ltd, Co Reg No 3333633
Directors P.Warnes & N.J.Warnes. Reg'd office 34 & 38 North St, Bridgwater, Somerset TA6 3YD. VAT Reg'd No GB 515 8449 31
HUNT ENGINEERING
Chestnut Court, Burton Row,
Brent Knoll, Somerset, TA9 4BP, UK
Tel: (+44) (0)1278 760188,
Fax: (+44) (0)1278 760199,
Email: sales@hunteng.co.uk
Adapted from the examples for HERON-FPGA3 and HERON-FPGA4
Updated high frequency de-serializer
Removed reference to specific ISE versions
www.hunteng.co.uk
www.hunt-dsp.com
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Related Manuals for Hunt Engineering HERON
Summary of Contents for Hunt Engineering HERON
- Page 1 Removed reference to specific ISE versions HUNT ENGINEERING is a trading style of HUNT ENGINEERING (U.K.) Ltd, Co Reg No 3333633 Directors P.Warnes & N.J.Warnes. Reg’d office 34 & 38 North St, Bridgwater, Somerset TA6 3YD. VAT Reg’d No GB 515 8449 31...
- Page 2 FPGA is connected to. A HERON module has access to FIFOs for communicating with other modules in the system – there may be up to 6 input FIFOs and 6 output FIFOs. It may have additional interfaces, such as ADCs, or level-shifting buffers, allowing it to interface to the real world.
- Page 3 This tutorial assumes that the version of ISE design tool you are using is the same as the version of the camera-link example. There are application notes on the HUNT ENGINEERING CD that describe how to re-use CD example projects with different versions of ISE if this is necessary. In addition, if you are using a different synthesis environment to ISE there is an application note ‘Using VHDL tools...
- Page 4 What the Bit-stream Does The Camera Link Area-scan Camera example provided on the HUNT ENGINEERING CD includes bit-streams that can be loaded directly onto the Virtex-II, HERON-FPGA5 module. These bit-streams implement a generic area-scan camera interface, with automatic frame-size and region of interest detection and programmable region of interest for capture, and frame capture control.
- Page 5 Functional Block Diagram Automatic Region of Conn.A Camera Link Interest Detection Area-scan Area-scan Signal & Camera Interface Conn.B RS-232 Interface Capture Region of Interest HERON Frame Message Interface Control Interface Output Packing Synchronisation 511x32 HERON FIFO CoreGen Write Interface FIFO...
- Page 6 RS232 output to the camera. The example bit-streams require the camera signals to be provided on Connector A and Connector B of the HERON-FPGA5. The connections that are required are shown in the table below. Connector A/B...
- Page 7 On the FPGA5 this simply requires the fitting of 100R resistor packs to the reverse side of the board. Please ensure that if you intend to use your HERON-FPGA5 module for implementing a Camera Link interface that you specify the inclusion of the 100R termination resistor packs for your board when you place the order.
- Page 8 Camera Speeds The bit-streams supplied by HUNT ENGINEERING have been specified for operation using a Camera pixel clock frequency of 50MHz or less. There are two versions of the bitstream, one built using a Low Frequency de-serializer for pixel clocks up to 24MHz and one built using a High Frequency de-serializer for pixel clocks above 24MHz.
- Page 9 FIFO built using Block RAM. When there is any data in the CoreGen FIFO, it is read out and placed in the HERON FIFO Write Interface. The FIFO number used for output is programmed over the HSB message interface. If the HERON FIFO becomes full, eventually the CoreGen FIFO will become full and camera data will be lost.
- Page 10 decoupled from HSB. The Baud rate of the RS-232 connection can be programmed over HSB. HSB Control Registers The following table defines the control registers that can be set by sending messages to the FPGA using HSB. HSB Address Register Function Description Byte (decimal) LSB of pixel start register for Capture...
- Page 11 Bit 7 is used to reset the Auto-Region-of- Interest logic. Set to 1 to assert reset and then set to 0 to de-assert reset. One Hot setting for the HERON Output FIFO Number Register FIFO number that the data will be sent on.
- Page 12 The following table defines the status registers that can be read from the FPGA using HSB. HSB Address Register Function Description Byte (decimal) Returns the bottom byte of the ‘First-Pixel’ First Pixel 0 Register value generated by the Auto-Region-of- Interest logic. Bits 0 to 3 return the top 4-bits of the ‘First- First Pixel 1 Register Pixel’...
- Page 13 HSB Address Register Function Description Byte (decimal) Receive Data Register A read from this register returns the next data byte available in the RS-232 receive buffer. A read from this register returns the Receive Status Register number of data bytes in the RS-232 receive buffer.
- Page 14 This tutorial covers downloading a Camera Link area-scan camera interface into the application FPGA of a HERON-FPGA5, followed by building and running the example DSP program to capture and store an image captured by the camera interface. To run the tutorial, follow this sequence: Select “Getting Started”...
- Page 15 DSP module in your system. The example defaults to a DSP module in slot 1 and a HERON-FPGA5 in slot 2. Other slot positions may be used but if you do so, you will need to modify the example.c source file and, in the case of the HEPC9, the Server/Loader network file as well.
- Page 16 For this example, the software assumes that the DSP module is in slot 1 and the HERON- FPGA5 module is in slot 2. As such, the DSP will use FIFO 2 and the FPGA module will use FIFO 3.
- Page 17 .rbt file specified in the network file. For this example, we have already configured the FPGA (this can be checked by looking at the DONE LED of the HERON-FPGA5 to see that it is off), so it will be better at this point to tick the box ‘Skip FPGA’.
- Page 18 This part of the tutorial will show you how you can make some very simple modifications to the FPGA program. The example projects for ISE are shipped on the HUNT ENGINEERING CD. Using these projects will allow you to run the complete design flow, from RTL-VHDL source files to the proper bit-stream, ready to download on your HERON-FPGA board.
- Page 19 Opening the Camera Project In the tree that you have just copied from the CD, open the sub-directory. You should CamLink_Cam see some further sub-directories. holds the common project files, including a modified version of Top.vhd. Common holds the Camera Link example CamLink_Ex Below the directory you should see the following sub-directories.
- Page 20 Setting up the Configuration Package At the top of the user_ap1.vhd file there are the settings that you can use to affect your design (in this case the camera example). The idea is that settings that are often changed are found here. 1.
- Page 21 The Table below summarises the available choices: FCLK_G_DOMAIN HIGH_FCLK_G HIGH_FCLK_RD HIGH_FCLK_WR True True / False n.a. n.a. False n.a. True / False True / False In the case of example1, the correct choices are:- For the HEPC8 DIV2_FCLK FCLK_G_DOMAIN HIGH_FCLK_G HIGH_FCLK_RD HIGH_FCLK_WR True...
- Page 22 Note that the user_ap level includes a very large counter which divides the main system clock and drives the LED #4. It is then obvious to see if the part has been properly programmed and downloaded: the LED should flash. If the LED does not flash, try a hardware reset.
- Page 23 Please note: a 100R series resistor is required for every LVDS input to the Virtex-II FPGA5. This is required to ensure correct operation. Please ensure that if you intend to use your Virtex-II HERON- FPGA5 module for implementing a Camera Link interface that you specify the inclusion of the 100R termination resistor packs for your board when you place the order.
- Page 24 Output Packing and Synchronisation The component PACK_SYNC takes the frames that are output by the FRAME_CONTROL component and packs the data ready for transmission through the HERON FIFOs. How the data is packed will depend on the mode of camera operation.
- Page 25 For 4x8 mode, only the bottom data byte carries camera data. In this mode, each 32-bit word sent to the HERON FIFOs is packed with four bytes of data. The data in the bottom byte is the first pixel in time, and the data in the top byte is the last pixel in time.
- Page 26 example, to judge how much of the FPGA is used by the camera interface logic. The standard IP uses 6% of the logic in the Virtex-II 1M gate FPGA. There are also block rams used by the CoreGen FIFO, but a newly developed design would replace or re-use that FIFO.
- Page 27 When developing a new FPGA program for the HERON-FPGA5, by making a new component that interfaces to camera data in the same way, you will be able to easily insert that component into the processing chain that currently exists in the area-scan example.
- Page 28 The component will typically need to register the signals on the connectors in IOB registers inside the FPGA to meet the timing requirements of the camera output interface. It will then need to generate the signals as well as N data bits, where PIXEL_STROBE DVALID END_OF_LINE...
- Page 29 Adding New Components New components can be added to do you want, and can be made to interface to the camera data in any way you choose. However, if you want to add new components and want to use the pipelined-pixel- stream format, then you must consider the following points.
- Page 30 3. The camera is operating with a set of control signals different to what is expected by the HERON- FPGA5. Please check the User Manual for the camera type you are using. The example program supplied on the CD has been configured for a typical Camera Link camera.
- Page 31 the example program. If ROI_MODE is set to 0, the example program when rebuilt will capture the whole frame output by the camera, including any black pixels surrounding the active image.
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