Table of Contents
Advertisement
Quick Links
Advertisement
Table of Contents
Subscribe to Our Youtube Channel
Summary of Contents for Reflex PLDA XpressGX5LP-QE
- Page 1 Reference Manual Version 2.0.0 November 2015 Copyright © ReFLEX CES 2015 Contact us : email : sales@reflexces.com ReFLEX CES North America / AsiaPac / Japan ReFLEX CES Europe www.reflexces.com Phone : +1 (408) 887 5981 Phone : +33(0) 169 870 255...
- Page 2 This document is intended only to assist the reader in the use of the product. ReFLEX CES shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.
-
Page 3: Table Of Contents
XpressGX5LP-QE Reference Manual Table of Contents About this Document ............6 Additional Reading . - Page 4 XpressGX5LP-QE Reference Manual List of Tables Table 1: Board features description ............11 Table 2: Stratix V GX FPGA Resources .
- Page 5 XpressGX5LP-QE Reference Manual List of Figures Figure 1: XpressGX5LP-QE layout ............9 Figure 2: XpressGX5LP-QE block diagram .
-
Page 6: About This Document
About this Document This document has been written for design managers, system engineers, and designers of ASICs and FPGAs who are evaluating or using the ReFLEX CES XpressGX5LP-QE board. Prior knowledge of PCI Express is assumed. Additional Reading ReFLEX CES periodically updates its documentation. Please contact ReFLEX CES Technical Support or check the Web site at http://www.reflexces.com for current versions. -
Page 7: Chapter 1 Introduction
40Gbs links • • Board configuration module Power monitoring • Power-Up and reset controller • IP protection (ReFLEX CES Protocore) • FPGA configuration functionality supports • Complete FPGA configuration from Flash Devices • Flash image boot management •... -
Page 8: System Requirements
System Requirements To use XpressGX5LP-QE board features, you must install the ReFLEX CES Software Tools. The ReFLEX CES Software Tools can be downloaded from ReFLEX CES’s extranet site. You can log in to the extranet from ReFLEX CES’s web site www.reflexces.com. -
Page 9: Chapter 2 Xpressgx5Lp-Qe Architecture
XpressGX5LP-QE Reference Manual Chapter 2 XpressGX5LP-QE Architecture The XpressGX5LP-QE board is supplied by both the 12 V and 3.3 V of the PCI Express slot. The PCI Express 12 V generates 1.35 V, 1.8 V, 2.5 V, and 0.9 V voltages, while the 3.3 V generates 3.0 V voltages. These voltages are available on the mezzanine power supply daughter card, which is mounted on the XpressGX5LP-QE by default. -
Page 10: Block Diagram Of The Board
XpressGX5LP-QE Reference Manual Block Diagram of the Board The XpressGX5LP-QE board is based on an Altera Stratix V GX FPGA, as shown below: Figure 2: XpressGX5LP-QE block diagram... -
Page 11: Board Features
This module consists of two 2 Gbit Numonyx Flash devices and an Altera CPLD. The Flash devices can be programmed using ReFLEX CES's FlashPCI software. Each device is directly connected to FPGA pins. JTAG connector The JTAG connector enables FPGA configuration via an Altera USB-Blaster and Quartus. -
Page 12: Mechanical Description
XpressGX5LP-QE Reference Manual Mechanical Description The following diagram illustrates the mechanical architecture of the XpressGX5LP-QE board without the fansink mounted. Note: The overall height of the board, that is, the height of the highest component, is 14mm. Figure 3: XpressGX5LP-QE mechanical architecture... -
Page 13: Chapter 3 Xpressgx5Lp-Qe Features
XpressGX5LP-QE Reference Manual Chapter 3 XpressGX5LP-QE Features Stratix V GX FPGA Device Altera 5SGXEA7K2F40C2N or the The XpressGX5LP-QE board can be mounted with either the 5SGXEA4K2F40C2N FPGA . The following table shows the resources of each available Stratix V GX FPGA: M20K RAM M20K 18x18... -
Page 14: Table 3: Flashprom Pin Assignments On The Fpga
XpressGX5LP-QE Reference Manual The BPCONF button and SW1-4 switch on the solder side of the board are shown below: Figure 5: Board configuration solder side The following diagram shows the board configuration module: Figure 6: Max II EPM 570 board configuration module The following table shows pin assignments for the FlashPROMs on the FPGA: Flash Data Flash Address... -
Page 15: Table 4: Flashprom Pin Assignments + Fpga Configuration Signals On The Cpld
XpressGX5LP-QE Reference Manual Flash Data Flash Address Flash Control flash_data07 AU32 flash_ad07 AK29 flash_data08 AT32 flash_ad08 AM25 flash_oe1# AV25 flash_data09 AR31 flash_ad09 AM26 flash_rst1# AN28 flash_data10 AP31 flash_ad10 AL29 flash_ce1# AK30 flash_data11 AW34 flash_ad11 AL30 flash_wp1# AP27 flash_data12 AV34 flash_ad12 AR27 flash_adv1# AR28... -
Page 16: Table 5: Flash Memory Mapping
XpressGX5LP-QE Reference Manual Flash Address Flash Control FPGA Configuration CPLD Status/Control + FPGA flash_ad05 flash_rst0# max_leduser0 flash_ad06 flash_wait0 nconfig max_leduser1 flash_ad07 flash_oe0# init_done max_leduser2 flash_ad08 flash_we0# dclk_cpld flash_ad09 clrconfig# conf_rfu0 AV22 flash_ad10 flash_adv1# nstatus conf_rfu1 AR24 flash_ad11 flash_wp1# conf_done conf_rfu2 AR22 flash_ad12 flash_ce1#... -
Page 17: Board Manager
XpressGX5LP-QE Reference Manual Board Manager A second Max II CPLD is dedicated to IP protection, Configuration via Protocol (CvP), Partial Reconfiguration, and power and temperature management. The following figure shows the Max II board manager: Figure 7: Max II board manager The following table shows the pin assignments of the management signals on the CPLD and other components: Signal CPLD Pin... - Page 18 XpressGX5LP-QE Reference Manual Signal CPLD Pin FPGA or Component Pin Comment fpga_proto_misc0 FPGA: AG21 IP protection misc signals fpga_proto_misc1 FPGA: AD20 fpga_proto_misc2 FPGA: AH21 fpga_proto_misc3 FPGA: AF22 fpga_proto_misc4 FPGA: AJ21 fpga_proto_misc5 FPGA: AB24 por_VCCR_GXB Power good from GXB DC/DC converters por_VCCA_GXB ddr3_pgood Power good from DDR3L...
-
Page 19: Dedicated Clocks
XpressGX5LP-QE Reference Manual Note: This device is the last device on the JTAG chain. Dedicated Clocks The following table describes clock assignments for the board. Signal FPGA Pin Type Comment Global Clock Inputs osc_config_FPGA AV29 LVCMOS25 Single-ended 50MHz clock used for the Max II CPLDs. Osc3 p/n AK23/AL23 LVDS... -
Page 20: Transceiver Clock Tree
XpressGX5LP-QE Reference Manual Transceiver Clock Tree The QSFP+ and Extension interface links are connected to four different GxB transceivers, each featuring two reference clock inputs. These eight clock inputs are fed by the same clock frequency with a maximum skew of 40ps. The clock frequency can either be a fixed 644.53125MHz/50ppm frequency or a user-defined clock from an I²C PLL (Si570FBB0042DG). -
Page 21: Pci Express Endpoint Connector
XpressGX5LP-QE Reference Manual PCI Express Endpoint Connector The PCI Express male connector enables access to Endpoint PCI Express components as a x1, x4, or x8 PCI Express 2.0/3.0 Link. Figure 9: PCI Express connector The table below describes pin assignments for the PCI Express Endpoint connector. Shaded signals are defined as optional by the PCI Express Card Electromechanical Specification 2.0, and signals that appear bold are active signals implemented on the XpressGX5LP-QE. - Page 22 XpressGX5LP-QE Reference Manual Side B Side A PCI Express PCI Express FPGA Pin Signal FPGA Pin Signal AU36 mPETp0 connected to mPRSNT2# AU37 mPETn0 mPRSNT#1 AT38 mPERp1 RSVD AT39 mPERn1 AR36 mPETp1 AR37 mPETn1 AP38 mPERp2 AP39 mPERn2 AN36 mPETp2 AN37 mPETn2 AM38...
- Page 23 XpressGX5LP-QE Reference Manual Side B Side A PCI Express PCI Express FPGA Pin Signal FPGA Pin Signal connected to mPRSNT#2 AA37 mPETn7 mPRSNT#1 Table 9: Pin assignments for the PCI Express endpoint connector...
-
Page 24: Ddr3L Sdram
XpressGX5LP-QE Reference Manual DDR3L SDRAM The XpressGX5LP-QE features 2 independent banks of DDR3L SDRAM, each capable of addressing 4 GB in a 72-bit wide datapath. The 18 mounted devices are Micron MT41K512M8RA-125. Figure 10: DDR3L SDRAM The following table shows pin assignments for the DDR3L SDRAM: Bank 0 Bank 1 FPGA Pin... - Page 25 XpressGX5LP-QE Reference Manual Bank 0 Bank 1 FPGA Pin Signal FPGA Pin Signal ddr3_Bank0_ba0 AL16 ddr3_Bank1_ba0 ddr3_Bank0_ba1 AV19 ddr3_Bank1_ba1 ddr3_Bank0_ba2 AU16 ddr3_Bank1_ba2 ddr3_Bank0_cas# AR17 ddr3_Bank1_cas# ddr3_Bank0_cke0 AW19 ddr3_Bank1_cke0 ddr3_Bank0_cke1 ddr3_Bank1_cke1 ddr3_Bank0_CKn AN18 ddr3_Bank1_CKn ddr3_Bank0_CKp AN19 ddr3_Bank1_CKp ddr3_Bank0_cs0# AN17 ddr3_Bank1_cs0# ddr3_Bank0_cs1# ddr3_Bank1_cs1# ddr3_Bank0_d00 AJ15...
- Page 26 XpressGX5LP-QE Reference Manual Bank 0 Bank 1 FPGA Pin Signal FPGA Pin Signal ddr3_Bank0_d23 AH10 ddr3_Bank1_d23 ddr3_Bank0_d24 ddr3_Bank1_d24 ddr3_Bank0_d25 AM10 ddr3_Bank1_d25 ddr3_Bank0_d26 ddr3_Bank1_d26 ddr3_Bank0_d27 AL10 ddr3_Bank1_d27 ddr3_Bank0_d28 ddr3_Bank1_d28 ddr3_Bank0_d29 ddr3_Bank1_d29 ddr3_Bank0_d30 AU10 ddr3_Bank1_d30 ddr3_Bank0_d31 ddr3_Bank1_d31 ddr3_Bank0_d32 AA12 ddr3_Bank1_d32 ddr3_Bank0_d33 AD14 ddr3_Bank1_d33 ddr3_Bank0_d34 AA13...
- Page 27 XpressGX5LP-QE Reference Manual Bank 0 Bank 1 FPGA Pin Signal FPGA Pin Signal ddr3_Bank0_d57 AE11 ddr3_Bank1_d57 ddr3_Bank0_d58 AG12 ddr3_Bank1_d58 ddr3_Bank0_d59 AD12 ddr3_Bank1_d59 ddr3_Bank0_d60 AF11 ddr3_Bank1_d60 ddr3_Bank0_d61 AE10 ddr3_Bank1_d61 ddr3_Bank0_d62 AL12 ddr3_Bank1_d62 ddr3_Bank0_d63 AE12 ddr3_Bank1_d63 ddr3_Bank0_d64 AV11 ddr3_Bank1_d64 ddr3_Bank0_d65 AR11 ddr3_Bank1_d65 ddr3_Bank0_d66 AK11 ddr3_Bank1_d66...
- Page 28 XpressGX5LP-QE Reference Manual Bank 0 Bank 1 FPGA Pin Signal FPGA Pin Signal ddr3_Bank0_odt1 ddr3_Bank1_odt1 ddr3_Bank0_ras# AV16 ddr3_Bank1_ras# ddr3_Bank0_rst# AU17 ddr3_Bank1_rst# ddr3_Bank0_tdqs00n AA15 ddr3_Bank1_tdqs00n ddr3_Bank0_tdqs00p AA14 ddr3_Bank1_tdqs00p ddr3_Bank0_tdqs01n AD17 ddr3_Bank1_tdqs01n ddr3_Bank0_tdqs01p AD18 ddr3_Bank1_tdqs01p ddr3_Bank0_tdqs02n ddr3_Bank1_tdqs02n ddr3_Bank0_tdqs02p ddr3_Bank1_tdqs02p ddr3_Bank0_tdqs03n AP10 ddr3_Bank1_tdqs03n ddr3_Bank0_tdqs03p AN10 ddr3_Bank1_tdqs03p...
-
Page 29: Dual Qsfp+ Interface
XpressGX5LP-QE Reference Manual Dual QSFP+ Interface Figure 11: QSFP+ interface The XpressGX5LP-QE dual QSFP+ interfaces use eight FPGA GXB transceivers to enable either 2 x 40Gbps or up to 8 x 10Gpbs links. Both QSFP+ interfaces are fully independent, although they share a reference clock, as shown on the following diagram: Figure 12: Dual QSFP+ interface connections... -
Page 30: Table 11: Qsfp+ 1 Pin Assignments
XpressGX5LP-QE Reference Manual The following table shows the QSFP+ 1 pin assignments on the FPGA: Signal FPGA Pin Ctrl/cmd/RefCLK FPGA Pin qsfp1_rx0n qsfp1_int# AH27 qsfp1_rx0p qsfp1_lpmode AD26 qsfp1_rx1n qsfp1_modprs# AH25 qsfp1_rx1p qsfp1_modsel AE26 qsfp1_rx2n qsfp1_reset# AF25 qsfp1_rx2p qsfp1_scl AF26 qsfp1_rx3n qsfp1_sda AG25 qsfp1_rx3p... -
Page 31: Time Stamping On Micro Bnc
XpressGX5LP-QE Reference Manual Signal FPGA Pin Ctrl/cmd/RefCLK FPGA Pin qsfp2_tx2n qsfp2_tx2p qsfp2_tx3n qsfp2_tx3p Table 12: QSFP+ 2 pin assignments Time Stamping on Micro BNC A time stamping feature is available on the XpressGX5LP-QE via a MicroBNC connector (Samtec part#: MCS-P-P-RA-TH1): Figure 13: MicroBNC for time stamping Time stamping signals are available as following on the FPGA: MicroBNC... -
Page 32: 3.10 Extension Interface
XpressGX5LP-QE Reference Manual Signal FPGA Pin Comment pps_out Comparator pps clock input pps_cs# ADC SPI chip select pps_sdo ADC SPI data signal Pps_sclk ADC SPI clock signal pps_y Schmitt triggered pps clock input Table 13: Time stamping signals 3.10 Extension Interface An Extension interface is available on the XpressGX5LP-QE. -
Page 33: Table 15: Extension Interface Clocks
XpressGX5LP-QE Reference Manual Signal FPGA Pin Connector Pin Signal FPGA Pin Connector Pin Ext_link_tx4n Ext_link_rx4n Ext_link_tx4p Ext_link_rx4p Ext_link_tx5n Ext_link_rx5n Ext_link_tx5p Ext_link_rx5p Ext_link_tx6n Ext_link_rx6n Ext_link_tx6p Ext_link_rx6p Ext_link_tx7n Ext_link_rx7n Ext_link_tx7p Ext_link_rx7p Ext_link_d1 Ext_link_d0 Ext_link_d3 Ext_link_d2 Ext_link_d5 Ext_link_d4 Ext_link_d7 Ext_link_d6 Ext_link_d9 Ext_link_d8 Table 14: Extension interface pin assignment The Reference clock for the eight GxB links of the Extension interface can be chosen from the following four clocks (644.53125MHz or I²C clock, see Section 3.5... -
Page 34: 3.11 Leds
XpressGX5LP-QE Reference Manual 3.11 LEDs Eight user LEDs are available on the board: Figure 15: User LEDs The following table describes pin assignments for the LEDs: Signal FPGA Pin LED Name LED Color user_led0 AJ20 Yellow user_led1 AK21 Yellow user_led2 AL20 Green user_led3... -
Page 35: 3.12 Local Reset
XpressGX5LP-QE Reference Manual 3.12 Local Reset One active low reset push button (BPI) is available on the solder side of the board to enable register initialization: Figure 16: Reset button Signal FPGA Pin user_resetn Table 17: Pin assignments for the reset button... -
Page 36: 3.13 Mechanical Switches
XpressGX5LP-QE Reference Manual 3.13 Mechanical Switches Three user switches are available on the solder side of the XpressGX5LP-QE on SW1. These enable three IOs to be set to a logical ’0’ or a logical ’1’. A fourth switch (SW1-4) enables you to select the configuration bit stream to load on the FPGA during configuration. -
Page 37: 3.15 Pic
XpressGX5LP-QE Reference Manual 3.15 PIC A PIC is available on the board for IP protection purposes. It is reserved for future use. The following table shows the PIC pin assignment on the FPGA: Signal FPGA Pin pic_gpio0 AG26 pic_gpio1 AJ26 pic_gpio2 AJ24 pic_gpio3... -
Page 38: 3.16 Power Supply
XpressGX5LP-QE Reference Manual 3.16 Power Supply The XpressGX5LP-QE board is supplied by both the 12 V and 3.3 V of the PCI Express slot. These voltages are available on the mezzanine power supply daughter card, which is mounted on the XpressGX5LP-QE by default. The PCI Express 12 V generates 1.5 V, 1.8 V, 2.5 V, and 0.9 V voltages, while the 3.3 V generates 3.0 V voltages, as shown below. - Page 39 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: ReFLEX CES XpressGX5-LPA7HE-Gen3 XpressGX5-LPA4QE-Gen3 XpressGX5-LPA7SE-Gen3...
Need help?
Do you have a question about the PLDA XpressGX5LP-QE and is the answer not in the manual?
Questions and answers