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12. Each bit set to ON in the AIO Panel should output a logic-high sig-
Note:
compatible outputs. For boards with relay outputs (REL-16, PDISO-8,
and PIO-32) the output will be a relay contact closure. For boards with
open collector outputs (PIO-HV) use a pull up resistor to an appropriate
voltage to detect output state. Refer to the hardware description in this
user's guide for more details on the output's electrical specification.
13. In the Digital Output Panel under Channels, click on the output
KEITHLEY
Channels
1
2
0
8
9
10
Figure 4-8. Configuring channel 0 for output bit pattern B
14. In the Digital Output Panel under Output Bits, set the bits of
15. Measure the voltage between signal ground and each bit of the
I/O Bit Tests
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nal at the corresponding I/O terminal, reading typically about 4 volts
(minimum of 2.2 volts) at a DMM/DVM. Each bit set to OFF in the
AIO Panel should output a logic-low signal at the corresponding I/O
terminal, reading typically about 0 volts (maximum of 0.8 volts) at a
DMM/DVM. Do one of the following:
The typical values shown are valid for boards with TTL
If the bit patterns set on the AIO Panel do not agree with the
G
logic levels measured at the I/O terminals, the board is not
functioning properly. Stop here, and determine why.
If the bit patterns set on the AIO Panel agree with the logic
G
levels measured at the I/O terminals, then repeat steps 9, 10, and
11 for remaining output channels.
channel to test (channel 0 in this example) as shown in Figure 4-8.
3
4
5
6
7
11
12
13
14
15
channel 0 for bit pattern B as shown in Figure 4-8.
output port with a DMM or DVM. Make measurements at the
STA-50 terminals or the cabled mating connector that is connected to
the selected CONN-3160-D1 50-pin connector.
Output Bits
7
6
5
AA
Digital Output Panel
4
3
2
1
0
4-9
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Table of Contents
Troubleshooting
