Block Diagram; Main Block Diagram - Panasonic TH-55CX700M Service Manual

TH-55CX700M TH-60CX700M

9 Block Diagram

9.1.

Main Block Diagram

S 3.3/ S 1. 8
TUNE R
F
T U -IIC 1
EX T _IF AG C1
S 3.3/ S 1. 2
IF 0
IF AG C 1
IF AG C 0
IF 1
DVB- T
T U -IIC 1
DVB-S/S2
DE M O D
1
IF 1
IF AG C 1
41M H z
A na lo g AV
Y
R P b
L P r
L/R in x 2
O PT
Op tical O U T
HDM I1
DDC* > S T M
HPD* < S T M
HD M I_5 V _DE T * > S T M
HDM I2
DDC* > S T M
HPD* < S T M
HD M I_5V _D E T * > S T M
HDM I3
DDC* > S T M
HPD* < S T M
HD M I_5V _D E T * > S T M
S 3.3 S 1.8 S O UND _VC C
Lch:10 W I2S A M P
I2 S (MCLK /LRCLK /BCLK /S D A T [1:0 ])
X R S T /#S O S /#A M P _MU T E
Y D A 176 -Q Z
(YA M A H A )
Rch:10 W
< FE_XRST
B E- IIC
2/T /C
T U _S erial_ T S1
T U _S erial_ T S 1 / T U _S erial_ T S 1_J P
(T U _P ara_ T S1)
(T U _P ara_ T S1)
F E A IN P
Lo w -IF
S AW
F E A IN N
IF 0 A DC
F LT
IF AG C 0 DVB -C
Decode r
DVB -T
Decode r
AT S C /Q A M
Decode r
DM D
Decode r
A DC
[0 ]
V-S W
YPbP r A DC A n alog V ide o
[3:1 ]
VD A C
A -S W
A DC
(T h ru )
D A C
ARC OU T
S3 .3/ S1 .1 R x0
27 M H z
HD M I1.4
I2S
< HD M I_X R S T
< HD M I_ IR Q
R x1 HD M I
B E- IIC
HD M I1.4 R x
R x0
HD M I
M UX
HD M 2.0
S W x4
R x1
R x2
M N 86 4 HD M I2.0
77 8
R x3
HD M I2.0
A -C h ip
W ire d O R
Internal CI
SPI -IF
controller
S U B
AV
Trans P o rt De m u x
Decoder
M A IN
De c video
Dec Audio
B2R
Di gita l SI F
AT V
Di gita l C VB S
T V Decode r
E xte rna l V ide o(Ana log )
Pr e
M IB
(IPNR)
P ro cesso r
P roc ess o r
E xte rna l V ide o(HDM I)
TV E
OSD
5
A udio
D S P
EASTER
SPDI F
S W
R2R
IIC
S T M-I IC
S eri al
A D x8
C L K ST M- S erial0
G E N
24 M H z
S T B 5V F15 V
< T V _S O S
A n alo g
AM P /H P M U T E
MO N IT O ROU T M U T E
A S IC
O VP
S afety
S O S
C ircuit
< M O N _M U T E
< SP _HP _M U T E
P W M A
P W M _ENB >
P W M O U T
36
S 5/ S 3 .3 S 3. 3
De bu g eM M C
Co nn ecto r 32G b it
S C L K
S D I
M MCCL K
S D O
MMCCM D
C E # 1
X E R S T
S 3.3 S 1.5
S 1.05 S 1.0
MMCD A T 0 -7
DDR 1 .5
SPI -IF eMMC-IF
DDR3
DDR3
4G bit
DDR3
4G bit
DDR3
O S D x80 DDR3 4G bit
DDR 3
4G b it
1, 2,3 x1 6
Controller
cu rs o r 4G bit
DDR3 1866 4Gb x5
T-C O N
M ain
Vb y O ne 8 La ne (Video )
MJ C
Scale r P Q (FR C ,
S ub
3D )
LV D S -T x/
V b y O ne 4 L ane (O S D )
mi n i-LVDS -T x
V-b y-On e
D ISPEN
LO G O _ON ,BL_O N
NT _X RS T
3D _O N , BL_ S O S
KE Y SCAN/P O W ER-KEY
S 3.3
24 M H z
D-Chip
USB -HU B
GL850 G
USB 2.0 -IF
U S B 2.0
(Port 0)
HUB _XRS T <
IIC
S eri al
BE_IIC0 S eri al1
U S B 2.0
BE_IIC1 US B
(port1 )
BE_IIC2
IF
x4
AR M
U S B 3.0
(Port 2)
Common-Res et
USB 2.0
(Port 3)
SD -IF E T HER -IF
Pa rago n
R eset
C ircuit
S T B 3.3
S 3.3/ 1. 8
S5
REG S 3.3
S D X C
UHS -I
/UHS-I
SDV O LC
S DC L K ,S DC M D ,
S DD A T [3 :0 ],S DCD ,S D W P
N T 1 .5V
1G 4
DDR 3
DDR 3
DDR 3
DDR 3
N T K3 .3V
16 M b
FR_ G PA_ 0 (SP I_CS ) SP I-FLASH
12M H z FR _G PA_ 1 (SP I_C LK)
FR_ G PA_ 2 (SP I_D I)
FR_ G PA_ 3 (SP I_D O )
N T _PA N E L_ VCC _ON
N T 72324
G P IO x8
P N L 3D O N
P anel
N T _BL_ P W M 1-8 PN L TEST O N
(Tcon)
PC ID _EN
LD
TV_S U B_ O N
P
S 3.3
USB 2.0-IF
B T Modul e
S5
USB*VBUS >
USB
< OVC U R *
Po w er SW
USB -1
(C amera)
S5
USB*VBUS >
USB
< OVC U R *
Po w er SW
USB -2
S5
USB*VBUS >
H D D -US B
< OVC U R *
Po w er SW
USB -3
USB 3.0 -IF
(3.0 HDD )
S5 S T B 5.3
Fo r W ake up O n W ireless (E uro )
USB
Po w er SW
IEEE 802. 11n
W irele ss UN IT
W O W _O N _IR Q <
< PH Y _P W R _O N
> W O W _OV P
E T H E R
10 /10 0M
S T B 3.3
For uP
E E P
< EEPR O M _W P
16 k
S T B -IIC