CHAPTER ONE INTRODUCTION 1.0 GENERAL The bc630AT Real Time Clock Operation and Technical Manual provides the following information: • General Introduction. • Installation and Setup Details. • Operation and Software Interface Details. • I/O Signal Information. • Theory of Operation.
• Drives Datum’s optional LED display modules with the decoded time. 1.2 PHYSICAL AND FUNCTIONAL OVERVIEW The bc630AT is a half height IBM XT/AT bus board designed to provide a precision real time clock, decode serial time code signals, digitally synchronize multiple PC's and provide a number of other valuable timing features.
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1,000 feet below sea level to 10,000 feet above sea level. Non-Operating 1,000 feet below sea level to 20,000 feet above sea level. Datum Inc bc630AT Real Time Clock Module Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
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Hundreds of time code formats were developed - one for each agency involved. During the early 1960's the InterRange Instrumentation Group (IRIG) promoted a series of 'standard' time code formats now loosely referred to as 'IRIG Time Codes'. The bc630AT decodes two of these formats: IRIG A and IRIG B.
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Physically, the bc630AT mounts in either an XT or AT type computer. In the case of the XT, the AT's second connector is not accessed resulting in a lower number of interrupt selections available to the PC.
For example, to set the bc630AT base address to 300H, set switches 1 and 2 to the OFF position and set switches 3, 4, 5, and 6 to the ON position. Refer to Table 2-1 for a list of all the available base addresses in the PC bus and the corresponding switch settings.
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PC Bus Base Address Selection (SW1) Base Addr 200H 210H 220H 230H 240H 250H 260H 270H 280H 290H 2A0H 2B0H 2C0H 2D0H 2E0H 2F0H bc630AT Real Time Clock Module Datum Inc Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
1. Remove the computer chassis cover. 2. Select a vacant expansion slot and remove the blank rear panel bracket. Save the screw. 3. Slide the bc630AT Real Time Clock Module straight down to engage the motherboard connectors. 4. Fasten the top of the bracket to the chassis using the screw that was saved from Step 2.
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CHAPTER TWO 2.3 DEMONSTRATION DISKETTE This disk contains two executable programs that demonstrate the use of the bc630AT Real Time Clock Module. 630DEMO1.EXE Reads IRIG B, IRIG A, NASA 36, 2137 modulated and DC level shift time codes. 630DEMO2.EXE General Purpose Demo Program for all time sources, time code types and features of the bc630AT.
Section 3.2 details the use of these registers. The Control Register memory map for the bc630AT is listed in Table 3-1. The memory map for the rest of the bc630AT registers is listed in Table 3-2. The first column of these tables shows the offset from the base address of each register.
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CHAPTER THREE 3.1.2 STATUS REGISTER (STATUS - offset 07H) The bc630AT provides a read/write status byte containing the status of the Real Time Clock Module. The status byte is the only control register that is written to by the bc630AT.
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Note: This flag is set each second approximately 150 :secs after the on-time mark occurs. The bc630AT clears this flag only at Power On and with a software 'Reset' or 'Initialize' command. If utilized the user is responsible for clearing the flag.
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When initialization completes, the bc630AT searches for the designated time code and if a valid time code is not found, enters a 'flywheel' state maintaining time with the mode specified time code period.
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Enable/Disable External Flywheel Synchronization 0 = Disable External Flywheel Synchronization. 1 = Enable External Flywheel Synchronization. Enables disciplining of the bc630AT's time base during 'flywheel' periods with an external 1PPS or 1, 5, 10 MHz frequency reference if present. FILTER Enables Digital Filtering of the time source signals.
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Heartbeat. 1PPS. The bc630AT generates an interrupt to the host PC by writing the Int Reg Val to the Interrupt Register (offset 0FH) upon the occurrence of the selected interrupt source. The interrupt is asserted until the host PC reads the Interrupt Register. The PC interrupt IRQ channel that the bc630AT asserts is controlled by jumper JP-5 (See Table 4-9).
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The PC XT/AT computer requests specific data from the bc630AT by writing a coded request to the Command Register at offset 0EH. The baseboard must then wait for the command byte to be modified by the bc630AT firmware to indicate that the requested data is available at offset locations 00H through 06H.
CHAPTER THREE 3.3 SOFTWARE COMMANDS The following command bytes have been defined for version OS 3.0. Additional command bytes may be added in future versions of the bc630AT firmware. ready data byte flag offset / bits 7-4 / bits 3-0 <Request Time>...
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/ day of week (Sunday = 0 ... Saturday = 6) <Request Power Off Time> Time when computer was last turned off. Datum Inc bc630AT Real Time Clock Module Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
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/ -- -- -- -- ( -- denotes bit undefined) Note: This command is primarily intended for use when the bc630AT is programmed to synchronize to an external 1PPS or frequency reference. It can also load time in other modes (e.g.
90H to the Command Register (offset 0EH). This action will cause the bc630AT to initialize and act on the data in the Control Registers. When the bc630AT is initialized and ready to accept another command, it will return the ready flag value of 10H to the Command Register (offset 0EH).
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3.4.3 EXTERNAL EVENT CAPTURE The bc630AT has the ability to capture time in response to an external event. Use bits 0 and 1 in the Masks Register to enable the external event function and to select the active edge for capture. When the bc630AT detects the appropriate edge of the event signal it will: •...
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The heartbeats become valid at the on-time mark after the command completes. Varying temperature changes to the bc630AT may result in a small drift of the Time Code Period measurement. When this occurs the heartbeats will become slightly out of sync near the end of the one second time period (possibly a few microseconds).
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1PPS and heartbeat. For example, if the cable between the time code source and the bc630AT introduces a delay of 50 :sec, and you want to make the system act as if the time code source is sitting right next to the bc630AT, then load the value +100 into the propagation delay registers.
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As an option in the Time Code Format Select register, the RTC IC can be selected for decoding by the bc630AT and read with microsecond precision through the standard Time Request commands.
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Julian date. (i.e. number of days = 0 or greater than 365 [366 in a leap year]). If an invalid number of days is detected, the bc630AT synchronizes only the hour/min/second time in the RTC IC. The user is responsible for providing the proper day-of-week data.
When the external flywheel is enabled, the bc630AT automatically detects a valid 1PPS or 1, 5, 10 MHz frequency and, if found, adjusts the bc630AT's Time Code Period to match the one second time period of the external reference.
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Note: On a Master\Slave bc630AT network only two modules should be terminated. Any one of the bc630AT's depicted in Figure 3-1 and 3-2 can serve as a Master. The Master is the only board in the network that transmits Time and Synchronization pulses on the RS-422 lines. If more than one bc630AT is operating as a Master, the time signals are corrupted.
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Wall mount junction connector with female RJ11 mating connector. “T” connector: 2 female and 1 male RJ11 connectors. 6 conductor phone cable with RJ11 male connector. bc630AT RJ11 Port (Female mating connector) Termination: Choice of one of the following methods: ♦...
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J2. The pinouts for J2 are listed in Table 4-2. Figure 4-2 shows the orientation of the J2 pinouts. This output is used for linking bc630AT's used in a Master/Slave configuration. Regular telephone wire is used connecting the Slave bc630AT's in parallel to the master.
The “dif” value reflects the difference between the internal crystal and the external time signal. 3) No data is transmitted out the serial port when the bc630AT is set up as a Slave to decode a Master bc630AT.
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EACH CYCLE is a TTL representation of the time code carrier (high during positive half cycles, low during negative half cycles). 1PPS is a TTL signal whose rising edge occurs once per second on time. Figure 4-1 bc630AT Real Time Clock Module Connector Layout bc630AT Real Time Clock Module Datum Inc...
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DATA TX/RX (+) DATA TX/RX (-) Ground 1PPS TX/RX (-) Note: The above pinouts apply to the bc630AT version C hardware. The pinouts differ from the version A and B boards. Figure 4-2 J2 Phone Jack Pinout Orientation 1 3 5...
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Signal Description Ground PDC ENABLE* EACH CYCLE / HEARTBEAT Not Used 1PPS 14-17 Not Used Ground +5 VDC +5 VDC Datum Inc bc630AT Real Time Clock Module Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
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* 9 to 10 Grounded Return J1 11 to 12 Isolated Time Code Return (Opt) * Factory Setting, Total of 3 Jumpers. bc630AT Real Time Clock Module Datum Inc Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
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3 to 4 100 ohm Termination * 5 to 6 No Termination 7 to 8 100 ohm Termination * Factory Setting. Datum Inc bc630AT Real Time Clock Module Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
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15 to 16 IRQ11 17 to 18 IRQ12 19 to 20 IRQ14 21 to 22 IRQ15 * Factory Setting. 4-10 bc630AT Real Time Clock Module Datum Inc Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
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J6 PDC PIN #13 JUMPER 1 to 2 Heartbeat Pulse * 3 to 4 Each Cycle Clock * Factory Setting. Datum Inc bc630AT Real Time Clock Module 4-11 Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
5.2 XT/AT bus INTERFACE The XT/AT bus interface consists of the usual assortment of bus transceivers, buffers, and decoders commonly found on any microprocessor based system. The bc630AT uses an 8 bit dual port RAM for the I/O interface. Datum Inc bc630AT Real Time Clock Module Artisan Technology Group - Quality Instrumentation ...
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Table 3-1 and Table 3-2. 6.1 SETTING UP THE CONTROL REGISTERS This example shows how to program the bc630AT control registers. The bc630AT is setup to automatically detect an IRIG A, IRIG B, NASA 36 or 2137 modulated or DC level shift time code input signal, disable external event time capture, disable heartbeat pulses, disable the filter, disable external flywheel synchronization and select no interrupt sources.
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This example shows how to capture time across the XT/AT bus using the 'Request Time' command. The bc630AT COMMAND register is polled to determine when the time data is valid. Before time is requested the Timecode Period data is obtained with the 'Output Auxiliary Data' command. This data is used to compute the frequency error.
/* Load year data into Data Transfer */ /* Address Space outportb(BASE+6, 0x02); /* Load day of week data into Data /* Transfer Address Space Datum Inc bc630AT Real Time Clock Module Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
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/* initiated. Process will be /* complete in approximately two /* seconds /* Polling rate not to exceed /* 500 KHz bc630AT Real Time Clock Module Datum Inc Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
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R6. 7.1 PHASE LOCK LOOP ADJUSTMENT The following steps assume that the bc630AT is correctly mounted on a baseboard and is exposed to allow access by an oscilloscope probe. A source of IRIG B time code is required.
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DRAWING SET CHAPTER EIGHT DRAWING SET 8.0 GENERAL This chapter contains the schematic diagram, assembly drawing, and parts list for the bc630AT. Datum Inc, Bancomm Div. bc630AT Manual Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com...
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