Sony HDR-TG5 Service Manual page 13

1 2 3
USB_3.3V
A_2.8V
D_2.8V
A
D_1.2V
A_1.2V
IC1705
XX
5
1
4
3
C1727
2
XX
10V
B
R1703
XX
IC1702
XX
5
R1702
X1701
XX 1
12MHz
4
3
4 3
R1701 1 2
C1702 2
XX
C1701 XX
10V
0.1u
10V
C
A_1.2V
CLK_SYS_OUT
D
XSYS_RST
TG5E/TG5VE/TG7VE
TG5/TG5V
E
F
STABLE_RUN
BOOT_MODE_PORT0
G
H
I
J
REG_GND
K
L
05
HDR-TG5/TG5E/TG5V/TG5VE/TG7VE_L3
4 5 6 7
A_1.2V
CLK_SYS_OUT
R1738
XX
CLK_SYS_OUT
CPU,
CAMERA DSP,
IC1701 (1/6) AV SIGNAL PROCESS,
R1707
CXD4212GG-TL MODE CONTROL
XX
A7 PLL1_VCC
B7 PLL1_GND
C1705
0.1u
A6 PLL2_VCC
6.3V
B6 PLL2_GND
E1 PLL3_VCC
D1 PLL3_GND
G1 PLL4_VCC
F1 PLL4_GND
C1703 C1706
2.2u 0.1u
H1 PLL5_VCC
6.3V
6.3V
J1 PLL5_GND
K1 PLL6_VCC
L1 PLL6_GND
B3 CLK_SYS_IN
C2 CLK_AUDIO_IN
R1706
1k
G2 RESET
C1704
10p
50V
E2 PLL_MODE2
F3 PLL_MODE1
D2 PLL_MODE0
F2 PLL_BYPASS
H2 PCV
E3 TESTMODE
V4 TDI_1
U3 TCK_1
W3 TMS_1 USB_VBUS_DISCHG
T4 TDO_1
W4 RTCK_1
T3 TRST/BKTGIO_1
V1 TDI_0
T2 TCK_0
U2 TMS_0
U1 TDO_0
T1 BKTGIO_0
R1 JTAG SEL[3]
R2 JTAG SEL[2]
P2 JTAG SEL[1]
P1 JTAG SEL[0]
V2 STABLE_RUN
AA4 BOOT_MODE[4]
AA1 BOOT_MODE[3]
AA3 BOOT_MODE[2]
Y1 BOOT_MODE[1]
AA2 BOOT_MODE[0]
8 9 10
USB_3.3V
A_2.8V
D_1.2V
USB_3.3V
USB_3.3V
AVDD1 AA32
AVDD1 AB32
C1719
4.7u
AGND1 V32
6.3V
AGND1 W32
AGND1 Y32
AVDD2
V33
AVDD2 V34
AGND2 U35
C1717
AGND2
Y35
0.1u
10V
AVDD3 AA35
AGND3 W34
ADVDD AA33
ADVDD AA34
ADGND Y33
ADGND Y34
DVDD
AB33 D_1.2V
DVDD AB34
C1720
DVSS AC32 1u
DVSS
AD32
GNDS AC33
GNDS AC34
RREF AB35
R1708 R1711
620 100
± 0.5% ± 0.5%
VBUS AC35
USB_ID U32
DP W35 USB_D+
DM V35 USB_D-
USB_VBUS_CHG T34
U33
USB_VBUS_EN U34
C1722
1u
A_2.8V
AVCC R33
AVSSQ R32
R1757
XX
VRH N34
R1709 R1713
VRL P34 10k 1k
± 0.5% ± 0.5%
VRN R34
VRP N35
R1712
AIN P35
1k
± 0.5%
AOUT R35
SYS_SOUND
C1707
0.1u
Q1701
6.3V
AVCC_DAC P33 UNR31AFG0LS0
TOUCH PANEL
AVSS_DAC
P32 SELECT SWITCH
VREF N33 D_2.8V
C1716
V_OUT N32 2.8 D_2.8V
0.01u
25V
C1721
2.8
C1708 1u R1744 R1747
R1758
0.1u 1M TP_SEL2
XX 100k
6.3V
AVCC_ADC2 AG33
0
AVSS_ADC2 AE33
R1741 1k
ADC2_IN1
AM35 TP_X
ADC2_IN2 AN34 TP_Y
R1742
ADC2_IN3 AM34
1k
ADC2_IN4
AM33
AVSS_ADC1 AD35
AVCC_ADC1 AJ32
ADC1_IN1 AL35
ADC1_IN2 AK34
ADC1_IN3 AL34
ADC1_IN4
AK33
ADC1_IN5 AG35
ADC1_IN6 AF35
ADC1_IN7 D_2.8V
AK35
ADC1_IN8 AL33
AVCC_ADC0 AG32
AVSS_ADC0 AD34
R1748 1k
ADC0_IN1 AH35 KEY_AD0
R1749 1k
ADC0_IN2 AH34 KEY_AD1
ADC0_IN3
AJ35
ADC0_IN4 AH33
ADC0_IN5 AG34 MEM_SEL1
ADC0_IN6 REG_GND
AF34
R1739 1k
ADC0_IN7 AJ34 JACK_AD
R1740 1k
ADC0_IN8 AJ33 ZOOM_VR_AD
R1746
1M
R1745
1M
4-9
11 12 13 14
CPU,
CAMERA DSP,
IC1701 (2/6) AV SIGNAL PROCESS,
CXD4212GG-TL MODE CONTROL
VIN_Y7 VIN_Y[7]
D15
VIN_Y6 C15 VIN_Y[6]
VIN_Y5 B17 VIN_Y[5]
VIN_Y4 VIN_Y[4]
B16
VIN_Y3
B15 VIN_Y[3]
VIN_Y2 A15 VIN_Y[2]
VIN_Y1 VIN_Y[1]
C16
VIN_Y0
D16 VIN_Y[0]
VIN_C7 C17 VIN_C[7] LCD_PDG/LCD_Y/LCD_SNE[7]
VIN_C6 VIN_C[6] LCD_PDG/LCD_Y/LCD_SNE[6]
D17
VIN_C5 C19 VIN_C[5] LCD_PDG/LCD_Y/LCD_SNE[5]
VIN_C4 C18 VIN_C[4] LCD_PDG/LCD_Y/LCD_SNE[4]
VIN_C3 VIN_C[3] LCD_PDG/LCD_Y/LCD_SNE[3]
A19
VIN_C2
D18 VIN_C[2] LCD_PDG/LCD_Y/LCD_SNE[2]
VIN_C1 D19 VIN_C[1] LCD_PDG/LCD_Y/LCD_SNE[1]
VIN_C0 B19 VIN_C[0] LCD_PDG/LCD_Y/LCD_SNE[0]
A16 VCLK_OUT
A18 VIN_CLK_IN
EXT_CAM_CLK EXT_CAM_CLK_IN
A20
VIN_FLD A17 VIN_FLD
VIN_VD VIN_VD
D20
VIN_HD
C20 VIN_HD
C21 FLD
B21 VD
FD
D21
EXT_CAM_VD B20 EXT_CAM_VD
C1728
XX
HD/SD_IN
A21
STL_DATA[15]
A11
C11 STL_DATA[14]
B11 STL_DATA/CCDIN_A[13]
B12 STL_DATA/CCDIN_A[12]
STL_DATA/CCDIN_A[11]
D11
C13 STL_DATA/CCDIN_A[10]
B13 STL_DATA/CCDIN_A[9]
STL_DATA/CCDIN_A[8]
A12
C12 STL_DATA/CCDIN_A[7]
D13 STL_DATA/CCDIN_A[6]
STL_DATA/CCDIN_A[5]
A13
D12 STL_DATA/CCDIN_A[4]
C14 STL_DATA/CCDIN_A[3]
A14 STL_DATA/CCDIN_A[2]
STL_DATA/CCDIN_A[1]
B14
D14 STL_DATA/CCDIN_A[0]
STL_ADDR[11]
G10
H13 STL_ADDR[10]
G11 STL_ADDR[9]
STL_ADDR[8]
G12
G13 STL_ADDR[7]
H11 STL_ADDR[6]
H12 STL_ADDR[5]
STL_ADDR[4]
K10
H14 STL_ADDR[3]
J10 STL_ADDR[2]
STL_ADDR[1]
H10
J11 STL_ADDR[0]
STL_BS[1]
G14
J15 STL_BS[0]
G15 STL_RAS
STL_CAS
J16
H15 STL_WE
D6 STL_CS1
STL_CS0
C7
C6 STL_CKE
STL_CLK_OUT
A8
A9 STL_BUS_CTRL
C10 CCD_FLD
CCD_FD
B10
D10 CCD_HD
CKTG_O
C9
D9 CKTG_I
B9 CKTG_EXT
D7 CK_AD
C8 CLAMP_DUMMY
D8 CLAMP_OPB
F4 MSHUT_EN
M1 STRB_ON1
N3 STRB_ON2
N4 CAM_V/STRB_ON3
VSUB_CONT
R4
N7 DIR0A
DIR0B
K8
M7 BRK0A/EN0
H8 BRK0B
DIR1A
L9
J8 DIR1B
L8 BRK1A/EN1
H9 BRK1B
DIR2A
P8
L7 DIR2B
K7 BRK2A/EN2
BRK2B
J7
A5 SENS1A
B5 SENS1B
AE32 SENS0
SENS2
AF32
FG1A
AE35
AE34 FG1B
15 16
LCD_PDR[7]
D26 A
LCD_PDR[6] C26
LCD_PDR[5] C27
LCD_PDR[4]
B26
LCD_PDR[3] B27
LCD_PDR[2] A26
LCD_PDR[1]
A27
LCD_PDR[0] D27
C29 D_2.8V
C28 SSS R1724
XX
D29 XWEN
B
A28 XHDMI_RST
A29
R1756
D28 XX
B29 TP_SEL1
B28 TP_SEL2
LCD_PDB/LCD_C[7] A31
LCD_PDB/LCD_C[6] C30
LCD_PDB/LCD_C[5]
A30
LCD_PDB/LCD_C[4] D31
LCD_PDB/LCD_C[3] B30
LCD_PDB/LCD_C[2]
B31
LCD_PDB/LCD_C[1] C31 C
LCD_PDB/LCD_C[0] D30
LCD_CLK_OUT
A32
LCD_EXT_CLK_IN A25
LCD_HS
C25
LCD_VS/SYS_V D25 SYS_V
LCD_PDEN D24
DR_VDATA[7] C33 DR_VDATA7
DR_VDATA[6] B33 DR_VDATA6
D
DR_VDATA[5] DR_VDATA5
C34
DR_VDATA[4] D32 DR_VDATA4
DR_VDATA[3] D34 DR_VDATA3
DR_VDATA[2] DR_VDATA2
D33
DR_VDATA[1] E34 DR_VDATA1
DR_VDATA[0] D35 DR_VDATA0
DR_GHDATA[3] F33 DR_GHDATA3
DR_GHDATA[2] E33 DR_GHDATA2
DR_GHDATA[1] G33 DR_GHDATA1
DR_GHDATA[0] DR_GHDATA0
E32
DR_GSDATA[3] F34 DR_GSDATA3
DR_GSDATA[2] F32 DR_GSDATA2 E
DR_GSDATA[1] DR_GSDATA1
G34
DR_GSDATA[0] G32 DR_GSDATA0
DR_GHPILOT DR_GHPILOT
H35
DR_GSPILOT/SYS_V G35 DR_GSPILOT
R1716
47
DR_VINCK_OUT F35 DR_VINCK
DR_SCK54_OUT DR_SCK54
E35
R1717
33
IC_2201_DATA[7] IC_2201_DATA7
J32
IC_2201_DATA[6] K33 IC_2201_DATA6
F
IC_2201_DATA[5] K32 IC_2201_DATA5
IC_2201_DATA[4] IC_2201_DATA4
L34
IC_2201_DATA[3] L33 IC_2201_DATA3
IC_2201_DATA[2] L32 IC_2201_DATA2
IC_2201_DATA[1] M33 IC_2201_DATA1
IC_2201_DATA[0] IC_2201_DATA0
M32
IC_2201_FLD K34 IC_2201_FLD
C1723
R1718
XX
XX
IC_2201_IVCLK
IC_2201_VCLK_OUT K35
IC_2201_SYSCLK_OUT L35 IC_2201_SYSCLK
R1719
XX
G
R1720 22
IC_2201_MCK_OUT H32 IC_2201_MCK
R1729 22
IC_2201_LRCK_INOUT H33 IC_2201_LRCK
R1730 22
IC_2201_ADATA J33 IC_2201_ADATA
R1721 XX
256fs_OUT ADA_FCK
M29
R1722 XX
ADA_BCK
BCK_OUT M28
R1723 XX
LRCK_OUT N29 ADA_LRCK
SDI0 N28 ADA_SOA0
SDI1 P29
SDI2 P28
H
SDO0 R29 ADA_SIA0
SDO1 R28
I
J
K
VC-561 BOARD (5/11)
CPU (SIGNAL PROCESS)
L
XX MARK:NO MOUNT
NO MARK:REC/PB MODE
VC-561 (5/11)