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eInfochips Eragon 624 SOM Hardware Reference Manual

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Summary of Contents for eInfochips Eragon 624 SOM

  • Page 2 This document is provided under a license to use only with all other rights, including ownership rights, being retained by eInfochips. This file may not be distributed, copied, or reproduced in any manner, electronic or otherwise, without the express written consent of eInfochips.

  • Page 3: Table Of Contents

    Guidelines to Design Carrier Board ..................... 34 6.3.1 Power Supply ........................34 6.3.2 Boot Configuration ......................34 6.3.3 General Purpose Keys (as per Eragon624 Carrier Board) ........... 35 6.3.4 USB Interface ........................35 Version 1.0 - iii - eInfochips Confidential...
  • Page 4 SOM Board Dimensions ......................49 Shields Dimensions ........................49 Special Care when using ERAGON624 SOM Board ................51 Development Device Notice ....................... 51 Anti-Static Handling Procedure ....................51 10 About eInfochips ..........................52 Version 1.0 - iv - eInfochips Confidential...
  • Page 5 Figure 5 – Boot Configuration Switch (SW1) ..................... 35 Figure 6 – General Purpose Keys ....................... 35 Figure 7 – WCD9335 Audio Code Daughter Board (custom made by eInfochips) ........36 Figure 8 – Schematic-1 on Carrier Board for Audio Code Daughter Board ..........36 Figure 9 –...
  • Page 6 Table 12: SIM CARD_2 connector (J36) Pinout ................... 46 Table 13: Debug Port Connector (J22) Pinout .................... 47 Table 14 : Absolute Maximum Ratings ....................... 48 Table 15 : Operating Conditions ......................... 48 Version 1.0 - vi - eInfochips Confidential...

  • Page 7: Document Details

    Bluetooth Low Energy Bill of Material Bluetooth Central Processing Unit Camera Serial Interface Direct Current Double Data Rate Display Serial Interface eInfochips Giga Byte GPIO General Purpose Interface Global Positioning System High Definition Version 1.0 - 7 - eInfochips Confidential...
  • Page 8 Master Out Slave In Mega Pixel On The Go Phase Loop Locked PMIC Power Management IC Random Access Memory Radio Frequency RoHS Restriction of Hazardous Substances Receive System On Module Serial peripheral Interface Transmit Version 1.0 - 8 - eInfochips Confidential...

  • Page 9: Table 2 : Definition, Acronyms And Abbreviations

    Hardware Reference Manual UART Universal Asynchronous Interface Universal Serial Bus Android Debug Bridge WLAN Wireless LAN Table 2 : Definition, Acronyms and Abbreviations Version 1.0 - 9 - eInfochips Confidential...

  • Page 10: References

    Hardware Reference Manual 1.3 References Document Version Remarks ERAGON624 SOM Schematic File ERAGON624 Carrier Schematic File Table 3 : References Version 1.0 - 10 - eInfochips Confidential...

  • Page 11: License Agreement

    Hardware Reference Manual 2 License Agreement The use of this document is subject to and governed by those terms and conditions in the eInfochips Ltd. Purchase and Software License Agreement for the APQ8053 based development platform, which you or the legal entity you represent, as the case may be, accepted and agreed to when purchasing ERAGON624 development platform from eInfochips Ltd.

  • Page 12: Preface

    It comes with Android software packages. This platform enables developers to evaluate and create solutions targeted at various market segments while customers and OEMs can build their products based on these designs directly or with customizations. Version 1.0 - 12 - eInfochips Confidential...

  • Page 13: Overview

    With variety of peripherals, SOM is targeted for wide range of applications supporting bulk storage, faster connectivity, higher through put and performance at lower power. Version 1.0 - 13 - eInfochips Confidential...

  • Page 14: Key Features

    Voltage In: 3.8V (VBATT+) on J4805 connector SOM: 60mm x 35mm  from Carrier Board (J13) Storage Temperature Range: o -20 to 70° C  Operating Temperature Range: o 0 to 60° C Version 1.0 - 14 - eInfochips Confidential...

  • Page 15: Applications

     Security & Surveillance  Biometric Access Control Systems  Home and Health Hub  Human-machine interface  Home energy management systems  In-flight entertainment  Intelligent industrial control systems  Portable medical Version 1.0 - 15 - eInfochips Confidential...

  • Page 16: Getting Started

    Hardware Reference Manual 5 Getting Started Prerequisites Before user power up the ERAGON 624 SOM board for the first time, will need following things:  Eragon 624 Carrier Board or Carrier Board with Exact Pin-outs and mating connectors  WiFi BT U.FL connector on SOM should be connected to Antenna on Carrier Board ...

  • Page 17: System Block Diagram

    Hardware Reference Manual System Block Diagram Figure 1 – ERAGON 624 SOM Block Diagram Version 1.0 - 17 - eInfochips Confidential...

  • Page 18: Eragon624 Board Image

    Hardware Reference Manual ERAGON624 BOARD IMAGE Figure 2 – ERAGON624 SOM Top View Figure 3 – ERAGON624 SOM BOT View Version 1.0 - 18 - eInfochips Confidential...
  • Page 19 Hardware Reference Manual The ERAGON 624 SOM offers a wide boost of interfaces and peripherals, including several high-speed signals through its edge connectors. The ERAGON624 SOM and Carrier are interfaced through three Hirose DF40C-100DP-0.4V Connectors. The pin outs for these three connectors is described below,...
  • Page 20 J11.45 MIPI_CSI0_CLK_P MIPI CSI0 Clock Positive J5.46 J11.46 Ground J5.47 J11.47 MIPI_CSI0_CLK_N MIPI CSI0 Clock Negative J5.48 J11.48 MIPI_DSI1_LANE0_N MIPI DSI1 Lane0 Negative J5.49 J11.49 Ground J5.50 J11.50 MIPI_DSI1_LANE0_P MIPI DSI1 Lane0 Positive Version 1.0 - 20 - eInfochips Confidential...
  • Page 21 Ground J5.71 J11.71 MIPI_CSI0_LANE3_N MIPI CSI0 Lane3 Negative J5.72 J11.72 MIPI_DSI0_CLK_N MIPI DSI0 Clock Negative J5.73 J11.73 Ground J5.74 J11.74 MIPI_DSI0_CLK_P MIPI DSI0 Clock Positive J5.75 J11.75 CSI1_RST CSI1 Reset GPIO Signal 1.8V Version 1.0 - 21 - eInfochips Confidential...
  • Page 22 24Mhz Master Clock 1 signal 1.8V J5.96 J11.96 MIPI_DSI0_LANE2_P MIPI DSI0 Lane2 Positive J5.97 J11.97 Ground J5.98 J11.98 MIPI_DSI0_LANE2_N MIPI DSI0 Lane2 Negative J5.99 J11.99 CAM_MCLK0 24Mhz Master Clock 0 signal 1.8V J5.100 J11.100 Ground Version 1.0 - 22 - eInfochips Confidential...
  • Page 23 J4805.18 J13.18 VBAT 3.5V-4.4V Input voltage J4805.19 J13.19 Ground J4805.20 J13.20 Ground J4805.21 J13.21 Ground J4805.22 J13.22 Ground J4805.23 J13.23 Ground J4805.24 J13.24 Ground J4805.25 J13.25 VBUS_USB_IN USB Input from the USB 3.0 Connector Version 1.0 - 23 - eInfochips Confidential...
  • Page 24 USB 3.0 Superspeed receive positive J4805.46 J13.46 AUDIO_INT1 Audio codec interrupt 1 J4805.47 J13.47 USB3_SS_RX_M USB 3.0 Superspeed receive negative J4805.48 J13.48 AUDIO_INT2 Audio interrupt 2 J4805.49 J13.49 Ground J4805.50 J13.50 PMIC_SPKR_DRV_M PMIC speaker out negative Version 1.0 - 24 - eInfochips Confidential...
  • Page 25 J4805.71 J13.71 F_LED1 Flash LED out J4805.72 J13.72 PMIC_MIC1_IN_P PMIC MIC1 Input positive J4805.73 J13.73 LCD_BL_LED_A Display backlight LED anode J4805.74 J13.74 EAR0_M Earpiece out negative J4805.75 J13.75 USB_CC1 USB type C input CC1 Version 1.0 - 25 - eInfochips Confidential...
  • Page 26 VCOIN Coil cell voltage J4805.97 J13.97 AUDIO_SLIMBUS_D0 Audio slimbus Data 0 J4805.98 J13.98 VREG_L12_VDDPX2_SDC PMIC LDO12 output voltage 2.95 J4805.99 J13.99 AUDIO_SLIMBUS_D1 Audio slimbus Data 1 J4805.100 J13.100 VREG_L22_2P8 PMIC LDO22 output voltage Version 1.0 - 26 - eInfochips Confidential...
  • Page 27 J4804.20 J16.20 BLSP5_UART_RX BLSP5 UART RX J4804.21 J16.21 SDC2_SDCARD_D0 SDC2 SDCARD Data 0 1.8/2.95 J4804.22 J16.22 Ground J4804.23 J16.23 SDC2_SDCARD_CLK SDC2 SDCARD clock 1.8/2.95 J4804.24 J16.24 HDMI_RST_N HDMI Reset J4804.25 J16.25 SDCARD_DET_N SDCARD Detect Version 1.0 - 27 - eInfochips Confidential...
  • Page 28 J4804.45 J16.45 MAG_DRDY_INT Magnetometer Interrupt J4804.46 J16.46 LED_GPIO2 GPIO9/Blue LED control J4804.47 J16.47 GYRO_INT Gyro meter Interrupt J4804.48 J16.48 HDMI_INT_GPIO GPIO 54/HDMI Interrupt J4804.49 J16.49 ACCL_INT1 Accelerometer Interrupt J4804.50 J16.50 MI2S_2_D0 MI2S2 Data0 Version 1.0 - 28 - eInfochips Confidential...
  • Page 29 MI2S1 Word Sync J4804.70 J16.70 MI2S_1_D2 MI2S1 Data2 J4804.71 J16.71 MAG_INT Magnetometer Interrupt J4804.72 J16.72 MI2S_1_D1 MI2S1 Data1 J4804.73 J16.73 TEMP_INT Temperature sensor Interrupt J4804.74 J16.74 Ground J4804.75 J16.75 FORCE_USB_BOOT Force USB Boot Version 1.0 - 29 - eInfochips Confidential...
  • Page 30 J16.95 PRI_MI2S_MCLK_B MI2S mater clock B J4804.96 J16.96 Ground J4804.97 J16.97 Ground J4804.98 J16.98 PMI_HAP_OUT_N PMI Haptics Out negative J4804.99 J16.99 PRI_MI2S_MCLK_C MI2S mater clock C J4804.100 J16.100 PMI_HAP_OUT_P PMI Haptics Out positive Version 1.0 - 30 - eInfochips Confidential...

  • Page 31: Major Blocks Of Eragon624 Som Module

    Flash 10.x and video processor decode optimization. Connectivity  8, 4-bits each BLSP Ports which can be configured as UART, I2C and SPI.  One USB 3.0/2.0 Port.  Gigabit Ethernet connectivity on Carrier card in USB3.0 HOST mode. Version 1.0 - 31 - eInfochips Confidential...

  • Page 32: Memory Interface

    6.2.2 Memory Interface In ERAGON 624 SOM APQ8053 integrates with single Embedded Multi Chip Package (eMCP) has dual function of LPDDR3 RAM and eMMC v5.1 flash. SOM supports up to 4GB of LPDDR3 RAM at max. 933MHz clock and 64GB of eMMC flash.

  • Page 33: Pmic Interface

    LED4 (Green LED): Indicates that VPH power supply generated. 6.2.7 Shielding Shields are Mounted on the WiFi (Top) Section, Processor + PMIC + eMMC (Top/Bottom) section & GPS section (Top), as per the FCC requirement for Single Module Certification. Version 1.0 - 33 - eInfochips Confidential...

  • Page 34: Guidelines To Design Carrier Board

    SDC2 -> SDC1 -> USB 3.0 SDC1 -> USB 3.0 USB 3.0 Table 4: ERAGON 624 BOOT Configuration options CONFIG switch in ON position indicates level 1. To boot through eMCP make sure switch is 0000. Version 1.0 - 34 - eInfochips Confidential...

  • Page 35: General Purpose Keys (As Per Eragon624 Carrier Board)

    ERAGON624 SOM can support PMIC’s internal codec. On the carrier Board, WCD9335 daughter board (eI PN# 17_00348_01) can be connected by Placing connector PN# DF40HC(3.0)-30DS-0.4V(51). This daughter board also has WSA8810 audio amplifier interfaced with codec. Version 1.0 - 35 - eInfochips Confidential...

  • Page 36: Figure 7 - Wcd9335 Audio Code Daughter Board (Custom Made By Einfochips)

    J19, Female headers J17 & J18. These Provisions can be given to carrier board for Audio interfaces. Figure 7 – WCD9335 Audio Code Daughter Board (custom made by eInfochips) Below is the Schematic portion for J28 & J29 to connect the Audio Daughter Board. For layout spacing, need to contact to eInfochips.

  • Page 37: Figure 9 - Schematic-2 On Carrier Board For Audio Code Daughter Board

    Hardware Reference Manual Figure 9 – Schematic-2 on Carrier Board for Audio Code Daughter Board Figure 10 – Audio Headset Jack Figure 11 – Audio Headset Jack schematic Version 1.0 - 37 - eInfochips Confidential...

  • Page 38: Figure 12 - Analog And Digital Codec Headers (J17 & J18)

    Ground J17.9 CDC_SPEAKER1_OUT_P Speaker1 Output Positive J17.10 CONN_CDC_MIC4_P MIC4 Input Positive J17.11 CDC_SPEAKER1_OUT_M Speaker1 Output Negative J17.12 Ground J17.13 CDC_EAR_M Earpiece Output Negative J17.14 CDC_SPEAKER2_OUT_P Speaker2 Output Positive J17.15 CDC_EAR_P Earpiece Output Positive Version 1.0 - 38 - eInfochips Confidential...

  • Page 39: Sensors

    (SD card). SD card is interfaced with APQ8053 (on SOM) through 4-bit SDC2 data signals along with SDC2 clock and SDC2 command signals. GPIO_133 of APQ8053 is used to detect SD card insertion and removal. Version 1.0 - 39 - eInfochips Confidential...

  • Page 40: Dsi To Hdmi

    MI2S_1 interface from the APQ8053 chip which is mentioned in the below block. The ERAGON624 carrier should contains the 14 pin HDMI Audio Connector to connect to the Bridge Board. Version 1.0 - 40 - eInfochips Confidential...

  • Page 41: Hdmi To Csi Audio Interface

    The ERAGON624 contains the 16 pin HDMI Audio Connector (J27) on the board. A 6-wire (audio input) I2S channel is routed directly from the APQ8053 SoC I2S interface pins to the HDMI to CSI Bridge Board through HDMI Audio connector. Version 1.0 - 41 - eInfochips Confidential...

  • Page 42: Wifi + Bt Chip Antenna

    Fractus chip antenna FR05-S1-NO-1-004 (ref ANTENNA1) to radiate. During the design of carrier Board, customer needs to use the same chip Antenna on application Board. For Placement & routing of the Antenna on Carrier Board, contact eInfochips to get the detailed information.

  • Page 43: Gps Chip Antenna

    Board Design. This 4G module is interfaced with second downstream port of USB Hub (it can be used to expand USB ports) through which it is connected to APQ8053 processor, MI2S_2 interface, BLSP4 UART interface and few other GPIOs of APQ8053 and Dual SIM card connectors (SIM1-J38, SIM2-J36). For more details, contact eInfochips. Version 1.0 - 43 -...

  • Page 44: Figure 18 - M.2 Connector (J35)

    LED Driver Control GPIO J35.11 Ground J35.12 Not Connected J35.13 Not Connected J35.14 Not Connected J35.15 Not Connected J35.16 Not Connected J35.17 Not Connected J35.18 Not Connected J35.19 Not Connected J35.20 MI2S_2_SCK I2S_2 Bit Clock Version 1.0 - 44 - eInfochips Confidential...
  • Page 45 Not Connected J35.54 Not Connected J35.55 Not Connected J35.56 Not Connected J35.57 Ground J35.58 Not Connected J35.59 TP26 Test Point J35.60 BLSP1_SPI_MISO GPIO for Coexistence J35.61 TP27 Test Point J35.62 BLSP4_UART_TX Coexistence UART Transmit Version 1.0 - 45 - eInfochips Confidential...

  • Page 46: Table 10: M.2 Connector (J35) Pinout

    SIM2 Reset Signal J36.3 SIM2_CLK_ESD SIM2 Clock J36.4 Ground J36.5 Vpp Output J36.6 SIM2_DATA_ESD SIM2 Data J36.7 SIM2_DETECT SIM2 Card Detect J36.8 to J36.17 SIM_SHEILD_GND Shield Ground Table 12: SIM CARD_2 connector (J36) Pinout Version 1.0 - 46 - eInfochips Confidential...

  • Page 47: Rtc

    Pin Number Net Name Pin Function J22.1 VBUS_5V USB 5V Supply J22.2 USB_DEBUG_DM USB Data Negative J22.3 USB_DEBUG_DP USB Data Positive J22.4 Not Connected J22.5 Ground Table 13: Debug Port Connector (J22) Pinout Version 1.0 - 47 - eInfochips Confidential...

  • Page 48: Electrical Specification

    Table 14 : Absolute Maximum Ratings Operating Conditions Parameter Unit VBATT+ Main Battery Input Supply Voltage 4.75 VCOIN RTC Input Supply Voltage 3.25 USB_VBUS USB VBUS Input Supply Voltage Table 15 : Operating Conditions Version 1.0 - 48 - eInfochips Confidential...

  • Page 49: Mechanical Specification

    Hardware Reference Manual Mechanical Specification SOM Board Dimensions Figure 22 – SOM Module Dimension Shields Dimensions Figure 23 – SOM Module TOP side Shields Version 1.0 - 49 - eInfochips Confidential...

  • Page 50: Figure 24 - Som Module Bot Side Shield

    Hardware Reference Manual Figure 24 – SOM Module BOT side Shield Version 1.0 - 50 - eInfochips Confidential...

  • Page 51: Special Care When Using Eragon624 Som Board

    Anti-Static Handling Procedure This device has exposed PCB and chips. Accordingly, proper anti-static precautions should be employed when handling the kit, including: Use a grounded anti-static mat Use a grounded wrist or foot strap Version 1.0 - 51 - eInfochips Confidential...

  • Page 52: About Einfochips

    5% of our revenues are earmarked for building reusable IPs that will accelerate product design cycles and reduce product risks. About 80% of eInfochips business comes from companies with revenues over $1 Billion, and 60% of total business from building life and mission critical products. eInfochips has the experience, expertise and infrastructure to deliver complex, critical and connected products.
  • Page 53 FCC Warning This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Any Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.
  • Page 54 IC Warning This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation. Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.

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