Summary of Contents for Seiko Epson E0C5251
- Page 1 MF1329-01 E0C5251 CMOS CALLING NUMBER IDENTIFICATION RECEIVER IC ECHNICAL ANUAL...
- Page 2 Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products.
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Page 3: Table Of Contents
5.9.1 Serial Interface AC Characteristics....................24 5.9.2 FSK Demodulated Data Read Mode ..................25 5.9.3 CAS Detection Circuit Control-Register Write Mode.............25 5.10 E0C5251 Timing Chart .............................26 5.10.1 Bellcore On-Hook Data Transfer....................26 5.10.2 Bellcore Off-Hook Data Transfer....................26 5.10.3 BT Idle State CLI Service ......................27 5.10.4 BT Loop State CLI Service ......................27... - Page 4 CONTENTS 5.11 External Wiring Diagram (Example) ......................28 5.11.1 Example of Bellcore-Compatible Telephone Circuit............28 5.11.2 Example of Bellcore-Compatible Auxiliary Circuit..............29 6 Package ........................30 7 Pad Layout........................31 7.1 Pad Layout Diagram............................31 7.2 Pad Coordinates ..............................31 EPSON E0C5251 TECHNICAL MANUAL...
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Page 5: Overview
1 OVERVIEW Overview The E0C5251 (CAS + FSK IC), an upgraded version of the E0C5250, is a CMOS IC for calling number identification with the Call Waiting function. It provides an interface to various call information delivery services based on Bellcore GR-30-CORE, such as CND (Calling Number Delivery), CNAM (Calling Name Delivery), and CIDCW (Calling Identity on Call Waiting), as well as British Telecom’s CLIP (Calling Line Identification Service) and Cable Communications Association’s CDS... -
Page 6: Block Diagram
SOP2-28pin DIP-28pin E0C5251 E0C5251 Pin name Pin name Pin name Pin name HOOK OSC3 #IRQ RDIN OSC4 #SCLK #RDRC EXTCLK CASIN #RDET MODE0 CASFB PDWN MODE1 CDIN #RESET #PQUAL BPOUT EXTREF #DET Figure 1.3.1 Pin assignment EPSON E0C5251 TECHNICAL MANUAL... -
Page 7: Pin Description
RDIN Schmitt Active Ring Detect Input: The attenuated ring signal is connected to this pin trigger input for the ring detection. This circuit is always active even if the device is in the power down mode. EPSON E0C5251 TECHNICAL MANUAL... - Page 8 FSK energy and off-hook detection mode is disabled. Refer to Table 3.2.1 for more details. #PQUAL Output High level Pre-qualification Output: Early qualification output will be monitored at this pin. When no tones are detected, this pin stays at high level. EPSON E0C5251 TECHNICAL MANUAL...
- Page 9 CDIN pin. The band pass filter output is monitored at this pin for internal testing purpose. Do not connect any external components except this capacitor to this pin. Excess load may cause improper operation of the circuit. Power Device Power Supply: Positive power supply pin. supply (+) EPSON E0C5251 TECHNICAL MANUAL...
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Page 10: Power Supply Block And Initial Reset
The following shows the operating power supply voltage of the E0C5251. Power supply voltage: 2.7 V to 5.5 V The E0C5251 is operated in the above voltage range by a single power supply that is connected between V . The voltage required for internal operation (V = 1/2 V ) is generated by the IC itself. -
Page 11: Functional Description
The CPU can access these CPU interface registers through the serial interface pins (SDI, #SCLK, and MODE0) and control the mode of the E0C5251. The CPU uses the first four bits of transmit data to specify the address A[3:0] of the internal register to be accessed. - Page 12 CASIN pin. If this bit is set to 0 when the MODE0 pin is high, the CAS signal can be input to the INP/INN pin. TEST Test mode selection This bit is used to test the IC. This bit normally must be fixed to 0. EPSON E0C5251 TECHNICAL MANUAL...
- Page 13 GH1 and GH0 change the gain in increments of 1 dB, whereas GH3 and GH2 change the gain in increments of 4 dB. The alert-tone detection level is attenuated (sensitivity is lowered) by an amount equal to the total gain set here. EPSON E0C5251 TECHNICAL MANUAL...
- Page 14 Table 3.1.6 AVR register Initial Bit name Description value X011 Average counter divide-ratio selection These bits control the frequency divide ratio of the internal average counter. Setting to 011 is recommended. AV2 AV1 Divide ratio 1/16 1/32 1/64 EPSON E0C5251 TECHNICAL MANUAL...
- Page 15 1.37, -1.32 1.45, -1.39 1.53, -1.46 1.61, -1.54 1.69, -1.61 Bit setting 0001 is Bellcore’s default value. Bit setting 0010 corresponds to British Telecom Loop State service and setting 1001 corresponds to British Telecom Idle State service. EPSON E0C5251 TECHNICAL MANUAL...
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Page 16: Outputs From The #Rdet, #Irq And #Det Pins
Hook detection detection detection detection CAS detection CASIN Off-hook Hook detection detection detection detection FSK energy detection INP/INN Off-hook RING RING Power mode detection detection detection down RING detection Hook detection FSK energy FSK energy detection detection EPSON E0C5251 TECHNICAL MANUAL... -
Page 17: Input Amp Circuit
× 0. 5 62 [times] is the power supply voltage fed to the V pin of the E0C5251. For R and R , Seiko Epson recommends using a resistance of about 200 kΩ for noise prevention. Tables 3.3.1 and 3.3.2 show typical resistance values and amp gain for the case where V... -
Page 18: Single End Input
× 0.562 [t imes] is the power supply voltage fed to the V pin of the E0C5251. Tables 3.3.3 and 3.3.4 show typical resistance values and amp gain for the case where V = 5 V and V = 3 V, respectively. -
Page 19: Ring/Line Reversal Signal Detection
Figure 3.4.1 shows a typical circuit used to detect the Bellcore ring signal and British Telecom Line Reversal signal. When the E0C5251 is in power-down mode, this circuit detects the ring signal or Line Reversal signal. The Line Reversal or ring signal causes the voltage on the RDIN pin to rise, which drives the Schmitt rigger output high. This causes the Nch transistor to turn on and the #RDRC pin to change to Low level. -
Page 20: Dual-Tone Detection
HOOK and EXTREF pins. When off-hook (HOOK pin voltage < EXTREF pin voltage) is detected, the #RDET pin outputs 0. RING HOOK – #RDET Amp( ) EXTREF MODE1 = 1 RING Figure 3.7.1 Off-hook detection circuit EPSON E0C5251 TECHNICAL MANUAL... -
Page 21: Precautions On Mounting
V terminals with patterns as short and large as possible. (2) When connecting between the V and V terminals with a bypass capacitor, the terminals should be connected as short as possible. Bypass capacitor connection example EPSON E0C5251 TECHNICAL MANUAL... - Page 22 (1) Design the product and implement the IC on the board so that it is shielded from visible radiation in actual use. (2) The inspection process of the product needs an environment that shields the IC from visible radiation. (3) As well as the face of the IC, shield the back and side too. EPSON E0C5251 TECHNICAL MANUAL...
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Page 23: Electrical Characteristics
=2.7V to 5.5V, V =0V, f =3.579545MHz, Ta=-20 to 70°C Parameter Symbol Condition Min. Typ. Max. Unit µA Current consumption I Zero-power mode (PDWN=High) µA FSK energy detection mode (PDWN=High) Power up mode (no signal inputs) EPSON E0C5251 TECHNICAL MANUAL... -
Page 24: Crystal Oscillation Characteristics
Data end → #DET rise msec CDOFF PDWN rise → Oscillation start msec DOCH msec 1st RING 2nd RING Input 101010... DATA #RDRC #RDET PDWN SUPD #DET CDON CDOFF 101010... DATA DOCH OSC4 Figure 5.6.1 FSK switching characteristics EPSON E0C5251 TECHNICAL MANUAL... -
Page 25: Fsk Energy Detection Mode Ac Characteristics
=3.579545MHz, Ta=-20 to 70°C, C =50pF Parameter Symbol Condition Min. Typ. Max. Unit FSK energy detect capture time msec EGAQ FSK end → #IRQ rise msec EGIH #IRQ EGAQ EGIH Figure 5.6.2 FSK energy detection mode switching characteristics EPSON E0C5251 TECHNICAL MANUAL... -
Page 26: Dual-Tone (Cas) Detection Circuit Characteristics
CAS end → #DET rise 2.8×(31-N)+13.1 msec CASDH CAS width msec CASW N = TH0 × 16 + TL3 × 8 + TL2 × 4 + TL1 × 2 + TL0 CASW #DET CASAQ CASDH Figure 5.7.1 CAS switching characteristics EPSON E0C5251 TECHNICAL MANUAL... -
Page 27: Call Progress Mode (Cpm) Detection Circuit Characteristics
=0V, f =3.579545MHz, Ta=-20 to 70°C, C =50pF Parameter Symbol Min. Typ. Max. Unit CPM tone-detect capture time msec CPMAQ CPM tone end → #IRQ rise msec CPMIH #IRQ CPMAQ CPMIH #DET Figure 5.8.1 CPM switching characteristics EPSON E0C5251 TECHNICAL MANUAL... -
Page 28: Serial Interface Circuit Characteristics
MODE0 Low setup time µsec MODE0 Low hold time µsec MODE0 Low pulse width SSDI HSDI #SCLK SCLK MODE0 WSCLK WSCLK Figure 5.9.1 Serial interface input timing DSDO DSDO #SCLK MODE0 Figure 5.9.2 Serial interface output timing EPSON E0C5251 TECHNICAL MANUAL... -
Page 29: Fsk Demodulated Data Read Mode
The subsequent four bits are the data bits D[3:0] to be written to the specified register. The data is input beginning with the LSB. First data Second data n’th data #SCLK Low level FSK/read mode MODE0 CAS/write mode Figure 5.9.5 Data write timing EPSON E0C5251 TECHNICAL MANUAL... -
Page 30: E0C5251 Timing Chart
5 ELECTRICAL CHARACTERISTICS 5.10 E0C5251 Timing Chart 5.10.1 Bellcore On-Hook Data Transfer INP/INN 1st RING data transfer 2nd RING #RDRC #IRQ Power-down due to timeout Power-down PDWN after receiving last data MODE0 FSK/read mode Ring detection Ring detection #DET Carrier detection... -
Page 31: Bt Idle State Cli Service
FSK mode must be set to prevent failure in carrier detection after sending ACK #DET CAS tone detection Carrier detection Control data bits written Receive data Serial clock Serial clock #SCLK OSC4 Figure 5.10.4 BT Loop State CLI service timing chart EPSON E0C5251 TECHNICAL MANUAL... -
Page 32: External Wiring Diagram (Example)
Figure 5.11.1 Example of Bellcore-compatible telephone circuit Note: The above circuit diagram is merely an example, and does not guarantee the operation of the circuit. ∗ See Section 3.3, "Input Amp Circuit", for the R to R values. EPSON E0C5251 TECHNICAL MANUAL... -
Page 33: Example Of Bellcore-Compatible Auxiliary Circuit
Figure 5.11.2 Example of Bellcore-compatible auxiliary circuit Note: The above circuit diagram is merely an example, and does not guarantee the operation of the circuit. ∗ See Section 3.3, "Input Amp Circuit", for the R to R values. EPSON E0C5251 TECHNICAL MANUAL... -
Page 34: Package
±0.05 +0.001 0.006 –0.002 ±0.3 ±0.1 1.27 +0.012 +0.003 0.039 –0.011 0.05 0.016 –0.004 0.067 DIP-28pin Ceramic Package Unit: mm (inch) 37.4 1.472 ±0.1 36.7 +0.003 1.445 –0.004 0.059 ±0.1 0.46 2.54 15.24 0° 0.018 15° EPSON E0C5251 TECHNICAL MANUAL... -
Page 35: Pad Layout
879.9 -1116.4 CASFB -879.8 850.5 MODE1 879.9 -823.8 -879.8 735.0 #PQUAL 879.9 -365.3 EXTREF -879.8 406.4 #DET 879.9 -74.7 HOOK -879.8 290.9 #IRQ 879.9 420.8 RDIN -879.8 -37.8 #SCLK 879.9 536.3 #RDRC -879.8 -328.4 879.9 976.1 EPSON E0C5251 TECHNICAL MANUAL... - Page 36 80992 Munich, GERMANY Phone: +65-337-7911 Fax: +65-334-2716 Phone: +49-(0)89-14005-0 Fax: +49-(0)89-14005-110 - KOREA - - GERMANY - SEIKO EPSON CORPORATION KOREA OFFICE SALES OFFICE 50F, KLI 63 Bldg., 60 Yoido-dong Altstadtstrasse 176 Youngdeungpo-Ku, Seoul, 150-763, KOREA 51379 Leverkusen, GERMANY Phone: 02-784-6027...
- Page 37 In pursuit of “Saving” Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers’ dreams. Epson IS energy savings.
- Page 38 ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ Issue JULY 2000, Printed in Japan...
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