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SBE wanPTMC-256T3 Hardware Technical Reference

High-performance ptmc communications controller
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wanPTMC-256T3
High-Performance PTMC Communications Controller
Hardware Technical Reference, Rev. 0.A, August 5, 2002
Primary Text Number
SBE, Inc.
SBE, Inc.
SBE, Inc.
SBE, Inc.
2305 Camino Ramon #200, San Ramon, California 94583
(925) 355-2000
Fax: (925) 355-2020
Website: http://www.sbei.com
M8258
Technical Support (800) 444-0990
FaxBack Service: (800) 214-4723

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Summary of Contents for SBE wanPTMC-256T3

  • Page 1 High-Performance PTMC Communications Controller Hardware Technical Reference, Rev. 0.A, August 5, 2002 Primary Text Number M8258 SBE, Inc. SBE, Inc. SBE, Inc. SBE, Inc. 2305 Camino Ramon #200, San Ramon, California 94583 (925) 355-2000 Technical Support (800) 444-0990 Fax: (925) 355-2020 FaxBack Service: (800) 214-4723 Website: http://www.sbei.com...
  • Page 2 SBE, Inc., except that the purchaser may copy necessary portions for internal use only. While every effort has been made to ensure the accuracy of this manual, SBE cannot be held responsible for damage resulting from information herein. All specifications are subject to change without notice.

  • Page 3: Table Of Contents

    2-1. Product Description and Functional Characteristics ............... 11 2-2. Unpacking Instructions ........................12 2-3. Handling Procedures .......................... 12 2-4. Installation ............................13 Installing the wanPTMC-256T3 onto a host board ............... 13 2-5. Returns/Service ..........................14 3. Specifications ............................15 3-1. Devices ............................... 16 Conexant CN8478 communications controller ................
  • Page 4 8. Appendix: Design Considerations for DS3 Application .................55 8-1. Use of Receive Equalizer ........................55 8-2. Line Build-Out Criteria ........................56 8-3. Use of LOSTHR ........................... 56 9. Appendix: RTM Design Guidelines ......................57 Contents wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002...
  • Page 5 4-1 Serial port mapping (PORTMAP=2)......................23 4-2 TEMUX block diagram ..........................25 4-3 Rear I/O support ............................26 6-1 wanPTMC-256T3 TDM data path structure ................... 33 6-2 wanPTMC-256T3 clocking structure....................... 34 6-3 Clock and frame phase relationship....................... 35 6-4 wanPTMC-256T3 interrupt structure...................... 37 7-1 Data timing between LIU and TEMUX .....................
  • Page 6 7-12 LRXR: PCI offset address D0010 ......................52 7-13 LED01: PCI offset address D0014 ......................53 7-14 LED23: PCI offset address D0018 ......................53 7-15 GPR: PCI offset address D000C......................54 9-1 PTMC Pn4 connector pin assignments....................60 Contents wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002...

  • Page 7: About This Manual

    1. About This Manual This manual is the technical reference for the wanPTMC-256T3 HDLC/SS7 communications module. This manual is intended for hardware and software engineers who are incorporating the wanPTMC-256T3 into a system. The wanPTMC-256T3 Technical Reference includes the following: •...

  • Page 8: Documentation Conventions

    Points out possible ways the product can be damaged if proper precautions are not followed. Warning! States potential dangers to the user if a procedure is not properly followed. Note: Provides information that is important to the surrounding text. About This Manual wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002...

  • Page 9: Related Documents

    1-2. Related Documents The following references can be used for background or additional information about this product. References are for informational purposes only and do not express or imply wanPTMC-256T3 product features and functions. • Conexant CN8478/4A/2A/1A Product Manual, document # 100660E.
  • Page 10 About This Manual wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002...

  • Page 11: Introduction

    HW400c/M. It combines a fully channelized DS3 interface (down to DS0s), a 256 channel “layer one” protocol processor, and a full matrix DS0 level switch in a single PTMC slot. The wanPTMC-256T3 supports DS3, DS2, and DS1 level framing including C-bit, CAS, and CCS signaling channels. Protocol processing capabilities include HDLC and SS7 MTP1 support.

  • Page 12: Unpacking Instructions

    SBE, Inc. to obtain a Return Materials Authorization (RMA) number and further shipping instructions. 2-3. Handling Procedures The wanPTMC-256T3 adapter uses CMOS components that can be easily damaged by static electrical discharge. To avoid damage, familiarize yourself with electrostatic discharge (ESD) procedures, which include the following...

  • Page 13: Installation

    Be sure to follow safe ESD procedures when handling electronic hardware. 1. Remove the wanPTMC-256T3 from the protective bag. 2. Press the wanPTMC-256T3 bezel into the cutout in the PTMC carrier I/O panel. The gasket around the wanPTMC-256T3 bezel makes a tight fit to ensure an electromagnetic seal.

  • Page 14: Returns/Service

    TEL: +925-355-2000 (Outside of USA) FAX: +925-355-2020 Ship all returns to SBE’s USA service center: SBE, Inc. 2305 Camino Ramon, Suite 200 San Ramon, CA 94583 SBE’s customer service department can be reached at 800-444-0990. Introduction wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002...

  • Page 15: Specifications

    3. Specifications This chapter details the physical characteristics and specifications for the wanPTMC-256T3 communications controller. Figure 3-1 is a block diagram of the wanPTMC-256T3 functionality. Figure 3-1 wanPTMC-256T3 functional block diagram Tx bi-color magnetics rear I/O support XRT7300 LIU cPLD...

  • Page 16: Devices

    DS0 time slots to support ISDN hyperchannels (Nx64Kbps) or as any number of bits in a DS0 for subchanneling applications (Nx8Kbps). Framer The wanPTMC-256T3 uses a PMC-Sierra TEMUX (PM8315) as the Framer. It has the following characteristics: • Integrates a DS3 framer, an M13 multiplexer, and 28 T1 (or 21 E1 framers) into a 324-ball PBGA package.

  • Page 17: Operating Requirements

    3-3. Operating Requirements The wanPTMC-256T3 is designed to function within these environmental parameters: Storage temperature: −40 to 85 °C (−40 to 176 °F) Operating temperature: −5 to 55 °C (23 to 136 °F) ambient temperature with power applied Relative humidity: 10% to 85% noncondensing Storage humidity: 5% to 95% noncondensing Power requirements: 7.5 watts maximum...

  • Page 18: Physical Characteristics

    3-4. Physical Characteristics Figure 3-2 shows the physical profile of the wanPTMC-256T3 adapter. Table 3-1 lists the dimensions. Figure 3-2 wanPTMC-256T3 physical profile PMC-Pn3 PMC-Pn4 Agere T8110 TEMUX MUSYCC CN8478A Altera Max PMC-Pn1 PMC-Pn2 Table 3-1 wanPTMC-256T3 dimensions Depth: 5.866 inches Width: 2.913 inches...

  • Page 19: Ptmc Bezel

    Keying The wanPTMC-256T3 can be operated in a 5V or 3.3V signaling environment. The signaling environment is determined by the voltage on the PCI VIO pins and is host-specific.

  • Page 20: Industry Standards Compliance

    3-6. Industry Standards Compliance The wanPTMC-256T3 complies with the following industry standard specifications: • PCI Local Bus Specification Revision 2.1. 3-7. Agency Compliance The wanPTMC-256T3 is designed to comply with the following standards or requirements: • BABT • NEBS • VCCI 3-8.

  • Page 21: Functional Interfaces

    4. Functional Interfaces 4-1. PCI Bus Interface The wanPTMC-256T3 interfaces to the host system using a 32bit/33MHz PCI 2.1-compliant bus controller built into the Conexant CN8478 (MUSYCC). The CN8478 is packaged in a 208 pin PBGA package and requires 3.3V for its I/O and 2.5V for its core.

  • Page 22: Busmode Pins

    BUSMODE pins Since the wanPTMC-256T3 supports only the bus protocol at the PTMC connectors, the BUSMODE1# pin is asserted LOW for only two reasons: to indicate the board’s presence to the host and to indicate that it is capable of performing PCI protocol (see Table 4-1).

  • Page 23: Hdlc/Ss7 Packet Processor

    Each port operates at 8.192Mbps (i.e., 4xE1 rate). Frame synchronization pulses occur at 8KHz and are generated using Frame Group outputs of T8110. See Section 6-2 for more information on clock timing requirements and phase relations. wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 HDLC/SS7 Packet Processor...

  • Page 24: Line Interface Unit

    CPLD. See LIU Transmit Control Register (LTXR) on page 51 and LIU Receive Control Register (LRXR) on page 52. B3ZS encoding and decoding is disabled in the LIU on wanPTMC-256T3. This feature is provided in the TEMUX. The LIU provides three interrupts: •...

  • Page 25: Ds3 Framer And Multiplexer

    DS3 port, the CT-Bus, and the Packet Processor. The T8110 is a 272-ball PBGA package and requires 3.3V for its operation. The T8110’s microprocessor interface is configured for 16-bit operation. wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 DS3 Framer and Multiplexer...

  • Page 26: Rear I/O Support

    The T3 TIP and RING signals as well as the LED signals are routed to the Pn4 connector using the SBE standard pairing for differential signals to support rear I/O. Quick Switch Bus FET Multiplexer (QS3VH257) is used to switch the T3 signals between front I/O and rear I/O.

  • Page 27: Connectors

    +3.3V DEVSEL# Ground STOP# Ground LOCK# PERR# Ground PCI-RSDV* PCI-RSVD* +3.3V SERR# Ground C/BE[1]# Ground V (I/O) AD[15] AD[14] AD[13] AD[12] AD[11] M66EN AD[10] AD[09] AD[08] +3.3V Ground C/BE[0]# AD[07] PMC-RSVD wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 Connectors...
  • Page 28 Signal name Signal name Pin # AD[06] AD[05] +3.3V PMC-RSVD AD[04] Ground PMC-RSVD Ground V (I/O) AD[03] PMC-RSVD PMC-RSVD AD[02] AD[01] Ground PMC-RSVD AD[00] ACK64# +3.3V Ground REQ64# Ground PMC-RSVD Functional Interfaces wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002...

  • Page 29: Pn4 User I/O Connector

    The default is front with rear I/O signals tri-stated. Table 4-3 Pn4 user I/O pin assignments Pin # Signal name Signal name Pin # TRING TTIP RRING RTIP /LED_AY /LED_AG /LED_BY /LED_BG /LED_CY /LED_CG /LED_DY /LED_DG wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 Connectors...

  • Page 30: Pn3 Ptmc Connector

    (N/C) CT_C8A CT_D19 CT_D18 CT_D17 CT_D16 NETREF2 CT_D14 (N/C) CT_D12 PTENB# (N/C) PTGNDZ3 NETREF1 CT_C8B CT_D15 CT_D10 CT_D13 CT_D8 CT_D11 CT_D9 CT_D6 CT_D7 CT_D4 PTID1 CT_D5 CT_D2 CT_D3 CT_D0 CT_D1 Functional Interfaces wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002...

  • Page 31: Power-Up, Reset, And Initialization

    • Power-up reset (DS1817) output is asserted. • 2.5V is bad (under voltage condition). Note that when the wanPTMC-256T3 is in reset it will not be accessible by the host. A yellow LED (CR3) indicates the reset state of the board. This is a useful troubleshooting indicator.

  • Page 32: Musycc Initialization

    0x600) must be set as shown in Table 5-2. Table 5-2 Global configuration descriptor settings for EBUS access Bit Field Name Value 14:12 BLAPSE[2:0] ECKEN MPUSEL ALAPSE[1:0] ELAPSE[2:0] Power-Up, Reset, and Initialization wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002...

  • Page 33: Architecture

    CT bus 7x H-MVIP CAS data Lucent 12 I/O TEMUX T8110 2 I/O 1x H-MVIP CCS data 2 I/O 2 I/O port #0 port #0 Conexant CN8478 PCI bus wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 Data Path Architecture...

  • Page 34: Clocking And Data Timing

    6-2. Clocking and Data Timing Figure 6-2 shows the clocking structure on the wanPTMC-256T3. The T8110 is the source for most of the clocks. Figure 6-2 wanPTMC-256T3 clocking structure T1/E1 recovered clk 1 T1/E1 recovered clk 2 netref 1 PMC-Sierra...
  • Page 35 T1 data may generated by an external source, the T8110 must utilize the recovered clock (RECVCLK1/RECVCLK2) from the TEMUX and synchronize all TDM highways to it. This implies that the wanPTMC-256T3 must become the CT Bus clock master.

  • Page 36: Interrupts

    6-3. Interrupts The wanPTMC-256T3 utilizes INTA# and INTB# interrupts. Both interrupts are controlled by CN8478. Assertion of INTA# indicates that the layer 2 (HDLC) portion requires service. Assertion of INTB# indicates that one of the other devices on the board is in need of service.
  • Page 37 Figure 6-4 wanPTMC-256T3 interrupt structure Interrupt EnableRegister Interrupt Pending Register IPR (read-write) IER (read-only) L_RLOS L_RLOS MUSYCC L_RLOL L_RLOL INTA# L_NTO L_NTO Combined Interrupts EBUS_INT TEMUX INTB# TEMUX DTACK DTACK SYSERR SYSERR CLKERR CLKERR wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 Interrupts...

  • Page 38: Dtack Interrupt

    EBUS cycle. If the data transfer is not completed, an interrupt is generated. This provides the host an opportunity to retry the read. A 1 must be written to bit 5 of the ISR to clear the DTACK interrupt. Architecture wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002...

  • Page 39: Programming Information

    7. Programming Information 7-1. Memory Map Table 7-1 shows the memory map for the wanPTMC-256T3. Note that the PCI address is EBUS address multiplied by four because all accesses to EBUS are on D-Word boundaries. Table 7-1 wanPTMC-256T3 memory map...

  • Page 40: Serial Eeprom

    HIGH-Z Erase/Write Enable HIGH-Z Erase/Write Read D7-D0 Write D7-D0 RDY_/BSY Write All D7-D0 RDY_/BSY Note that each bit in Table 7-2 represents one PCI write or read cycle, as appropriate. Programming Information wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002...
  • Page 41 Table 7-3 and Table 7-4 are examples of a write and read from the EEPROM. To write data value 0xAA to EEPROM memory location 0x55, the following sequence of PCI accesses must be performed. All accesses are to PCI address offset 0xC0000. wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 Serial EEPROM...
  • Page 42 Data In (D4) Write “00000101”B (0x05) Data In (D3) Write “00000100”B (0x04) Data In (D2) Write “00000101”B (0x05) Data In (D1) Write “00000100”B (0x04) Data In (D0) Write “00000000”B (0x00) Programming Information wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002...
  • Page 43 500ns delay between successive EBUS accesses when accessing the EEPROM. The process of completing an instruction by writing 0x00 to the EEPROM at the end of the cycle insures that the minimum time between successive accesses is satisfied. wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 Serial EEPROM...

  • Page 44: Ds3 Framer And Multiplexer

    (bit 5 of IPR is set), or utilize the DTACK interrupt to address the situation. In either case, the state of DTACK bit must be cleared after it has been used. Programming Information wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002...
  • Page 45 0x00A00 – 0x00BFC Interrupt control 0x00C00 – 0x00DFC Reserved 0x00E00 – 0x1FFFC Virtual channel memory 0x20000 – 0x3FFFC Data memory 0x40000 – 0x5FFFC Reserved 0x60000 – 0x7FFFC Connection memory 0x80000 – 0x9FFFC wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 T8110 Programming...
  • Page 46 Master output 0x444 C8 output rate /FR_COMP width enables 0x448 Reserved CCLK output enables 0x44C SCLK output rate TCLK select 0x450 L_SC1 select L_SC0 select 0x454 L_SC3 select L_SC2 select Programming Information wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002...
  • Page 47 In-service, byte 0 0xDFC In-service byte 3 In-service byte 2 See Section 6-1, Data Path Architecture, and Section 6-2, Clocking and Data Timing, for information on connection of TDM highways and clocks. wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 T8110 Programming...

  • Page 48: Cpld

    0 should be written to them. At power-up all reserved bits are cleared (initialized to 0). Programming Information wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002...

  • Page 49: Board Id Register (Bid)

    Board ID Register (BID) The Board ID Register (BID) is a read-only register that provides a unique value for the wanPTMC-256T3 board to distinguish it from other boards. Use of this register is optional, as there may be other ways to distinguish between different boards.

  • Page 50: Interrupt Pending Register (Ipr)

    TEMUX Interrupt L_NTO LIU No Transmitter Output Interrupt L_RLOL LIU Receiver Loss of Lock Interrupt L_RLOS LIU Receiver Loss of Signal Interrupt See Section 6-3, Interrupts, for additional details on interrupts. Programming Information wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002...

  • Page 51: Liu Transmit Control Register (Ltxr)

    Turn off Transmitter Transmitter ON Transmitter OFF TAOS Transmit All Ones Normal Operation Transmit All Ones Signal LBODIS Disable Line Build-out Line Build-out Enabled (short cable) Line Build-out Disabled (long cable) wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 CPLD...

  • Page 52: Liu Receive Control Register (Lrxr)

    Remote Loop-back REQEN Enable Receive Equalizer Receive Equalizer Disabled Receive Equalizer Enabled (long cable) See Chapter 8, Appendix: Design Considerations for DS3 Application, for more information on LOSTHR and REQEN. Programming Information wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002...

  • Page 53: Led Registers

    Blink LED n if only one LED is ON; Alternate Y and G if both LEDs are RATEn Blink Rate for LED n (no effect if BLNKn = 0) Slow (one cycle per second) Fast (two cycles per second) wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002 CPLD...

  • Page 54: General Purpose Register (Gpr)

    PTENB not asserted Host does not support PTMC modules; do not enable CT Bus highways on T8110. PTENB asserted Host supports PTMC modules; okay to enable CT Bus highways on T8110. Programming Information wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002...

  • Page 55: Appendix: Design Considerations For Ds3 Application

    Based on the above reasoning, the Receive Equalizer is turned on (REQEN bit is set) after power-up/reset on the wanPTMC-256T3. If a short loopback is used the Receive Equalizer should be turned off. Figure 8-1 Typical DS3 application...

  • Page 56: Line Build-Out Criteria

    8-3. Use of LOSTHR At power-up/reset the wanPTMC-256T3’s analog loss of signal threshold is set to the higher value (i.e., the LOSTHR bit (bit 4) of LRXR is cleared). This indicates a LOS condition before the signal falls so low that it may cause data errors.

  • Page 57: Appendix: Rtm Design Guidelines

    When rear I/O is used, the rear transition module (RTM) must provide the magnetics. Due to the frequencies and signal amplitudes involved, great care must be taken in how the signals are routed on the wanPTMC-256T3, the carrier, and the RTM. Figure 9-1 and Figure 9-2 show the general requirements.
  • Page 58 However, the return loss on the receive side is important. The 100 ohm line between the transformer on the RTM and the multiplexer on the wanPTMC-256T3 can be made to appear as 75 ohm by carefully adjusting the terminations. A 100 ohm resistor at the input of multiplexer and approximately 350-450 ohm on the RTM at the transformer input (line side) achieves this.
  • Page 59 Figure 9-3 Routing from the CM choke to BNC plane void Table 9-1 shows the Pn4 connections on wanPTMC-256T3. SBE has defined pin assignment for eight differential pairs on Pn4. These are routed as 100 ohm differential pairs on the HW400c/M between Jn4 and J5. The first four pairs can be used for high-speed (HS) signals, such as T3/E3, or for low-speed (LS) signals, such as T1/E1.
  • Page 60 TIP5(LS) RING5(LS) LED3 /LED_BY /LED_BG LED4 LED5 /LED_CY /LED_CG LED6 LED7 /LED_DY TIP6(LS) RING6(LS) /LED_DG LED8 RING7(LS) TIP7(LS) LED9 LED10 LED11 LED12 LED13 LED14 LED15 LED16 RING8(LS) TIP8(LS) Appendix: RTM Design Guidelines wanPTMC-256T3 Technical Reference - 0.A, August 5, 2002...

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