SiFive FE310-G003 Manual
  1. Manuals
  2. Brands
  3. SiFive Manuals
  4. Network Hardware
  5. FE310-G003
  6. Manual

SiFive FE310-G003 Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

SiFive FE310-G003 Manual
v1p1
© SiFive, Inc.

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the FE310-G003 and is the answer not in the manual?

Questions and answers

Summary of Contents for SiFive FE310-G003

  • Page 1 SiFive FE310-G003 Manual v1p1 © SiFive, Inc.
  • Page 2 SiFive does not assume any liability rising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation indirect, incidental, spe- cial, exemplary, or consequential damages.

  • Page 3: Table Of Contents

    Contents Introduction ......................8 ....................8 FE310-G003 Overview ..................... 10 E31 RISC‑V Core ......................... 10 Interrupts ................... 10 On-Chip Memory System .................... 11 Always-On (AON) Block ......................11 GPIO Complex .............11 Universal Asynchronous Receiver/Transmitter ..............11 Hardware Serial Peripheral Interface (SPI) .....................
  • Page 4 Machine Status Register (mstatus) ................38 8.3.2 Machine Trap Vector (mtvec) .................40 8.3.3 Machine Interrupt Enable (mie) ...............40 8.3.4 Machine Interrupt Pending (mip) ................. 41 8.3.5 Machine Cause (mcause) ..................... 42 Interrupt Priorities ....................... 42 Interrupt Latency FE310-G003 Manual © SiFive, Inc. Page 2...
  • Page 5 12.3 AON Reset Unit ................... 58 12.4 Power-On Reset Circuit ....................59 12.5 External Reset Circuit ......................59 12.6 Reset Cause ................... 59 12.7 Watchdog Timer (WDT) .................... 59 12.8 Real-Time Clock (RTC) FE310-G003 Manual © SiFive, Inc. Page 3...
  • Page 6 RTC Configuration Register (rtccfg) ................74 15.3 RTC Compare Register (rtccmp) General Purpose Input/Output Controller (GPIO) ......75 ................. 77 16.1 GPIO Instance in FE310-G003 ......................77 16.2 Memory Map ....................78 16.3 Input / Output Values FE310-G003 Manual © SiFive, Inc.
  • Page 7 16.8 HW I/O Functions (IOF) Universal Asynchronous Receiver/Transmitter (UART) ....81 ...................... 81 17.1 UART Overview ................81 17.2 UART Instances in FE310-G003 ......................82 17.3 Memory Map ................82 17.4 Transmit Data Register (txdata) ................83 17.5 Receive Data Register (rxdata) .................83...
  • Page 8 18.17 SPI Flash Instruction Format Register (ffmt) Pulse Width Modulator (PWM) ..............99 ....................... 99 19.1 PWM Overview ................100 19.2 PWM Instances in FE310-G003 ....................100 19.3 PWM Memory Map ................101 19.4 PWM Count Register (pwmcount) ..............102 19.5 PWM Configuration Register (pwmcfg) ...............103...
  • Page 9 21.4 Debug Interface ................117 21.4.1 JTAG TAPC State Machine ................... 117 21.4.2 Resetting JTAG Logic ..................... 118 21.4.3 JTAG Clocking ................118 21.4.4 JTAG Standard Instructions ................118 21.4.5 JTAG Debug Commands References ......................119 FE310-G003 Manual © SiFive, Inc. Page 7...

  • Page 10: Introduction

    Chapter 1 Introduction The FE310-G003 is the third revision of the General Purpose Freedom E300 family with addi- tional DTIM memory. The FE310-G003 is built around the E31 Core Complex instantiated in the Freedom E300 plat- form and fabricated in the TSMC CL018G 180nm process. This manual serves as an architec- tural reference and integration guide for the FE310-G003.
  • Page 11 Chapter 1 Introduction Figure 1: FE310-G003 top-level block diagram. Table 1: FE310-G003 Feature Summary. Available in Feature Description QFN48 1× E31 RISC‑V cores with machine and user mode, RISC-V Core 16 KiB 2-way L1 I-cache, and 64 KiB data tightly inte- ✔...

  • Page 12: E31 Risc-V Core

    1.3 Interrupts The FE310-G003 includes a RISC-V standard platform-level interrupt controller (PLIC), which supports 52 global interrupts with 7 priority levels. The FE310-G003 also provides the standard RISC‑V machine-mode timer and software interrupts via the Core-Local Interruptor (CLINT). Interrupts are described in Chapter 8. The CLINT is described in Chapter 9. The PLIC is described in Chapter 10.

  • Page 13: Always-On (Aon) Block

    1.8 Hardware Serial Peripheral Interface (SPI) There are 3 serial peripheral interface (SPI) controllers. Each controller provides a means for serial communication between the FE310-G003 and off-chip devices, like quad-SPI Flash mem- ory. Each controller supports master-only operation over single-lane, dual-lane, and quad-lane protocols.

  • Page 14: I²C

    Chapter 1 Introduction 1.10 I²C The FE310-G003 has an I²C controller to communicate with external I²C devices, such as sen- sors, ADCs, etc. The I²C is described in detail in Chapter 20. 1.11 Debug Support The FE310-G003 provides external debugger support over an industry-standard JTAG port, including 8 hardware-programmable breakpoints per hart.

  • Page 15: List Of Abbreviations And Terms

    Joint Test Action Group JTAG Loosely Integrated Memory. Used to describe memory space delivered in a SiFive Core Complex but not tightly integrated to a CPU core. Physical Memory Protection Platform-Level Interrupt Controller. The global interrupt controller in a PLIC RISC-V system.
  • Page 16 Writes-Preserve Reads-Ignore field. A register field that might contain WPRI unknown information. Reads should ignore the value returned, but writes to the whole register should preserve the original value. FE310-G003 Manual © SiFive, Inc. Page 14...

  • Page 17: E31 Risc-V Core

    Chapter 3 E31 RISC-V Core This chapter describes the 32-bit E31 RISC‑V processor core used in the FE310-G003. The E31 processor core comprises an instruction memory system, an instruction fetch unit, an exe- cution pipeline, a data memory system, and support for global, software, and timer interrupts.

  • Page 18: I-Cache Reconfigurability

    Chapter 3 E31 RISC-V Core FE310-G003 Memory Map in Chapter 4 for a description of executable address regions that are denoted by the attribute X. Trying to execute an instruction from a non-executable address results in a synchronous trap. 3.1.1...

  • Page 19: Data Memory System

    DTIM and other uncached memory regions. See The RISC‑V Instruction Set Manual, Volume I: User-Level ISA, Version 2.1 for more infor- mation on the instructions added by this extension. FE310-G003 Manual © SiFive, Inc. Page 17...

  • Page 20: Supported Modes

    In addition to locking the PMP entry, the bit indicates whether the R/W/X permissions are enforced on M-Mode accesses. When the bit is clear, the R/W/X permissions apply only to U- mode. FE310-G003 Manual © SiFive, Inc. Page 18...

  • Page 21: Hardware Performance Monitor

    Chapter 3 E31 RISC-V Core 3.8 Hardware Performance Monitor The FE310-G003 supports a basic hardware performance monitoring facility compliant with The RISC‑V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10. The mcycle CSR holds a count of the number of clock cycles the hart has executed since some arbitrary time in the past.
  • Page 22 Branch direction misprediction Branch/jump target misprediction Pipeline flush from CSR write Pipeline flush from other event Integer multiplication interlock Memory System Events, [7:0] = 2 mhpeventX Bits Meaning Instruction cache miss Memory-mapped I/O access FE310-G003 Manual © SiFive, Inc. Page 20...

  • Page 23: Memory Map

    Chapter 4 Memory Map The memory map of the FE310-G003 is shown in Table 4. Table 4: FE310-G003 Memory Map. Memory Attributes: R - Read, W - Write, X - Execute, C - Cacheable, A - Atomics Base Attr. Description...
  • Page 24 Chapter 4 Memory Map Table 4: FE310-G003 Memory Map. Memory Attributes: R - Read, W - Write, X - Execute, C - Cacheable, A - Atomics Base Attr. Description Notes Reserved 0x1000_9000 0x1000_FFFF OTP Control 0x1001_0000 0x1001_0FFF Reserved 0x1001_1000 0x1001_1FFF...

  • Page 25: Boot Process

    Chapter 5 Boot Process The FE310-G003 supports booting from several sources, which are controlled using the Mode Select ( ) pins on the chip. All possible values are enumerated in Table 5. MSEL[1:0] Table 5: Boot media based on pins...

  • Page 26: One-Time Programmable (Otp) Memory

    SPI flash (e.g., just using on-chip OTP). Off-chip SPI devices can vary in number of supported I/O bits (1, 2, or 4). SPI flash bits contain all 1s prior to programming. FE310-G003 Manual © SiFive, Inc. Page 24...

  • Page 27: Clock Generation

    AON block (Chapter 12) or the PRCI block (Section 6.2). 6.1 Clock Generation Overview Figure 2: FE310-G003 clock generation scheme Figure 2 shows an overview of the FE310-G003 clock generation scheme. Most digital clocks on the chip are divided down from a central high-frequency clock produced from either hfclk the PLL or an on-chip trimmable oscillator.

  • Page 28: Prci Address Space Usage

    The AON block contains registers with similar functions, but only for the AON block units. Table 8 shows the memory map for the PRCI on the FE310-G003. Table 8: SiFive PRCI memory map, offsets relative to PRCI base address.
  • Page 29 HFROSC. HFROSC can be explicitly renabled by setting . HFROSC will be hfroscen automatically re-enabled at every reset. The status bit indicates if the oscillator is operational and ready for use as a clock hfroscrdy source. FE310-G003 Manual © SiFive, Inc. Page 27...

  • Page 30: External 16 Mhz Crystal Oscillator (Hfxosc)

    6–48 MHz. The PLL can generate output clock frequencies in the range 48–384 MHz. The PLL is controlled by a memory-mapped read-write register in the PRCI address pllcfg space. The format of is shown in Table 11. pllcfg FE310-G003 Manual © SiFive, Inc. Page 28...
  • Page 31 Figure 3: Controlling the FE310-G003 PLL output frequency. field encodes the reference clock divide ratio as a 2-bit binary value, where the pllr[1:0] value is one less than the divide ratio (i.e., =4).
  • Page 32 The supply filter should be a 100 Ω resistor in series with the board 1.8 V supply decoupled with a 100 nF capacitor across the VDDPLL/VSSPLL supply pins. The VSSPLL pin should not be connected to board VSS. FE310-G003 Manual © SiFive, Inc. Page 30...

  • Page 33: Pll Output Divider

    The LFROSC can be calibrated in software using a more accurate high-frequency clock source. Table 14: lfrosccfg: Ring Oscillator Configuration and Status lfrosccfg: Ring Oscillator Configuration and Status ( lfrosccfg 0x70 Register Offset Bits Field Name Attr. Rst. Description FE310-G003 Manual © SiFive, Inc. Page 31...

  • Page 34: Alternate Low-Frequency Clock (Lfaltclk)

    This mux selection can only be controlled by external pads, it is not psdlfaltclksel controllable by software. 6.9 Clock Summary Table 15 summarizes the major clocks on the FE310-G003 and their initial reset conditions. At external reset, the AON domain is clocked by either the LFROSC or , as...
  • Page 35 Chapter 6 Clock Generation Table 15: FE310-G003 Clock Sources 0.375 MHz 384 MHz hfclkrst JTAG TCK 0 MHz 16 MHz FE310-G003 Manual © SiFive, Inc. Page 33...

  • Page 36: Power Modes

    Chapter 7 Power Modes This chapter describes the different power modes available on the FE310-G003. The FE310-G003 supports three power modes: Run, Wait, and Sleep. 7.1 Run Mode Run mode corresponds to regular execution where the processor is running. Power consump- tion can be adjusted by varying the clock frequency of the processor and peripheral bus, and by enabling or disabling individual peripheral blocks.
  • Page 37 HFROSC at the default setting, and must reconfigure clocks to run from an alternate clock source (HFXOSC or PLL) or at a different setting on the HFROSC. Because the FE310-G003 has no internal power regulator, the PMU’s control of the power sup- plies is through chip outputs, .

  • Page 38: Interrupts

    Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10. 8.1 Interrupt Concepts The FE310-G003 supports Machine Mode interrupts. It also has support for the following types of RISC‑V interrupts: local and global. Local interrupts are signaled directly to an individual hart with a dedicated interrupt value. This...

  • Page 39: Interrupt Operation

    Chapter 8 Interrupts Figure 4: FE310-G003 Interrupt Architecture Block Diagram. 8.2 Interrupt Operation If the global interrupt-enable is clear, then no interrupts will be taken. If mstatus.MIE is set, then pending-enabled interrupts at a higher interrupt level will preempt cur- mstatus.MIE...

  • Page 40: Interrupt Control Status Registers

    A summary of the fields related to interrupts in mstatus the FE310-G003 is provided in Table 16. Note that this is not a complete description of mstatus as it contains fields unrelated to interrupts. For the full description of...
  • Page 41 See Table 17 for a description of the register. See Table 18 for a description of the mtvec field. See Table 22 for the FE310-G003 interrupt exception code values. mtvec.MODE Mode Direct When operating in direct mode all synchronous exceptions and asynchronous interrupts trap to address.

  • Page 42: Machine Interrupt Enable (Mie)

    Table 20. Table 20: Register Machine Interrupt Pending Register Bits Field Name Attr. Description [2:0] Reserved WIRI MSIP Machine Software Interrupt Pending [6:4] Reserved WIRI MTIP Machine Timer Interrupt Pending FE310-G003 Manual © SiFive, Inc. Page 40...

  • Page 43: Machine Cause (Mcause)

    1, if the trap was caused by an interrupt; 0 otherwise. Table 22: Exception Codes mcause Interrupt Exception Codes Interrupt Exception Code Description 0–2 Reserved Machine software interrupt 4–6 Reserved Machine timer interrupt FE310-G003 Manual © SiFive, Inc. Page 41...

  • Page 44: Interrupt Priorities

    • Machine timer interrupts 8.5 Interrupt Latency Interrupt latency for the FE310-G003 is 4 cycles, as counted by the numbers of cycles it takes from signaling of the interrupt to the hart to the first instruction fetch of the handler.
  • Page 45 . This means that the total latency, in cycles, for a global interrupt is: 4 + 3. coreClk This is a best case cycle count and assumes the handler is cached or located in ITIM. It does not take into account additional latency from a peripheral source. FE310-G003 Manual © SiFive, Inc. Page 43...

  • Page 46: Core-Local Interruptor (Clint)

    Chapter 9 Core-Local Interruptor (CLINT) The CLINT block holds memory-mapped control and status registers associated with software and timer interrupts. The FE310-G003 CLINT complies with The RISC‑V Instruction Set Manual, Volume II: Privileged Architecture, Version 1.10. 9.1 CLINT Memory Map Table 23 shows the memory map for CLINT on SiFive FE310-G003.

  • Page 47: Msip Registers

    The timer interrupt is reflected in the bit of the mtimecmp mtip register described in Chapter 8. On reset, is cleared to zero. The registers are not reset. mtime mtimecmp FE310-G003 Manual © SiFive, Inc. Page 45...

  • Page 48: Platform-Level Interrupt Controller (Plic)

    Architecture, Version 1.10 and supports 52 interrupt sources with 7 priority levels. 10.1 Memory Map The memory map for the FE310-G003 PLIC control registers is shown in Table 24. The PLIC memory map has been designed to only require naturally aligned 32-bit memory accesses.

  • Page 49: Interrupt Sources

    0x1000_0000 10.2 Interrupt Sources The FE310-G003 has 52 interrupt sources. These are driven by various on-chip devices as listed in Table 25. These signals are positive-level triggered. In the PLIC, as specified in The RISC‑V Instruction Set Manual, Volume II: Privileged Architec- ture, Version 1.10, Global Interrupt ID 0 is defined to mean "no interrupt."...

  • Page 50: Interrupt Priorities

    10.3 Interrupt Priorities Each PLIC interrupt source can be assigned a priority by writing to its 32-bit memory-mapped register. The FE310-G003 supports 7 levels of priority. A priority value of 0 is priority reserved to mean "never interrupt" and effectively disables the interrupt. Priority 1 is the lowest active priority, and priority 7 is the highest.

  • Page 51: Interrupt Enables

    Bit 0 of enable word 0 represents the non-existent interrupt ID 0 pending and is hardwired to 0. Only 32-bit word accesses are supported by the array in SiFive RV32 systems. enables FE310-G003 Manual © SiFive, Inc. Page 49...

  • Page 52: Priority Thresholds

    WARL field, where the FE310-G003 supports a maximum threshold of 7. threshold The FE310-G003 masks all PLIC interrupts of a priority less than or equal to . For threshold example, a value of zero permits all interrupts with non-zero priority, whereas a threshold value of 7 masks all interrupts.

  • Page 53: Interrupt Claim Process

    (Table 32), which returns the ID of the highest-priority pending interrupt or zero if there is no pending interrupt. A successful claim also atomically clears the corresponding pending bit on the interrupt source. A FE310-G003 hart can perform a claim at any time, even if the MEIP bit in its (Table 20) register is not set.

  • Page 54: Error Device

    The error device serves a dual role. Internally, it is used as a landing pad for illegal off-chip requests. However, it also useful for testing software handling of bus errors. FE310-G003 Manual © SiFive, Inc. Page 52...

  • Page 55: One-Time Programmable Memory (Otp) Peripheral

    Table 33: Register offsets within the OTP Controller memory map Offset Name Description Programmed-I/O lock register 0x00 otp_lock OTP device clock signals 0x04 otp_ck OTP device output-enable signal 0x08 otp_oe OTP device chip-select signal 0x0C otp_sel OTP device write-enable signal 0x10 otp_we FE310-G003 Manual © SiFive, Inc. Page 53...

  • Page 56: Programmed-I/O Lock Register (Otp_Lock)

    Listing 1: Sequence to acquire and release otp_lock la t0, otp_lock li t1, 1 loop: sw t1, (t0) lw t2, (t0) beqz t2, loop # Programmed I/O sequence goes here. sw x0, (t0) FE310-G003 Manual © SiFive, Inc. Page 54...

  • Page 57: Programmed-I/O Sequencing

    Table 34: otp_rsctrl: OTP read sequencer control otp_rsctrl: OTP read sequencer control ( otp_rsctrl 0x34 Register Offset Bits Field Name Attr. Rst. Description [2:0] OTP timescale scale Address setup time Read pulse time Read access time tacc [31:6] Reserved FE310-G003 Manual © SiFive, Inc. Page 55...

  • Page 58: Otp Programming Warnings

    7. SOAK any verification failures by repeating steps 2-5 using 400 us pulses. 8. REVERIFY the rewritten bits setting =0xF. Steps 7,8 may be repeated up to otp_mrr 10 times before failing the part. 9. UNLOCK the otp by writing 0x0 to otp_lock FE310-G003 Manual © SiFive, Inc. Page 56...

  • Page 59: Always-On (Aon) Domain

    Chapter 12 Always-On (AON) Domain The FE310-G003 supports an always-on (AON) domain that includes real-time counter, a watchdog timer, backup registers, low frequency clocking, and reset and power-management circuitry for the rest of the system. Figure 5 shows an overview of the AON block.

  • Page 60: Aon Power Source

    12.3 AON Reset Unit An AON reset is the widest reset on the FE310-G003, and resets all state except for the JTAG debug interface. An AON reset can be triggered by an on-chip power-on reset (POR) circuit when power is first...

  • Page 61: External Reset Circuit

    The Real-Time Clock is described in detail in Chapter 15. 12.9 Backup Registers The backup registers provide a place to store critical data during sleep. The FE310-G003 has 32 32-bit backup registers. 12.10 Power-Management Unit (PMU) The power-management unit (PMU) sequences the system power supplies and reset signals when transitioning into and out of sleep mode.
  • Page 62 Backup Register 7 0x09C backup_7 Backup Register 8 0x0A0 backup_8 Backup Register 9 0x0A4 backup_9 Backup Register 10 0x0A8 backup_10 Backup Register 11 0x0AC backup_11 Backup Register 12 0x0B0 backup_12 Backup Register 13 0x0B4 backup_13 FE310-G003 Manual © SiFive, Inc. Page 60...
  • Page 63 Sleep program instruction 7 0x13C pmusleepi7 PMU Interrupt Enables 0x140 pmuie PMU Wakeup Cause 0x144 pmucause Initiate PMU Sleep Sequence 0x148 pmusleep PMU Key. Reads as 1 when PMU is unlocked 0x14C pmukey FE310-G003 Manual © SiFive, Inc. Page 61...
  • Page 64 The WDT is based around a 31-bit counter held in . The counter can be read wdogcount[30:0] or written over the TileLink bus. Bit 31 of returns a zero when read. wdogcount FE310-G003 Manual © SiFive, Inc. Page 62...
  • Page 65 The wdogenalways bit, if set, means the watchdog counter increments if the processor core is wdogencoreawake not asleep. The WDT uses the signal from the wakeup sequencer to know when the corerst FE310-G003 Manual © SiFive, Inc. Page 63...
  • Page 66 To prevent spurious reset of the WDT, all writes to wdogkey must be preceded by an wdogcfg wdogfeed wdogcount wdogcount wdogcmp wdogip0 unlock operation to the register location, which sets . The value wdogkey wdogkey 0x51F15E FE310-G003 Manual © SiFive, Inc. Page 64...
  • Page 67 The register resides in the register, and can be read wdogip wdogcfg and written over TileLink to clear down the interrupt. FE310-G003 Manual © SiFive, Inc. Page 65...
  • Page 68 Chapter 14 Power-Management Unit (PMU) The FE310-G003 power-management unit (PMU) is implemented within the AON domain and sequences the system’s power supplies and reset signals during power-on reset and when tran- sitioning the "mostly off" (MOFF) block into and out of sleep mode.
  • Page 69 Signal Condition/ Synchronize Figure 7: FE310-G003 Power-Management Unit The PMU is a synchronous unit clocked by the in the AON domain. The PMU handles lfClk reset, wakeup, and sleep actions initiated by power-on reset, wakeup events, and sleep requests.
  • Page 70 0x51F15E pmukey address to set the state bit before any write access to any other PMU register. The state bit is reset at AON reset, and after any write to a PMU register. FE310-G003 Manual © SiFive, Inc. Page 68...
  • Page 71 Table 41 shows the default sleep program. Table 40: Default PMU wakeup program Program Instruction Value Meaning 0x3F0 Assert all resets and enable all power supplies 0x2F8 Idle cycles, then deassert hfclkrst 0x030 Deassert corerst padrst 0x030 Repeats FE310-G003 Manual © SiFive, Inc. Page 69...
  • Page 72 RTC comparator can rouse MOFF. Table 42: pmuie: PMU Interrupt Enables pmuie: PMU Interrupt Enables ( pmuie 0x140 Register Offset Bits Field Name Attr. Rst. Description [3:0] PMU Interrupt Enables pmuie [31:4] Reserved FE310-G003 Manual © SiFive, Inc. Page 70...
  • Page 73 PMU Wakeup Cause pmucause Table 44: Wakeup cause values Index Meaning Reset RTC Wakup ( Digitial input wakeup ( dwakeup Table 45: Reset cause values Index Meaning Power-on Reset External reset Watchdog timer reset FE310-G003 Manual © SiFive, Inc. Page 71...
  • Page 74 ≥48-bit counter width ensures there will no counter rollover for over 270 years assuming a 32.768 kHz low-frequency real-time clock source. The counter registers can be read or written over the TileLink bus. FE310-G003 Manual © SiFive, Inc. Page 72...
  • Page 75 . The maximum value of 15 in corresponds to rtcs rtclo rtcscale dividing the clock rate by , so for an input clock of 32.768 kHz, the LSB of will incre- rtcs FE310-G003 Manual © SiFive, Inc. Page 73...
  • Page 76 Table 49: rtccmp0: Comparator 0 rtccmp0: Comparator 0 ( rtccmp0 0x60 Register Offset Bits Field Name Attr. Rst. Description [31:0] Comparator 0 rtccmp0 FE310-G003 Manual © SiFive, Inc. Page 74...
  • Page 77 This chapter describes the operation of the General Purpose Input/Output Controller (GPIO) on the FE310-G003. The GPIO controller is a peripheral device mapped in the internal memory map. It is responsible for low-level configuration of actual GPIO pads on the device (direction, pull up-enable, and drive value ), as well as selecting between various sources of the controls for these signals.
  • Page 78 Chapter 16 General Purpose Input/Output Controller Figure 9: Structure of a single GPIO Pin with Control Registers. This structure is repeated for each pin. FE310-G003 Manual © SiFive, Inc. Page 76...
  • Page 79 Chapter 16 General Purpose Input/Output Controller 16.1 GPIO Instance in FE310-G003 FE310-G003 contains one GPIO instance. Its address and parameters are shown in Table 50. Table 50: GPIO Instance Instance Number Address ngpio 0x10012000 16.2 Memory Map The memory map for the GPIO control registers is shown in Table 51. The GPIO memory map has been designed to require only naturally-aligned 32-bit memory accesses.
  • Page 80 When configured as inputs, each pin has an internal pull-up which can be enabled by software. At reset, all pins are set as inputs, and pull-ups are disabled. 16.6 Drive Strength When configured as output, each pin has a software-controllable drive strength. FE310-G003 Manual © SiFive, Inc. Page 78...
  • Page 81 If there is no IOFx for a pin configured with IOFx, the pin reverts to full software control. Table 52: GPIO IOF Mapping GPIO Number IOF0 IOF1 PWM0_PWM0 PWM0_PWM1 SPI1_CS0 PWM0_PWM2 SPI1_DQ0 PWM0_PWM3 SPI1_DQ1 SPI1_SCK SPI1_CS2 SPI1_CS3 PWM2_PWM0 PWM2_PWM1 I2C0_SDA PWM2_PWM2 I2C0_SCL PWM2_PWM3 UART0_RX UART0_TX UART1_TX PWM1_PWM1 FE310-G003 Manual © SiFive, Inc. Page 79...
  • Page 82 Chapter 16 General Purpose Input/Output Controller Table 52: GPIO IOF Mapping GPIO Number IOF0 IOF1 PWM1_PWM0 PWM1_PWM2 PWM1_PWM3 UART1_RX FE310-G003 Manual © SiFive, Inc. Page 80...
  • Page 83 The UART peripheral does not support hardware flow control or other modem control signals, or synchronous serial data transfers. 17.2 UART Instances in FE310-G003 FE310-G003 contains two UART instances. Their addresses and parameters are shown in Table 53. Table 53: UART Instances...
  • Page 84 Table 55: Transmit Data Register Transmit Data Register ( txdata Register Offset Bits Field Name Attr. Rst. Description [7:0] Transmit data data [30:8] Reserved Transmit FIFO full full FE310-G003 Manual © SiFive, Inc. Page 82...
  • Page 85 Table 57: Transmit Control Register Transmit Control Register ( txctrl Register Offset Bits Field Name Attr. Rst. Description Transmit enable txen Number of stop bits nstop [15:2] Reserved [18:16] Transmit watermark level txcnt [31:19] Reserved FE310-G003 Manual © SiFive, Inc. Page 83...
  • Page 86 Table 59: UART Interrupt Enable Register UART Interrupt Enable Register ( 0x10 Register Offset Bits Field Name Attr. Rst. Description Transmit watermark interrupt enable txwm Receive watermark interrupt enable rxwm FE310-G003 Manual © SiFive, Inc. Page 84...
  • Page 87 (MHz) Target Baud (Hz) Divisor Actual Baud (Hz) Error (%) tlclk 31250 31250 115200 117647 31250 31250 115200 115107 0.08 250000 250000 FE310-G003 Manual © SiFive, Inc. Page 85...
  • Page 88 Table 62: Baud Rate Divisor Register Baud Rate Divisor Register ( 0x18 Register Offset Field Bits Attr. Rst. Description Name [15:0] Baud rate divisor. bits wide, and the reset div_width value is div_init [31:16] Reserved FE310-G003 Manual © SiFive, Inc. Page 86...
  • Page 89 Hardware interlocks ensure that the current transfer completes before mode transitions and control register updates take effect. 18.2 SPI Instances in FE310-G003 FE310-G003 contains three SPI instances. Their addresses and parameters are shown in Table Table 63: SPI Instances Instance...
  • Page 90 Chip select mode 0x18 csmode Reserved 0x1C Reserved 0x20 Reserved 0x24 Delay control 0 0x28 delay0 Delay control 1 0x2C delay1 Reserved 0x30 Reserved 0x34 Reserved 0x38 Reserved 0x3C Frame format 0x40 Reserved 0x44 FE310-G003 Manual © SiFive, Inc. Page 88...
  • Page 91 Table 65: Serial Clock Divisor Register Serial Clock Divisor Register ( sckdiv Register Offset Bits Field Name Attr. Rst. Description [11:0] Divisor for serial clock. bits wide. div_width [31:12] Reserved FE310-G003 Manual © SiFive, Inc. Page 89...
  • Page 92 -bit register that encodes the index of the CS pin to be toggled csid by hardware chip select control. The reset value is Table 69: Chip Select ID Register Chip Select ID Register ( csid 0x10 Register Offset Bits Field Name Attr. Rst. Description FE310-G003 Manual © SiFive, Inc. Page 90...
  • Page 93 • Direct-mapped flash mode is enabled. Table 71: Chip Select Mode Register Chip Select Mode Register ( csmode 0x18 Register Offset Bits Field Name Attr. Rst. Description [1:0] Chip select mode mode [31:2] Reserved FE310-G003 Manual © SiFive, Inc. Page 91...
  • Page 94 Rst. Description [7:0] CS to SCK Delay cssck [15:8] Reserved [23:16] SCK to CS Delay sckcs [31:24] Reserved Table 74: Delay Control Register 1 Delay Control Register 1 ( delay1 0x2C Register Offset FE310-G003 Manual © SiFive, Inc. Page 92...
  • Page 95 SPI I/O direction. This is reset to 1 for flash-enabled SPI controllers, 0 otherwise. [15:4] Reserved [19:16] Number of bits per frame [31:20] Reserved Table 76: SPI Protocol. Unused DQ pins are tri-stated. Value Description Data Pins Single DQ0 (MOSI), DQ1 (MISO) FE310-G003 Manual © SiFive, Inc. Page 93...
  • Page 96 Table 79: Transmit Data Register Transmit Data Register ( txdata Register Offset 0x48 Bits Field Name Attr. Rst. Description [7:0] Transmit data data [30:8] Reserved FIFO full flag full FE310-G003 Manual © SiFive, Inc. Page 94...
  • Page 97 Transmit watermark. The reset value is 1 for flash-enabled txmark controllers, 0 otherwise. [31:3] Reserved 18.14 Receive Watermark Register ( rxmark register specifies the threshold at which the Rx FIFO watermark interrupt triggers. rxmark The reset value is FE310-G003 Manual © SiFive, Inc. Page 95...
  • Page 98 [31:2] Reserved Table 84: SPI Watermark Interrupt Pending Register SPI Watermark Interrupt Pending Register ( 0x74 Register Offset Bits Field Name Attr. Rst. Description Transmit watermark pending txwm Receive watermark pending rxwm FE310-G003 Manual © SiFive, Inc. Page 96...
  • Page 99 Enable sending of command cmd_en [3:1] Number of address bytes (0 to 4) addr_len [7:4] Number of dummy cycles pad_cnt [9:8] Protocol for transmitting command cmd_proto [11:10] Protocol for transmitting address and padding addr_proto FE310-G003 Manual © SiFive, Inc. Page 97...
  • Page 100 Chapter 18 Serial Peripheral Interface (SPI) Table 86: SPI Flash Instruction Format Register [13:12] Protocol for receiving data bytes data_proto [15:14] Reserved [23:16] Value of command byte cmd_code [31:24] First 8 bits to transmit during dummy cycles pad_code FE310-G003 Manual © SiFive, Inc. Page 98...
  • Page 101 PWM instances can support comparator precisions ( ) up to 16 bits, with the example cmpwidth described here having the full 16 bits. To support clock scaling, the register is 15 bits pwmcount wider than the comparator precision cmpwidth FE310-G003 Manual © SiFive, Inc. Page 99...
  • Page 102 Chapter 19 Pulse Width Modulator (PWM) Figure 10: PWM Peripheral 19.2 PWM Instances in FE310-G003 FE310-G003 contains three PWM instances. Their addresses and parameters are shown in Table 87. Table 87: PWM Instances Instance Number Address ncmp cmpwidth 0x10015000 0x10025000 0x10035000 19.3 PWM Memory Map...
  • Page 103 Chapter 19 Pulse Width Modulator (PWM) Table 88: SiFive PWM memory map, offsets relative to PWM peripheral base address Offset Name Description PWM configuration register 0x00 pwmcfg Reserved 0x04 PWM count register 0x08 pwmcount Reserved 0x0C Scaled PWM count register...
  • Page 104 PWM1 Compare Center pwmcmp1center PWM2 Compare Center pwmcmp2center PWM3 Compare Center pwmcmp3center [23:20] Reserved PWM0/PWM1 Compare Gang pwmcmp0gang PWM1/PWM2 Compare Gang pwmcmp1gang PWM2/PWM3 Compare Gang pwmcmp2gang PWM3/PWM0 Compare Gang pwmcmp3gang PWM0 Interrupt Pending pwmcmp0ip FE310-G003 Manual © SiFive, Inc. Page 102...
  • Page 105 Table 91: Scaled PWM Count Register Scaled PWM Count Register ( pwms 0x10 Register Offset Bits Field Name Attr. Rst. Description [15:0] Scaled PWM count register. bits wide. pwms cmpwidth FE310-G003 Manual © SiFive, Inc. Page 103...
  • Page 106 0x28 Register Offset Bits Field Name Attr. Rst. Description [15:0] PWM 2 Compare Value pwmcmp2 [31:16] Reserved Table 95: PWM 3 Compare Register PWM 3 Compare Register ( pwmcmp3 0x2C Register Offset FE310-G003 Manual © SiFive, Inc. Page 104...
  • Page 107 FE310-G003 Manual © SiFive, Inc. Page 105...
  • Page 108 At a 16 MHz bus clock rate with 16-bit precision, this limits the fastest PWM cycle to 244 Hz, or 62.5 kHz with 8-bit precision. Higher bus clock rates allow proportion- FE310-G003 Manual © SiFive, Inc. Page 106...
  • Page 109 When a comparator is operating in center mode, the deglitch circuit allows one 0-to-1 transition during the first half of the cycle and one 1-to-0 transition during the second half of the cycle. FE310-G003 Manual © SiFive, Inc. Page 107...
  • Page 110 The PWM peripheral can also be used as a regular timer with no counter reset ( =0), pwmzerocmp where the comparators are now used to provide timer interrupts. FE310-G003 Manual © SiFive, Inc. Page 108...
  • Page 111 Chapter 20 Inter-Integrated Circuit (I²C) Master Interface The SiFive Inter-Integrated Circuit (I²C) Master Interface is based on OpenCores® I²C Master Core. Download the original documentation at https://opencores.org/project,i2c. All I²C control register addresses are 4-byte aligned. 20.1 I²C Instance in FE310-G003 FE310-G003 contains one I²C instance.
  • Page 112 Chapter 21 Debug This chapter describes the operation of SiFive debug hardware, which follows The RISC‑V Debug Specification 0.13. Currently only interactive debug and hardware breakpoints are sup- ported. 21.1 Debug CSRs This section describes the per-hart trace and debug registers (TDRs), which are mapped into...
  • Page 113 TDR-Specific Data [31:28] type Type of the trace & debug register selected tselect Table 101: CSRs tdata2/3 Trace and Debug Data Registers 2 and 3 tdata2/3 Bits Field Name Attr. Description [31:0] TDR-Specific Data FE310-G003 Manual © SiFive, Inc. Page 111...
  • Page 114 Debug ROM. The debugger may use it as described in The RISC‑V Debug Specifi- cation 0.13. 21.2 Breakpoints The FE310-G003 supports eight hardware breakpoint registers per hart, which can be flexibly shared between debug mode and machine mode. When a breakpoint register is selected with...
  • Page 115 Breakpoint action to take. 0 or 1. timing WARL Timing of the breakpoint. Always 0. select WARL Perform match on address or data. Always 0. Reserved WPRI Reserved [26:21] maskmax Largest supported NAPOT range FE310-G003 Manual © SiFive, Inc. Page 113...
  • Page 116 Table 105: NAPOT Size Encoding Match type and size maddress Exact 1 byte a…aaaaaa 2-byte NAPOT range a…aaaaa0 4-byte NAPOT range a…aaaa01 8-byte NAPOT range a…aaa011 16-byte NAPOT range a…aa0111 FE310-G003 Manual © SiFive, Inc. Page 114...
  • Page 117 When debug mode uses a breakpoint register, it is no longer visible to machine mode (that is, will be 0). Typically, a debugger will leave the breakpoints alone until it needs them, tdrtype either because a user explicitly requested one or because the user is debugging code in ROM. FE310-G003 Manual © SiFive, Inc. Page 115...
  • Page 118 – 0x300 0x3FF The FE310-G003 has 16 32-bit words of program buffer for the debugger to direct a hart to exe- cute arbitrary RISC-V code. Its location in memory can be determined by executing aiupc instructions and storing the result into the program buffer.
  • Page 119 Chapter 21 Debug 21.4 Debug Interface The SiFive FE310-G003 includes the JTAG debug transport module (DTM) described in The RISC‑V Debug Specification 0.13. This enables a single external industry-standard 1149.1 JTAG interface to test and debug the system. The JTAG interface is directly connected to input pins.
  • Page 120 On the FE310-G003, the IDCODE is set to 0x20000913 21.4.5 JTAG Debug Commands The JTAG DEBUG instruction gives access to the SiFive debug module by connecting the debug scan register between jtag_TDI jtag_TDO The debug scan register includes a 2-bit opcode field, a 7-bit debug module address field, and a 32-bit data field to allow various memory-mapped read/write operations to be specified with a single scan of the debug scan register.
  • Page 121 Chapter 22 References Visit the SiFive forums for support and answers to frequently asked questions: https://forums.sifive.com [1] A. Waterman and K. Asanovic, Eds., The RISC-V Instruction Set Manual, Volume I: User- Level ISA, Version 2.2, May 2017. [Online]. Available: https://riscv.org/specifications/ [2] ——, The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.10,...

Table of Contents