JVC XV-M50BK Service Manual page 11

1.7 MN102L62GGP (IC401) : Unit CPU
PinNo. Symbol I/O
1 WAIT I
2 RE O
3 SPMUTE O
4 WEN O
5 CS0 -
6 CS1 O
7 CS2 O
8 CS3 O
9 DRVMUTE O
10 SPKICK -
11 LSIRST O
12 WORD I
13 A0 O
14 A1 O
15 A2 O
16 A3 O
17 VDD -
18 SYSCLK -
19 VSS -
20 XI -
21 XO -
22 VDD -
23 OSCI I
24 OSCO O
25 MODE I
26 A4 O
27 A5 O
28 A6 O
29 A7 O
30 A8 O
31 A9 O
32 A10 O
33 A11 O
34 VDD -
35 A12 O
36 A13 O
37 A14 O
38 A15 O
39 A16 O
40 A17 O
41 A18 O
42 A19 O
43 VSS -
44 A20 O
45 TXSEL O
46 HAGUP O
47 CD/DVD I
48 ADPD O
49 HMFON O
50 TRVSW I
51 FGIN I
52 TRS
53 ADSCEN O
Function
Micon wait signal input
Read enable
Spindle muting output to IC251
Write enable
Not use
Chip select for ODC
Chip select for ZIVA
Chip select for outer ROM
Driver mute
Non connect
LSI reset
Bus selection input
Address bus 0 for CPU
Address bus 1 for CPU
Address bus 2 for CPU
Address bus 3 for CPU
Power supply
Non connect
Ground
Not use (Connect to vss)
Non connect
Power supply
Clock signal input(13.5MHz)
Clock signal output(13.5MHz)
CPU Mode selection input
Address bus 4 for CPU
Address bus 5 for CPU
Address bus 6 for CPU
Address bus 7 for CPU
Address bus 8 for CPU
Address bus 9 for CPU
Address bus 10 for CPU
Address bus 11 for CPU
Power supply
Address bus 12 for CPU
Address bus 13 for CPU
Address bus 14 for CPU
Address bus 15 for CPU
Address bus 16 for CPU
Address bus 17 for CPU
Address bus 18 for CPU
Address bus 19 for CPU
Ground
Address bus 20 for CPU
TX Select
Connect to pick-up
CD/DVD Detect signal
Power down control signal to IC511
HFM Control output to IC102
Detection switch of traverse inside
Focus gain input
Servo DSC serial I/F chip select
PinNo. Symbol I/O
54 VDD - Power supply
55 FEPEN O Serial enable signal for FEP
56 SLEEP O Standby signal for FEP
57 BUSY I Communication busy
58 REQ O Communication request
59 CIRCEN O CIRC serial I/F chip select
60 HSSEEK
61 VSS - Ground
62 EPCS O EEPROM chip select
63 EPSK O EEPROM clock
64 EPDI I EEPROM data input
65 EPDO O EEPROM data output
66 VDD - Power supply
67 SCLKO O Communication clock
68 S2UDT I Communication input data
69 U2SDT O Communication output data
70 CPSCK O Clock for ADSC serial
71 SDIN I ADSC serial data input
72 SDOUT O ADSC serial data output
73 - I Not use (Pull up)
74 - I Not use (Pull up)
75 NMI I NMI Terminal
76 ADSCIRQ I Interrupt input of ADSC
77 ODCIRQ I Interrupt input of ODC
78 DECIRQ I Interrupt input of ZIVA
79 WAKEUP - Connect to ground
80 ODCIRQ2 I Interruption of system control
81 ADSEP I Address data selection input
82 RST I Reset input
83 VDD - Power supply
84 TEST1 I Test signal 1 input
85 TEST2 I Test signal 2 input
86 TEST3 I Test signal 3 input
87 TEST4 I Test signal 4 input
88 TEST5 I Test signal 5 input
89 TEST6 I Test signal 6 input
90 TEST7 I Test signal 7 input
91 TEST8 I Test signal 8 input
92 VSS - Ground
93 D0 I/O Data bus 0 of CPU
94 D1 I/O Data bus 1 of CPU
95 D2 I/O Data bus 2 of CPU
96 D3 I/O Data bus 3 of CPU
97 D4 I/O Data bus 4 of CPU
98 D5 I/O Data bus 5 of CPU
99 D6 I/O Data bus 6 of CPU
100 D7 I/O Data bus 7 of CPU
XV-M50BK
Function
11