Summary of Contents for SynthCube Fuzz Bucket
- Page 2 Version: 1.1 Date: 2018-08-11 The Fuzz Bucket is an 8HP eurorack fuzz and delay module made up of a two transistor fuzz circuit and an MN3005 bucket brigade delay (BBD). Unlike most delay implementations which aim to mask sampling and reconstruction error, the Fuzz Bucket provides direct unfiltered access to delay line inputs and outputs as well as override of the BBD clock.
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Page 3: Controls And Connections
Controls & Connections Internal rate control - sets the rate of the internal clock generator from roughly 3kHz to 3MHz. Above 200kHz (roughly 4 o'clock position), the MN3005 BBD is overclocked. External clock override - AC coupled BBD clock override input. Any signal with at least 2V of swing between high and low values can be used. - Page 4 Schematic...
- Page 5 Parts Qty Value Refs Footprint Note Example Part R5 R6 R_0805 1/4W ERJ-T06J100V R_0805 ERJ-6ENF1000V R2 R4 R20 R_0805 ERJ-S06F1001V 5.6k R15 R16 R_0805 ERJ-6ENF5601V R7 R9 R_0805 ERJ-S06F1001V R_0805 ERJ-6ENF1202V R_0805 ERJ-6ENF2202V R_0805 ERJ-6ENF3302V R_0805 ERJ-6ENF4702V 100k R8 R10 R11 R12 R13 R14 R21 R_0805 ERJ-U06F1003V R24 R25...
- Page 6 Component Selection Notes An HEF4093 quad CMOS NAND IC was chosen for schmitt trigger U1 for a low typical hysteresis voltage of about 1V. This selection allows for a wide range of clock sources without the need for amplification. Any 4093 equivalent should work, but may require a larger clock input to reliably switch.
- Page 7 Build Instruction Clean PCB and inspect for defects. Solder transistors Q1 & Q2. Solder ICs U1, U2 & U4. Pin one on each chip is indicated on the silkscreen. Solder diodes D1, D2, D3 & D4. Solder all 0805 resistors. Solder all 0805 capacitors.
- Page 8 Insert pots RV2, RV3, RV4 & RV5 and jacks J2, J3, J4, J5, J6 & J7 according to silkscreen. Fit front panel and lightly attach all parts. Ensure flush connection with PCB and panel, then solder all jacks and pots. Clean board, tighten jacks and pots, then attach knobs.
- Page 9 Test and Adjustment Procedure Set all controls to minimum, fully counter-clockwise. Set RV1 (Clk Bias) trimmer to mid-point. Connect an oscilloscope to test point TP1 (Clk). Verify that the internal clock is generating a square wave running at approximately 3kHz. Vary rate control and check that the internal clock increases to roughly 3MHz at maximum (fully clockwise) position.
- Page 10 Verify roughly 4V peak to peak sinusoidal wave on output. Vary fuzz amount control and verify clipping of input signal. Set input A level to minimum, and swap input signal from A to B. Adjust input B level to maximum (fully clockwise) setting. Verify roughly 6V peak to peak sinusoidal wave on output.
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Page 11: Design Files
Design Files Schematic Diagram: Parts List: PCB Gerber Files: Kicad project: Gzipped TAR Sample front panel design: Inkscape SVG Front panel drill guide: Issues and Limitations Unfiltered outputs from the BBD carry a small amount of the clock signal, and at near ultra- sonic rates this clock noise may be perceived as a loud hiss. - Page 12 Acknowledgements The fuzz block applied to input A is a crude adaptation of the classic two transistor fuzz face circuit as published on ElectroSmash utilising notes on the use of silicon transistors in The Technology of the Fuzz Face by R. G. Keen. The delay core and the two-phase clock that drives it is based on a circuit published in Barry Klein's Electronic Music Circuits.
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