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PIN CONNECTIONS FOR EXPANSION INTERFACE
SIGNAL
DESCRIPTION
PIN
1
G N D
G R O U N D
G ND
G R O U N D
2
3
A 7
4
A 6
5
A 5
A 4
6
7
A1
8
A 3
9
A 2
10
AO
11
D5
12
D2
13
NC
14
D1
15
DO
16
D 3
17
D7
18
D6
+ 5V SUPPLY
19
VCC
D4
20
21
A 15
22
A 8
23
A 14
24
A 9
25
NC
NO C O N N EC TIO N
SIGNAL
DESCRIPTION
PIN
26
A 10
27
A 13
28
A11
29
A12
30
PHI
P IN T
31
32
NC
33
NC
PH LD A
34
35
PHANTO M
H A L T
36
37
PW AIT
38
IO R Q
39
PHOLD
WR
40
41
RD
42
CCDBS/STADBS
M REQ
43
44
DO DBS/ADDBS
M l
45
46
RESET
47
RFSH
NM I
48
49
GND
G ND
50
1.79 M Hz clock
IN T E R R U P T
NO C O N N EC TIO N
NO C O N N EC TIO N
PROCESSOR H O LD AC K N O W LED G E
PHANTO M
H A L T A C K N O W LED G E
PROCESSOR W A IT
IN P U T /O U T P U T REQUEST
PROCESSOR H O LD
PROCESSOR W R IT E
PROCESSOR READ
C O N T R O L A N D STA TU S BUS DISABLE
M E M O R Y REQUEST
D A T A A N D ADDRESS BUS DISABLE
F IR S T STA TE OF IN S T R U C T IO N CYCLE
CPU RESET
D Y N A M IC M E M O R Y REFRESH
N O N-M ASK AB LE IN T E R R U P T
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