GE CM6 Hardware Reference Manual page 56

CHAPTER 6
Chapter Scope
Processor
Clock Assignment
GE Intelligent Platforms – CM6 Hardware Reference Manual, Fourth Edition
Function Blocks
This section gives a brief overview over the software interfaces of onboard
devices on the CM6 CompactPCI Single Board Computer.
The CM6 is driven by the Freescale MPC8641 processor. This processor
integrated either one or two PowerPC e600 cores (previously referred to as the
G4 core) with system logic required for networking, storage and general
purpose applications. The e600 core consists of a processor core, 32Kbyte
separate level-one instruction and data caches and a 1Mbyte L2 cache. The two
cores can have private address space without any special software involvement.
The high level of integration in the MPC8641 helps simplify board design and
offers significant bandwidth and performance increase. The internal MPX
processor bus runs with a maximal frequency of 333MHz. The MPC8641 has
two memory controllers, a local bus controller, a programmable interrupt
controller, two I2C controllers, four channel DMA controller and a dual
universal asynchronous receiver transmitter (UART). For high speed
interconnect the MPC8641 provides two sets of PCI Express interfaces. The
device has also four integrated 10/100/1000 Ethernet controllers.
The clock scheme of the CM6 is very flexible. The main clock is a generated
from PLL and support 66MHz, 100MHz, 133MHz, and 166MHz for the
MPC8641. With this main clock the MPC8641 determines with configuration
pins the ratio between main clock – MPX-, memory, core, local bus-clock. The
selected main clock can be read at PLD register STAT0 bit [5:6], and the ratio
factors of the MPC8641 in the power-on reset register (PORPLLSR).
Clocks for the PCI Express (100MHz), PCI (33/66/100MHz), Timer (25MHz),
and Ethernet controller (125MHz) are supplied separately.
The clock frequency is set at the factory according to the used MPC8641 speed
grade.
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