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DS619 April 7, 2009
Introduction
The ChipScope™ PLB Integrated Bus Analyzer (IBA) core
is a specialized bus analyzer core designed to debug embed-
ded systems that contain the IBM CoreConnect™ Processor
Local Bus (PLB) version 4.6. The ChipScope PLB46 IBA
core in EDK is based on a Tcl script that generates an Hard-
ware Description Language (HDL) wrapper to the PLB IBA
and calls the ChipScope Core Generator (Coregen) to gener-
ate the netlist based on user parameters.
The ChipScope PLBv46 IBA is a soft IP core designed for
Xilinx® FPGAs and contains the following features:
•
Probes the master, slave, arbiter, and error status signals
of the PLBv46 bus
•
Probes the PLBv46 OR'ed slave signals
•
Automatically adjusts ports to the PLBv46 bus width
•
Separates master, slave, and error status signals into
independent match units which can be enabled or
disabled by a design parameter
•
Allows independent enabling or disabling of probed
master, slave, and error status signals for data capture
•
Supports trigger port customization by a design
parameter
•
Supports match unit type customization for each trigger
port by a design parameter
•
Supports sample depths from 1024-131,072 on
Virtex™-5 Devices selectable by a design parameter
•
Can probe as few as 1 signals and as many as 1115
signals on a Virtex-5 device
•
Provides a separate input bus to allow a user-defined
input debug port
•
Supports a trigger output indicator pin that can be sent
off chip or to other cores
For more information about the PLBv46 IBA core, refer to
the ChipScope Pro Software and Cores User Guide.
© 2009 Xilinx, Inc. Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
DS619 April 7, 2009
Product Specification
(Bus Analyzer) (v. 1.00a, 1.01a)
Supported Device
Family
Version of Core
Slices
LUTs
FFs
Block RAMs
Documentation
Design File Formats
Constraints File
Verification
Instantiation Template N/A
Reference Designs
Design Tool Requirements
Xilinx Implementation
Tools
Verification
Simulation
Synthesis
Provided by Xilinx, Inc.
www.xilinx.com
ChipScope PLBv46 IBA
Product Specification
LogiCORE™ Facts
Core Specifics
Spartan®-3, Spartan-3A, Spartan-3AN,
Spartan-3A DSP, Spartan-3E,
Virtex®-4, Virtex-4 FX, Virtex-4 LX,
Virtex-4 SX, Virtex-5 LX,
Virtex-5 LXT, Virtex-5 SXT
chipscope_plb46_iba
Resources Used
Min
N/A
N/A
N/A
N/A
Provided with Core
Product Specification
VHDL/EDIF
N/A
N/A
None
ISE® 11.1 or later
ChipScope Pro 11.1 or later
Not Supported in Simulation
XST
Support
v1.00a
Max
N/A
N/A
N/A
N/A
1
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Summary of Contents for Xilinx ChipScope PLB46 IBA v1.00a
- Page 1 ChipScope Pro Software and Cores User Guide. © 2009 Xilinx, Inc. Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.
- Page 2 Simulation Slave Simulation Simulation Simulation Slave Slave Slave Slave Simulation www.xilinx.com Description Icon control bus IO System Clock Generic Trigger Inputs IBA Trigger Output Registered reset output from arbitration logic Bus Error Interrupt PLB lock error indicator PLB Master slave read error indicator PLB Master slave write error indicator Master interrupt request.
- Page 3 Slave Slave Slave Slave Slave Slave Slave Slave www.xilinx.com Description PLB current master identifier PLB byte enables PLB Transfer Attribute PLB address bus, lower 32 bits PLB address bus, upper 32 bits PLB write data bus Output of SL_rdDBus OR gate...
- Page 4 Master Master Master Master Master Master Master Master Master www.xilinx.com Description Slave write error indicator Master bus request Master bus request priority Master Bus Lock Master abort bus request indicator PLB pending read request priority PLB pending write request priority...
- Page 5 Signal Name Interface Master Master Master Master Table 1 connect to the PLBv46 bus. The core divides related ports into 13 match www.xilinx.com Description Master transfer size PLB Master slave data bus width indicator Master transfer type Master byte enables...
- Page 6 Parameter Name C_FAMILY C_DEVICE C_PACKAGE C_SPEEDGRADE C_PLBV46_NUM_MASTERS C_PLBV46_NUM_SLAVES C_PLBV46_MID_WIDTH C_PLBV46_AWIDTH C_PLBV46_DWIDTH IBA Storage Options and Trig Out C_NUM_DATA_SAMPLES C_MAX_SEQUENCER_ LEVELS C_ENABLE_STORAGE_ QUALIFICATION www.xilinx.com Allowable Default VHDL Values Value Type spartan3, virtex5 String spartan3e, spartan3a, spartan3adsp, spartan3an, virtex4, virtex5 String String...
- Page 7 C_MU_1_TYPE_TRIG_RST_ ERR_STAT C_MU_1_CNT_W_TRIG_ RST_ERR_STAT C_MU_1_EN_STORE_TRIG_ RST_ERR_STAT PLB Grouped Control Bus C_USE_MU_2B_SIZE_BE C_USE_MU_2C_TATTR C_MU_2_NUM_GRP_CTL C_MU_2_TYPE_GRP_CTL C_MU_2_CNT_W_GRP_CTL C_MU_2_EN_STORE_GRP_ PLB Address C_USE_MU_3A_ABUS C_USE_MU_3B_UABUS C_MU_3_TYPE_ADDR C_MU_3_CNT_W_ADDR www.xilinx.com Allowable Default VHDL Values Value Type Integer Integer Integer Integer 0-189 Integer Integer 0,1-32 Integer Integer Integer...
- Page 8 C_MU_4_CNT_W_WR_DBUS 0,1-32 C_MU_4_EN_STORE_WR_ DBUS C_USE_MU_5_RD_DBUS C_MU_5_TYPE_RD_BUS 0,1,2,3,4,5 C_MU_5_CNT_W_RD_DBUS 0,1-32 C_MU_5_EN_STORE_RD_ DBUS Slave Control Bus C_USE_MU_6A_SLV_CTL C_USE_MU_6B_SLV_SZ_ WADDR C_MU_6_NUM_SLV_CTL_ C_MU_6_TYPE_SLV_CTL_ C_MU_6_CNT_W_SLV_CTL_ 0,1-32 www.xilinx.com Default VHDL Value Type Integer Integer Integer Integer Integer Integer Integer Integer Integer Integer Integer Integer Integer Integer...
- Page 9 C_MU_7_CNT_W_SLV_BSY C_MU_7_EN_STORE_SLV_ Slave Read/Writer Error Status C_USE_MU_8_SLV_RD_ERR C_MU_8_TYPE_SLV_RD_ C_MU_8_CNT_W_SLV_RD_ C_MU_8_EN_STORE_SLV_ RD_ERR C_USE_MU_9_SLV_WR_ERR 1,0 C_MU_9_TYPE_SLV_WR_ C_MU_9_CNT_W_SLV_WR_ C_MU_9_EN_STORE_SLV_ WR_ERR PLB Arbitration C_USE_MU_10_ARB_CTL C_MU_10_TYPE_ARB_CTL C_MU_10_CNT_W_ARB_CTL 0,1-32 www.xilinx.com Allowable Default VHDL Values Value Type Integer Integer Integer 0,1-32 Integer Integer Integer Integer 0,1-32 Integer...
- Page 10 C_MU_11_CNT_W_MSTR_ C_MU_11_EN_STORE_ MSTR_CTL PLB Master Size and Type Status C_USE_MU_12_MSTR_SZ C_MU_12_TYPE_MSTR_SZ C_MU_12_CNT_W_MSTR_SZ 0,1-32 C_MU_12_EN_STORE_ MSTR_SZ PLB Master Byte Enable C_USE_MU_13_MSTR_BE C_MU_13_TYPE_MSTR_BE C_MU_13_CNT_W_MSTR_B C_MU_13_EN_STORE_ MSTR_BE www.xilinx.com Allowable Default VHDL Values Value Type Integer Integer Integer Integer 0,1-32 Integer Integer Integer Integer...
- Page 11 ChipScope PLB46 IBA Module Block Diagram X-Ref Target - Figure 1 DS619 April 7, 2009 Product Specification Chipscope ICON icon_control mon_plb Chipscope iba_trig_out PLB_IBA iba_trig_in Figure 1: ChipScope PLB46 IBA Block Diagram www.xilinx.com DS283_01_092506...
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Page 12: Ordering Information
XST is the synthesis tool used for synthesizing the wrapper HDL generated for the ChipScope PLB IBA. The EDIF netlist output from XST and ChipScope Core Generator are then input to the Xilinx Foundation tool suite for actual device implementation. -
Page 13: Revision History
Notice of Disclaimer Xilinx is providing this design, code, or information (collectively, the “Information”) to you “AS-IS” with no warranty of any kind, express or implied. Xilinx makes no representation that the Information, or any particular implementation thereof, is free from any claims of infringement.
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