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TeleChips TCC720 User Manual

32-bit risc microprocessor for digital media player
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USER'S MANUAL
TCC720
32-bit RISC
Microprocessor
For
Digital Media Player
Preliminary Rev 0.51

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Summary of Contents for TeleChips TCC720

  • Page 1 USER’S MANUAL TCC720 32-bit RISC Microprocessor Digital Media Player Preliminary Rev 0.51...

  • Page 2: Table Of Contents

    TCC720 TABLE OF CONTENTS 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 TABLE OF CONTENTS 1. INTRODUCTION 1.1 Features 1.2 Pin Description 1.3 Package Diagram 2. ADDRESS & REGISTER MAP 3. DAI (Digital Audio Interface) & CDIF (CD-DSP Interface) 4.
  • Page 3 CHAPTER 1 NTRODUCTION...

  • Page 4: Introduction

    The on-chip USB controller enables the data transmission between a personal computer and storage of device such as NAND flash, HDD, CD etc, which can be controlled by TCC720. TCC720 also includes on-chip stereo audio CODEC eliminates the need of expensive external audio CODEC.

  • Page 5: Features

    TCC720 INTRODUCTION 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 1.1 FEATURES 32bit ARM940TDMI RISC CPU core 8KB instruction/data cache Internal boot ROM of 4Kbytes for various boot procedure(NAND, UART) and security Internal SRAM of 64K bytes for general usage...
  • Page 6 TCC720 INTRODUCTION 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 XIN, XOUT, XTIN, XTOUT, XFILT USB_DP / GPIO_B26, USB_DN / GPIO_B27 XA21 / DQM0 CLK Generator XA20 / DQM1 USB1.1 XA[19:18] Power Manager XA17 / ND_CLE...

  • Page 7: Pin Description

    TCC720 INTRODUCTION 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 1.2 Pin Description JTAG Interface Signal Name Type Description JTAG serial data input for ARM940T JTAG Test mode select for ARM940T JTAG test clock for ARM940T...
  • Page 8 TCC720 INTRODUCTION 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 General Purpose I/O Signal Shared Signal Type Description GPIO_A[15:12] EXINT[3:0] 124:121 GPIO_A[15:12] / External Interrupt Source 3 ~ 0 GSIO2[3:0] GPIO_A[11:8] (SDI_2, FRM_2, 118:115 GPIO_A[11:8] / General Purpose Serial I/O 2...
  • Page 9 TCC720 INTRODUCTION 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 USB / UART / IrDA Interface Signal Shared Signal Type Description USB D+ GPIO_B26 USB Function D+ pin / GPIO_B26 USB D- GPIO_B27 USB Function D- pin / GPIO_B27...
  • Page 10 TCC720 INTRODUCTION 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 General Purpose ADC Interface Signal Shared Signal Type Description ADIN[2:0] 84:82 General purpose multi-channel ADC input Mode Control Signal Shared Signal Type Description MODE1 Mode Setting Input 1...

  • Page 11: Package Diagram

    TCC720 INTRODUCTION 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 1.3 Package Diagram VSSIO VDDIO MODE1 LRCK/GPIO_B22 BCLK/GPIO_B21 UT_RX/IDE_nCS1/GPIO_B9 UT_TX/GPIO_B8 nTRST SDO0/GPIO_A0 ND_nWE/GPIO_B7 SCK0/GPIO_A1 SD_CKE/GPIO_B0 SFRM0/GPIO_A2 VSSI SDI0/GPIO_A3 GPIO_B29 SDO1/GPIO_A4 GPIO_B28 VDDI USB_DN/GPIO_B27 VSSI USB_DP/GPIO_B26...

  • Page 12: Address & Register Map

    CHAPTER 2 DDRESS & REGISTER MAP...
  • Page 13 Preliminary Spec 0.51 2 ADDRESS & REGISTER MAP 2.1 Address Map The TCC720 has fixed address maps for digital audio en-decoder system. The address space is separated MSB 4bits of address bus, the following table represents overall address space of TCC720 system.
  • Page 14 Dec. 16. 2002 Preliminary Spec 0.51 detailed operation. TCC720 has only one chip select for SDRAM, so its address space is dependent on SDRAM size attached to TCC720. TCC720 has various peripherals for controlling a digital audio en-decoder system. These peripherals can be configured appropriately by it’s own registers that can be accessed through...
  • Page 15 TCC720 ADDRESS & REGISTER MAP 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 2.2 Register Map DAI & CDIF Register Map (Base Address = 0x80000000) Name Address Type Reset Description DADI_L0 0x00 Digital Audio Left Input Register 0...
  • Page 16 TCC720 ADDRESS & REGISTER MAP 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Timer/Counter Register Map (Base Address = 0x80000200) Name Address Type Reset Description TCFG0 0x0000 0x00 Timer/Counter 0 Configuration Register TCNT0 0x0004 0x0000...
  • Page 17 TCC720 ADDRESS & REGISTER MAP 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 GPIO Register Map (Base Address = 0x80000300) Name Addr Type Reset Description GDATA_A 0x00 0xFFFFFFFF GPIO_A Data Register GIOCON_A 0x04 0xFFFF0000 GPIO_A Direction Control Register...
  • Page 18 TCC720 ADDRESS & REGISTER MAP 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 USB Register Map (Base Address = 0x80000500) Name Address Type Reset Description UBFADR 0x00 Function Address Register UBPWR 0x04 Power Management Register...
  • Page 19 TCC720 ADDRESS & REGISTER MAP 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 UART/IrDA Register Map (Base Address = 0x80000600) Name Address Type Reset Description 0x00 Receiver Buffer Register 0x00 Transmitter Holding Register 0x04 0x0000...
  • Page 20 TCC720 ADDRESS & REGISTER MAP 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Analog Interface & ETC Register Map (Base Address = 0x80000A00) Name Address Type Reset Description ADCTR 0x00 ADC Control Register ADDATA 0x04...
  • Page 21 TCC720 ADDRESS & REGISTER MAP 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 NAND flash Register Map (Base Address = N * 0x10000000) Name Address Type Reset Description 0x00 Command Cycle Register LADDR 0x04 Linear Address Cycle Register...

  • Page 22: Dai (Digital Audio Interface) & Cdif (Cd-Dsp Interface)

    CHAPTER 3 AI & CDIF...
  • Page 23 Preliminary Spec 0.51 3 DAI (Digital Audio Interface) & CDIF (CD-DSP Interface) 3.1 DAI The TCC720 provides digital audio interface that complies with IIS (Inter-IC Sound). The DAI has five input/output pins for IIS interface; MCLK, BCLK, LRCK, DAI, DAO. All DAI input/output pins are multiplexed with GPIO pins;...
  • Page 24 TCC720 DAI & CDIF 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 DAI Register Map (Base Address = 0x80000000) Name Address Type Reset Description DADI_L0 0x00 Digital Audio Left Input Register 0 DADI_R0 0x04 Digital Audio Right Input Register 0...
  • Page 25 TCC720 DAI & CDIF 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Digital Audio Mode Register (DAMR) 0x80000020 Reserved BD<1:0> FD<1:0> CM MM DAI Master Enable [15] DAI disabled DAI enabled DAI Transmitter Enable [14]...
  • Page 26 TCC720 DAI & CDIF 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 CDIF Clock Select CDIF Clock master mode disabled CDIF Clock master mode enabled. DAI Bit Clock Divider select [7:6] Div 4 ( 256fs->64fs ) Div 6 ( 384fs->64fs )
  • Page 27 TCC720 DAI & CDIF 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Digital Audio Volume Control Register (DAVC) 0x80000024 Reserved Reserved VC<3:0> DAI Volume control [3:0] 0000 0001 -6dB 0010 -12dB 0011 -18dB 0100 -24dB...
  • Page 28 TCC720 DAI & CDIF 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Input Buffer DADI LEFT0 RIGHT0 IIS_SDI Input Buffer LEFT1 Pointer DAVC RIGHT1 LEFT2 RIGHT2 LEFT3 RIGHT3 CDIF Data Output Buffer DADO LEFT0 IIS_SDO...
  • Page 29 TCC720 DAI & CDIF 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 LRCK Left Right 13 12 11 10 BCLK DAI/O MD=0 (IIS mode), BP=0, BCLK = 32fs LRCK Left Right 28 27 BCLK DAI/O...
  • Page 30 Preliminary Spec 0.51 3.2 CDIF The TCC720 provides CD-ROM interface for feasible implementation of CD-ROM application such as CD-MP3 player. The CDIF supports the industry standard IIS format and the LSB justified format that is used as the most popular format for CD-ROM interface by Sony and Samsung.
  • Page 31 TCC720 DAI & CDIF 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 CD Interface Control Register (CICR) 0x80000088 Reserved Reserved Reserved CDIF Enable CDIF disabled CDIF enabled CDIF Bit Clock select [3:2] 64fs 32fs 48fs...
  • Page 32 TCC720 DAI & CDIF 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Input Buffer CDDI0 LEFT0 RIGHT0 LEFT1 CDDI1 RIGHT1 LEFT2 CDAI Input Buffer RIGHT2 Pointer LEFT3 RIGHT3 CBCLK CLRCK Figure 3.3. CDIF Block Diagram...

  • Page 33: Interrupt Controller

    CHAPTER 4 NTERRUPT CONTROLLER...
  • Page 34 4 INTERRUPT CONTROLLER 4.1 Overview Interrupt controller can manage up to 16 interrupt sources. In TCC720, there are 4 external interrupt sources that can be detected various kind of method, that is a rising edge/ falling edge / level high / level low detection can be set for external interrupt sources. External interrupt sources can be reliably managed with noise filtering up to 100 ~ 400 us.
  • Page 35 TCC720 INTERRUPT CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 4.2 Register Description Interrupt Controller Register Map (Base Address = 0x80000100) Name Address Type Reset Description 0x00 0x0000 Interrupt Enable Register CREQ 0x04 Clear Interrupt Request Register...
  • Page 36 TCC720 INTERRUPT CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 External interrupt request 1 control External interrupt request 0 control Clear Interrupt Request Register (CREQ) 0x80000104 DMA LCD CDIF *) When writing “1” to each field, the interrupt request flag of corresponding interrupt is cleared.
  • Page 37 TCC720 INTERRUPT CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 FT3~FT0 Filter Type Clock based filter is used. The filter delay is proportional to PCLK period as the following equations. Filter Delay = T...

  • Page 38: Timer / Counter

    CHAPTER 5 IMER / COUNTER...
  • Page 39 5 TIMER / COUNTER 5.1 Overview The TCC720 has four 16bit and two 20bit timer counter. Each timer counter has 3 registers for various operation modes. Refer to register description table for details. When operating in counter modes, External interrupt pin is used as counting clock for that counter.
  • Page 40 TCC720 TIMER / COUNTER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 the TREF, TCNT register has 20bit resolution. It can be used for generation of a long time period. 5.2 Register Description Timer/Counter Register Map (Base Address = 0x80000200)
  • Page 41 TCC720 TIMER / COUNTER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Timer/Counter n Configuration Register (TCFGn) 0x800002n0 TCKSEL IEN PWM CON Clear Count TCNTn hold its value. TCNTn is cleared to zero. TCK Polarity...
  • Page 42 TCC720 TIMER / COUNTER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Timer/Counter n Counting Register (TCNTn) 0x800002n4 TCNTn[19:16] TCNTn[15:0] *) TCNTn is increased by 1 at every pulse of selected clock source. TCNTn can be set to any value by writing the value to this register.
  • Page 43 TCC720 TIMER / COUNTER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Timer/Counter Interrupt Request Register (TIREQ) 0x80000260 TWF TF5 Watchdog Timer Flag Watchdog timer has reached to its reference value. Timer/Counter n Flag Timer/counter n has been overflowed.
  • Page 44 TCC720 TIMER / COUNTER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Watchdog Timer Configuration Register (TWDCFG) 0x80000270 TCKSEL Watchdog timer is used for the system not to be stuck by generating a reset pulse automatically when the watchdog timer counter overflows to zero.
  • Page 45 CHAPTER 6 PIO PORT...
  • Page 46 6 GPIO (General Purpose I/O) PORT 6.1 Functional Description The TCC720 has a lot of general purpose I/Os that can be programmed by setting internal registers. All I/Os are set to input mode at reset. The block diagram of GPIO is in the following figure.
  • Page 47 Preliminary Spec 0.51 that CPU has written before. In TCC720, there are various kinds of peripherals that generate its own control signals. These peripherals can occupy the dedicated GPIO pins. This option is controlled by the state of the GSELx register. If a bit of these GSELx is 1, the corresponding GPIO pin is entered to other function mode, so used by other peripherals not by GPIO block.

  • Page 48: Gpio

    TCC720 GPIO PORT 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 6.2 Register Description GPIO Register Map (Base Address = 0x80000300) Name Addr Type Reset Description GDATA_A 0x00 0xFFFFFFFF GPIO_A Data Register GIOCON_A 0x04 0x00000000...
  • Page 49 TCC720 GPIO PORT 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 GPIO_A Data Register (GDATA_A) 0x80000300 0xFFFF Data for GPIO_A[15:0] pin GPIO_A Direction Control Register (GIOCON_A) 0x80000304 0xFFFF Direction control for GPIO_A[15:0] pin *) if a bit is set to 1, the corresponding GPIO pin is set to output mode.
  • Page 50 TCC720 GPIO PORT 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 GPIO_A Test Select Register (GTSEL_A) 0x8000030C TC5 TC1 TC4 TC0 *) if a bit is set to 1, and the corresponding bit of GSEL_A is 0, GPIO pin is used by the other dedicated function blocks.
  • Page 51 TCC720 GPIO PORT 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 USB[1:0] GPIO_B[27:26] Function Select [27:26] GPIO_B[27:26] pin is working as Normal GPIO Function GPIO_B[27] pin is working as USB D- Port GPIO_B[26] pin is working as USB D+ Port...
  • Page 52 TCC720 GPIO PORT 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 GPIO_B Test Select Register (GTSEL_B) 0x8000031C GST[2:0] *) if a bit is set to 1, and the corresponding bit of GSEL_B is 0, GPIO pin is used by the other dedicated function blocks.

  • Page 53: Clock Generator

    CHAPTER 7 LOCK GENERATOR...
  • Page 54 7 CLOCK GENERATOR 7.1 Functional Description In TCC720, there are a lot of peripherals for which has different operating frequency. To support an appropriate stable clock to each other peripherals, TCC720 has clock generator unit and for considering power consumption there is also power management unit that can manage several operating modes, such as initialization mode, normal operation mode, idle mode, stop mode.
  • Page 55 16.4 ms The DIVCLK1 are used as main clock of TCC720 and it can be either an oscillator output or PLL output clock. It is the source of system clocks (FCLK, HCLK, PCLK). The PCLK can be also driven by XTIN.
  • Page 56 0. Power down and Idle mode bit are write-only register, and it is always 0 when read CKCTRL register. Power Down Mode [25] TCC720 goes to power down mode. All blocks disabled. IDLE Idle Mode [24] TCC720 goes to idle mode.
  • Page 57 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 XTIN Sub Clock Control [12] Disable XTIN Clock PLL Control [11] Disable PLL block GSIO Control Disable GSIO block Timer Control Disable Timer block...
  • Page 58 / ((P + 2) * 2 S/M/P The TCC720 has one PLL for generating of internal main clock. This internal PLL can generate the required frequency by setting internal register. The desired frequency can be acquired by the following equation.
  • Page 59 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 System Clock Control Register (SCLKmode) 0x80000408 P_PHASE F_PHASE H_PHASE It generates FCLK, HCLK, PCLK for system operation. FCLK is dedicated for ARM940T processor, HCLK is used as internal AHB bus clock, and PCLK is for APB bus clock. Each clock is generated by 6bit DCO (Digital Controlled Oscillator) that can generate a stable and variable frequency as long as its frequency is below about 0.1 times of that of divisor clock.
  • Page 60 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 DCLK (DAI/CODEC) Control Register (DCLKmode) 0x8000040C D_PHASE[13:0] DIVD DIVD DCLK Divisor Clock Select [15:14] use XIN as a divisor clock of DCLK generator use PLL output as a divisor clock of DCLK generator...
  • Page 61 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 EXTCLK Control Register (EXTCLKmode) 0x80000414 DIVXT EX_PHASE[13:0] DIVXT EXTCLK Divisor Clock Select [15:14] use XIN pin as a divisor clock of EXTCLK generator use PLL output as a divisor clock of EXTCLK generator...
  • Page 62 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 UTCLK (UART) Control Register (UTCLKmode) 0x80000418 DIVUT UT_PHASE[13:0] DIVUT UTCLK Divisor Clock Select [15:14] use XIN pin as a divisor clock of UTCLK generator...
  • Page 63 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 UBCLK (USB) Control Register (UBCLKmode) 0x8000041C DIVUB UB_PHASE[5:0] UBCLK is used as the main clock of USB block. It is generated by a DCO that has 6bit resolution, and its frequency is set by writing the phase value calculated by the following equation to the UB_PHASE register.
  • Page 64 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 TCLK (Timer) Control Register (TCLKmode) 0x80000424 DIVT TC_PHASE[5:0] DIVT TCLK Divisor Clock Select [9:8] use XIN pin as a divisor clock of TCLK generator...
  • Page 65 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 GCLK (GSIO) Control Register (GCLKmode) 0x80000428 DIVG GC_PHASE[5:0] DIVG GCLK Divisor Clock Select [9:8] use XIN pin as a divisor clock of GCLK generator...
  • Page 66 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Software Reset Register (SW_nRST) 0x8000043C DMA Block Reset Control [12] Reset for DMA is released Reset for DMA is generated Miscellaneous Block Reset Control...
  • Page 67 TCC720 CLOCK GENERATOR 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Interrupt Controller Block Reset Control Reset for Interrupt Controller is released Reset for Interrupt Controller is generated DAI/CDIF Block Reset Control Reset for DAI/CDIF is released...

  • Page 68: Usb (Universal Serial Bus) Controller

    CHAPTER 8 SB CONTROLLER...
  • Page 69 Preliminary Spec 0.51 8 USB (Universal Serial Bus) CONTROLLER 8.1 Overview The TCC720 supports a fully compliant to USB 1.1 specification, full-speed (12 Mbps) functions and suspend/resume signaling. The USB controller is compatible with both OpenHCI and Intel UHCI standards.
  • Page 70 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 8.2 Register Description USB Register Map (Base Address = 0x80000500) Name Address Type Reset Description NON INDEXED REGISTERS UBFADR 0x00 Function Address Register UBPWR...
  • Page 71 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Function Address Register (UBFADR) 0X80000500 Reserved FADR Function Address Update UP = 0 Function address doesn’t be updated UP = 1 Function address can be updated with FADR The MCU sets this bit whenever it updates the FADR field.
  • Page 72 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Power Management Register (UBPWR) 0x80000504 Reserved RST RSM SP ENSP Type Reset Signal Indicates that 1 reset signaling is received from the host Type...
  • Page 73 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Endpoint Interrupt Register (UBEIIR) 0x80000508 Reserved EP2 EP1 EP0 EP[2:0] Type EP Interrupt Flag [2:0] if bit n is 1 Indicates that the USB EP interrupt has been generated...
  • Page 74 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 The EP0 interrupt is generated under the following conditions: OUT Packet is ready. ORDY field is set in the CSR register IN Packet is ready. IRDY field is set in the CSR register...
  • Page 75 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Endpoint Interrupt Enable Register (UBEIEN) 0x8000051C Reserved EP2 EP1 EP0 USB Interrupt Enable Register (UBIEN) 0x8000052C Reserved RST RSM SP Corresponding to each interrupt register, there is an INTERRUPT ENABLE register (except resume interrupt enable).
  • Page 76 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 USB Index Register (UBIDX) 0x80000538 Reserved This Index register is used to indicate the endpoint number while accessing the indexed registers: MAXP, INCSR1/2, OCSR1/2, OFIFO1/2.
  • Page 77 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 IN CSR1 Register (INCSR1n) 0x80000544 Reserved CTGL STST ISST FLFF FNE IRDY CTGL Type Clear Data Toggle Bit The data toggle bit is cleared...
  • Page 78 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 EP0 CSR Register (EP0CSR) 0x80000544 Reserved CLSE CLOR ISST CEND DEND STAL IRDY ORDY *) EP0 CSR register can access by writing “0” to UBIDX register, and use same address as INCSR1.
  • Page 79 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 IRDY Type IN Packet Ready Indicates that the packet has been successfully sent to host After writing a packet of data into EP0 FIFO, set this bit to 1.
  • Page 80 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 OUT CSR1 Register (OCSR1n) 0x80000550 Reserved CTGL STST ISST FLFF FFL ORDY CTGL Type Data Toggle Bit The data toggle sequence bit is reset to DATA0...
  • Page 81 TCC720 USB CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 OUT FIFO Write Count 1 Register (OFIFO1n) 0x80000558 Reserved OFIFO1n OUT FIFO Write Count 2 Register (OFIFO2n) 0x8000055C Reserved OFIFO2n There are two register, OFIFO1n and OFIFO2n, which maintain the write count. OFIFO1n maintains the lower bytes, while OFIFO2n maintains the higher byte.
  • Page 82 CHAPTER 9 ART/IrDA CONTROLLER...

  • Page 83: Uart / Irda

    Preliminary Spec 0.51 9 UART / IrDA 9.1 Functional Description The TCC720 has 1 simple UART module that can be used in programming the system software or IrDA interfacing. The block diagram of UART is in the following figure. Receiver...
  • Page 84 TCC720 UART / IrDA 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 9.2 Register Desciption UART/IrDA Register Map (Base Address = 0x80000600) Name Address Type Reset Description 0x00 Receiver Buffer Register 0x00 Transmitter Holding Register...
  • Page 85 TCC720 UART / IrDA 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Receiver Buffer Register (RXD) 0x80000600 Received Data (when reading) Whenever FRX flag of IR register is set, or RA flag of LSR register is set, reading of this register gets the 1 byte of received data.
  • Page 86 TCC720 UART / IrDA 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Interrupt Register (IR) 0x80000608 Receiver Line Status Interrupt [10] disabled enabled Transmitter Holding Register Empty Interrupt disabled enabled Receiver Data Available Interrupt disabled...
  • Page 87 TCC720 UART / IrDA 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Request for Transmitter Holding Register Empty Interrupt Interrupt has not generated Interrupt has generated, but not cleared Request for Receiver Data Available Interrupt...
  • Page 88 TCC720 UART / IrDA 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 UART/IrDA Control Register (CR) 0x8000060C FIFO Start Bit Width Check Check if the pulse width of start bit is more than 0.5 bit duration of baud rate Don’t check the pulse width of start bit (used only for test or boot mode)
  • Page 89 TCC720 UART / IrDA 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Stop Bit 1 Stop bit 2 Stop bit Number of Bits per Character 8 bit 7 bit 9 - 7...
  • Page 90 TCC720 UART / IrDA 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Line Status Register (LSR) 0x80000610 Transmitter FIFO Not empty Empty *) Transmitter FIFO depth is fixed to 4. Transmitter FIFO Not full Full *) Transmitter FIFO depth is fixed to 4.
  • Page 91 TCC720 UART / IrDA 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 IrDA Configuration Register 1 (IrDACFG1) 0x80000614 P1 POL LB IrDA TX Enable [15] IrDA TX is disabled, UART mode is used IrDA TX is enabled...
  • Page 92 TCC720 UART / IrDA 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 IrDA Configuration Register 2 (IrDACFG2) 0x80000618 P1 POL MAX1 MIN1 IrDA RX Enable [15] IrDA RX is disabled, UART mode is used IrDA RX is enabled...
  • Page 93 CHAPTER 10 SIO PORT...

  • Page 94: Gsio (General Purpose Serial Input/Output)

    Dec. 16. 2002 Preliminary Spec 0.51 10 GSIO (General Purpose Serial Input/Output) PORT The TCC720 has three GSIOs for communication between the TCC720 and other devices that have serial interface. All the pins in the GSIOs are multiplexed with GPIOs.
  • Page 95 TCC720 GSIO 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 GSIO Register Map (Base Address = 0x80000700) Name Address Type Reset Description GSDO0 0x00 GSIO0 Output Data Register GSDI0 0x04 GSIO0 Input Data Register GSCR0...
  • Page 96 TCC720 GSIO 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 GSIOn Control Register (GSCR0, GSCR1, GSCR2, GSCR3) 0x800007x8 WORD DELAY FRM1 FRM2 GSIO Enable [31] GSIO Disabled GSIO Enabled First Bit Select [30] LSB first...
  • Page 97 TCC720 GSIO 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Frame pulse polarity [12] FRM has low active pulse FRM has high active pulse FRM1 Frame pulse start position [11:6] Frame pulse starts after n base clock has generated...
  • Page 98 TCC720 GSIO 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 The following figures represent some kinds of various GSIO operations. div_factor = 1 ; div4 = 2*(1+1) word_size = 7 ; 8bits = 7+1 init_delay = 2, clk_pol = 0...

  • Page 99: Miscellaneous Peripherals

    CHAPTER 11 ISCELLANEOUS PERIPHERALS...

  • Page 100: Adc

    11 MISCELLANEOUS PERIPHERALS 11.1 ADC The TCC720 has 3-input general purpose low-power ADC for battery level detection, remote control interface, touch screen interface, etc. It is a CMOS type 8bit/10bit changeable A/D converter which combines suitable blocks for various purpose such as an analog input multiplexer, auto offset calibration comparator, 8bit/10bit changeable successive approximation register (SAR), etc.
  • Page 101 TCC720 MISCELLANEOUS PERIPHERALS 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 ADC Data Register (ADCDATA) 0x80000A04 ADATA ADATA ADC Data [10:1] When 8bit mode, lsb 2bit must be ignored. When 10bit mode, ADC data = adc...

  • Page 102: Codec

    Preliminary Spec 0.51 11.2 CODEC The TCC720 has on-chip sigma delta type 16bit audio stereo CODEC for high grade digital audio en-decoder systems. It contains various blocks such as compensation filter, digital volume attenuator, de-emphasis filter, FIR filter, sinc filter, digital sigma-delta modulator, analog postfilter, anti-image filter, etc.
  • Page 103 TCC720 MISCELLANEOUS PERIPHERALS 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Data Format Select 16bit Right Justified Mode is selected 16bit IIS Mode is selected FSEL Sample Frequency Select [6:5] 0, 3 32KHz, 44.1KHz, 48KHz mode (System clock must be 256*fs) 16KHz, 22.05KHz mode (System clock must be 512*fs)
  • Page 104 TCC720 MISCELLANEOUS PERIPHERALS 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 CODEC Gain Control Register (CDC_GAIN) 0x80000A0C DATA Gain Register Select [5:4] ADC Left Channel is selected ADC Right Channel is selected DAC Left Channel is selected...
  • Page 105 TCC720 MISCELLANEOUS PERIPHERALS 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 11.3 ETCETERA Count Leading Zero Register (CLZ) 0x80000A10 CLZ[31:16] CLZ[15:0] When X is written to CLZ register, the number of zero counting from MSB of X can be calculated by reading CLZ register.

  • Page 106: Dma Controller

    CHAPTER 12 MA CONTROLLER...
  • Page 107 12 DMA CONTROLLER 12.1 Functional Description TCC720 has a simple 1-channel DMA controller for data transfer. It can be used to transfer data from some kind of memory block to other kind of memory block. The block diagram of DMA controller is in the following figure.
  • Page 108 TCC720 DMA CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 In SINGLE type transfer, 1 Hop of transfer occurs only once at every DMA requests. The 1 Hop of transfer means 1 burst read followed by 1 burst write. 1 burst means 1, 2 or 4 consecutive read or write cycles defined by CHCTRL[7:6] field.
  • Page 109 TCC720 DMA CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 12.2 Register Description DMA Controller Register Map (Base Address = 0x80000E00) Name Address Type Reset Description ST_SADR 0x00 Start Address of Source Block SPARAM...
  • Page 110 TCC720 DMA CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Source Block Parameter Register (SPARAM) 0x80000E04 / 0x80000E08 SMASK[23:8] SMASK[7:0] SINC[7:0] SMASK Source Address Mask Register [23:8] non-masked masked *) Each bit field controls the corresponding bit of source address field. That is, if SMASK[23] is set to 1, the 28th bit of source address is masked, and if SMASK[22] is set to 1, the 27th bit of source address is masked, and so on.
  • Page 111 TCC720 DMA CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Destination Block Parameter Register (DPARAM) 0x80000E14 / 0x80000E18 DMASK[23:8] DMASK[7:0] DINC[7:0] DMASK Destination Address Mask Register [23:8] non-masked masked *) Each bit field controls the corresponding bit of source address field. That is, if DMASK[23] is set to 1, the 28th bit of source address is masked, and if DMASK[22] is set to 1, the 27th bit of source address is masked, and so on.
  • Page 112 TCC720 DMA CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Current Source Address Register (C_SADR) 0x80000E0C C_SADR[31:16] C_SADR[15:0] *) This register contains current source address of DMA transfer. Current Destination Address Register (C_DADR) 0x80000E1C...
  • Page 113 TCC720 DMA CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Channel Control Register (CHCTRL) 0x80000E24 DMASEL[12:0] CONT LOCK TYPE BSIZE WSIZE FLAG IEN DMASEL Select Source of DMA Request [28:16] Each bit field selects corresponding signal as a source for DMA request.
  • Page 114 TCC720 DMA CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 BSIZE Burst Size [7:6] 1 Hop transfer consists of 1 pair of read and write cycle. 1 Hop transfer consists of 2 pair of read and write cycle...

  • Page 115: Memory Controller

    CHAPTER 13 EMORY CONTROLLER...

  • Page 116: Overview

    13 MEMORY CONTROLLER 13.1 Overview TCC720 has a memory controller for various kind of memory for digital media en-decoding system. It can manipulate SDRAM, Flash (NAND, NOR type), ROM, SRAM type memories, and also support the IDE interface for HDD or USB2.0 device. It has configurable data bus width through the GPIO pin or each configuration register.
  • Page 117 TCC720 MEMORY CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Memory Controller Register Map (Base Address = 0xF0000000) Name Address Type Reset Description SDCFG 0x00 0x4268A020 SDRAM Configuration Register SDFSM 0x04 SDRAM FSM Status Register...

  • Page 118: Sdram Controller

    Dec. 16. 2002 Preliminary Spec 0.51 13.2 SDRAM Controller SDRAM controller can control from 64Mbit up to 256Mbit SDRAM. In TCC720 system, the SDRAM contains almost parts for system operation. (program, data, ESP buffer, etc is located in SDRAM). The SDRAM parameter such as size, refresh period, RAS to CAS delay, refresh to idle delay can be programmed by internal register.
  • Page 119 TCC720 MEMORY CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 SDBASE SDRAM Base Address [27:24] Indicates the MSB 4bit of SDRAM area. That is SDRAM base = 0xN0000000 Delay of Refresh to Idle (tRC)
  • Page 120 TCC720 MEMORY CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 SDRAM Write Cycle (Non-sequential) SDCLK SDnCS nRAS nCAS tRCD CAS0 CAS1 DQM0 DQM1 Stop SDRAM Read Cycle (Row Actived) SDCLK SDnCS nRAS nCAS Stop...
  • Page 121 RAM must be mapped to these space as the system program including interrupt vector table is located in this area. To satisfy this requirement, TCC720 provide RM flag. BM flag is used to select the boot procedure between the 7 kinds of them. Refer to chapter of boot mode for details.

  • Page 122: Miscellaneous Configuration

    TCC720 MEMORY CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Miscellaneous Configuration Register (MCFG) 0xF0000008 JTEN SDEN SDS GPO RM Type Bus Width Flag [15] The state of READY pin is low. The state of READY pin is high.
  • Page 123 TCC720 MEMORY CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 JTEN Type Master of Internal Memory Select JTAG port is disabled JTAG port is enabled SDEN Type Master of Internal Memory Select SDRAM controller is disabled...

  • Page 124: External Memory Controller

    TCC720 MEMORY CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 13.4 External Memory Controller External memory controller can control external memories such as NAND or NOR type flash memory and ROM, SRAM type memory. These memories are selected by nCS3 ~ nCS0 pins.
  • Page 125 But if the system uses multiple NAND flashes by sharing a chip select but separating each data to 16 or 32bit data bus of TCC720, the AMSK must be set to 1, so the address can be fed to each NAND flashes.
  • Page 126 Figure 13.3 Basic Timing Diagram for External Memories In case of IDE type memories, there are two chip enable signals for it. In TCC720, each enable can be controlled by offset address space. ‘nCS0’ reflects that the offset address range of 0 ~ 0x1F is accessed, ‘nCS1’...
  • Page 127 TCC720 MEMORY CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 In case of NAND flash type memories, there are several sub-registers for accessing. The followings are these sub-registers. (M is base field of CSCFGn register)
  • Page 128 TCC720 MEMORY CONTROLLER 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 Single Address Cycle Register (IADDR) 0xM000000C Reserved Reserved IADDR *) When CPU writes to this register, one cycle of address cycle is generated. Data Register (DATA)

  • Page 129: Internal Memories

    Preliminary Spec 0.51 14.5 Internal Memories In TCC720, there is 64Kbytes of SRAM for general purposes and 4Kbytes of ROM for system initialization. SRAM area is dedicated to area 3 (0x30000000 ~ 0x3FFFFFFF), and also accessed by area 0 (0x00000000 ~ 0x0FFFFFFF) when there are no devices assigned to area 0.
  • Page 130 CHAPTER 14 OOTING PROCEDURE...

  • Page 131: External Rom Boot

    Preliminary Spec 0.51 14 BOOTING PROCEDURE In the TCC720, there is a internal boot ROM for system initialization process. It contains the fundamental routines for system initialization or firmware upgrading through various interface such as UART, HPI(Host Port Interface) BUS.
  • Page 132 TCC720 BOOTING PROCEDURE 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 14.1 External Boot It support an external boot ROM. When external boot mode, the sequence begins from external ROM that is attached to nCS3.
  • Page 133 Because of TCC720 always regard none 0xFF data as ‘0’, it is more robust to set the baud rate of a host UART faster than that of TCC720. The baud rate of a host UART must be as fast as that the duration of the start bit is shorter than that of TCC720 and longer than the period of UART clock (XIN/8 or XTIN).
  • Page 134 Preliminary Spec 0.51 1 byte unit. (0xFF or others) TCC720 enables UART as 9600 baud, none parity bit, 1 stop bit, and 7 data bits. ii) It receives initial code size of 16bit. iii) Receive a code of 32bit with order of MSB first and then 1 bit even parity information.
  • Page 135 AA / DA At first, TCC720 checks if the second byte of each spare area is ‘0xC4’ or not starting from the last page to first page. It considers the page of containing ‘0xC4’ at the second byte in that spare area as the start page of containing the initialization codes, so it copies those codes from NAND to internal SRAM.
  • Page 136 After the initialization code finishes, and the code returns by the above exit code, the main F/W copy code begins copy from the start page contained in R0 register. TCC720 copies the size of page – 8 bytes of codes per every page to the area starting from the address of ‘0x00000000’.
  • Page 137 TCC720 BOOTING PROCEDURE 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 The procedure of booting from NAND flash is displayed in figure 14.4 Device code reading & Mode Setting (Bus width = 8bit, CADR register setting)
  • Page 138 In both cases, the NOR flash must be connected via nCS3 signal. In case of non-encrypted mode, the F/W code in external flash is directly fetched to TCC720 without any other intermediate processing, but in case of encrypted mode, the F/W code in external flash is stored in encrypted value, so boot ROM must decrypt it ahead and then copy these codes to the other random accessible memories.
  • Page 139 14.5 Development mode To ease the effort for starting development withTCC720, TCC720 provides development mode in booting. In this mode, JTAG interface is enabled and set cache & protection unit of TCC720 appropriately. The table 14.4 describes the region setting in this mode.

  • Page 140: Jtag Debug Interface

    CHAPTER 15 TAG DEBUG INTERFACE...
  • Page 141 Preliminary Spec 0.51 15 JTAG DEBUG INTERFACE The TCC720 has the ARM940T core as main controller, and JTAG interface for developing the application programs. It can be connected with Multi-ICE of ARM or other third party’s in-circuit emulator supporting for ARM940T core.
  • Page 142 CHAPTER 16 ACKAGE DEMENSION...

  • Page 143: Package Dimension

    TCC720 PACKAGE DIMENSION 32-bit RISC Microprocessor for Digital Media Player Dec. 16. 2002 Preliminary Spec 0.51 16 PACKAGE DEMENSION 16.1 128-Pin TQFP 16.00BSC 14.00BSC TCC720 0.40BSC 0.18 0.05 (0.80) 0.10 0.05 1.00 0.05 1.20MAX Figure 16.1 Package Dimension of 128-TQFP-1414...

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