Renesas Tsi301 HyperTransport User Manual
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Renesas Tsi301 HyperTransport User Manual

Renesas Tsi301 HyperTransport User Manual

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®
Tsi301
™
HyperTransport to PCI
User Manual
80D3000_MA001_02
September 2009
6024 Silver Creek Valley Road, San Jose, California 95138
Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775
Printed in U.S.A.
©2009 Integrated Device Technology, Inc.

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  • Page 1 ® Tsi301 ™ HyperTransport to PCI User Manual 80D3000_MA001_02 September 2009 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775 Printed in U.S.A. ©2009 Integrated Device Technology, Inc.
  • Page 2 GENERAL DISCLAIMER Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use.

  • Page 3: About This Manual

    About This Manual This reference manual contains technical specifications for the Tsi301 HyperTransport PCI bridge chip. Notes The manual is intended for use by system designers and developers who are using the chipset in their designs. HyperTransport and LDT In this manual, HyperTransport technology and LDT (Lightning Data Transport) are sometimes used interchangeably.
  • Page 4 Direct Memory Access DRAM Direct Random Access Memory ESBGA Enhanced Super Ball Grid Array FIFO First In, First Out HSTL High-Speed Transistor Logic Input/Output Tsi301 HyperTransport to PCI User Manual *Notice: The information in this document is subject to change without notice...
  • Page 5 Serial Initialization Packet Serial Presence Detect Serial ROM Interface SROM Serial Read Only Memory SRAM Static Random Access Memory System Reference Manual Tsi301 HyperTransport to PCI User Manual *Notice: The information in this document is subject to change without notice...
  • Page 6 About This Manual Notes Tsi301 HyperTransport to PCI User Manual *Notice: The information in this document is subject to change without notice...

  • Page 7: Chapter 1 Bridge Features

    Chapter 1 Bridge Features This chapter describes the features and operation of the API NetWorks HyperTransport PCI bridge. Notes 1.1 HyperTransport PCI Bridge Features The HyperTransport PCI bridge is an I/O bridge from HyperTransport to PCI with the following features: •...

  • Page 8: Pci Master

    HyperTransport PCI bridge provides a Serial Initialization Packet (SIP) interface to read an external SROM during a cold reset sequence. Tsi301 HyperTransport to PCI User Manual 1-10 *Notice: The information in this document is subject to change without notice...

  • Page 9: Interface Levels

    HyperTransport transmit clocks. The bypass clocks run directly at the frequency provided. Both bypass clocks must be derived from the same base frequency source. Tsi301 HyperTransport to PCI User Manual 1-10 *Notice: The information in this document is subject to change without notice...
  • Page 10 Tsi301 Notes Tsi301 HyperTransport to PCI User Manual 1-10 *Notice: The information in this document is subject to change without notice...

  • Page 11: Chapter 2 Signal Descriptions

    Chapter 2 Signal Descriptions 2.1 HyperTransport Signals Notes Note: The Lx_ prefix denotes signals associated with either HyperTransport Link 0 (x=0) or Hyper- Transport Link 1 (x=1). The PCI bridge HyperTransport implementation is a standard HyperTransport design. Table 2.1 lists all HyperTransport signals.
  • Page 12 If AP_TYPEDET_N is pulled high and VDD3050 PCI[7:0] is at 5.0 V, PCI signals conform to the PCI 5.0 V signalling rules. No other combinations of AP_TYPEDET_N and VDD3050 PCI[7:0] are supported. Tsi301 HyperTransport to PCI User Manual *Notice: The information in this document is subject to change without notice...
  • Page 13 Open Drain Output. In Pass1, 2.5 volt open drain LVCMOS. In Pass2, 3.3 volt open drain LVCMOS. The HyperTransport PCI bridge has detected a non-fatal error. Tsi301 HyperTransport to PCI User Manual *Notice: The information in this document is subject to change without notice...

  • Page 14: Test Signals

    Note: This signal should be pulled low for normal functional mode. TMODE [3:0] Input. Test pins. In Pass1, 2.5 volt LVCMOS. In Pass2, 3.3 volt LVCMOS. Tsi301 HyperTransport to PCI User Manual *Notice: The information in this document is subject to change without notice...
  • Page 15 If AP_TYPEDET _N is pulled high, these should be at 5.0 V. PCI signalling will conform to the 5.0 V rules. VDD3P_AGP[3:1] In Pass1, 3.3 V. In Pass2, these signals are absent. Lx_VLDT[y] HyperTransport I/O power. 1.2 V. Tsi301 HyperTransport to PCI User Manual *Notice: The information in this document is subject to change without notice...
  • Page 16 The resistor value should be equal to half of the differential impedance of the HyperTransport signals, which is 100 ohms +/- 10%. Note: The LDT_RREF_GND should not be connected to ground. Tsi301 HyperTransport to PCI User Manual *Notice: The information in this document is subject to change without notice...

  • Page 17: Chapter 3 Functional Operation

    Chapter 3 Functional Operation This chapter details the operation of the HyperTransport PCI Bridge chip. Notes Figure 3.1 HyperTransport PCI Bridge Block Diagram 3.1 HyperTransport Interface The HyperTransport PCI bridge HyperTransport interface consists of two identical link interfaces, each with a HyperTransport transmitter and receiver.
  • Page 18 NeedResp CSR fields to set minimum buffer allocations for each virtual channel. If retiring a data buffer to the pool would cause a virtual channel to fall below its allocation, that buffer is immediately re-allocated to the Tsi301 HyperTransport to PCI User Manual 3-20...
  • Page 19 • Broadcast request addresses are also decoded and accepted if they match a HyperTransport PCI Tsi301 HyperTransport to PCI User Manual 3-20 *Notice: The information in this document is subject to change without notice...
  • Page 20 64 KB where the bottom 10 bits are in the ranges 3B0h – 3BBh or 3C0h – 3DFh) which the HyperTransport PCI bridge accepts. Accepted RdSized requests result in IoRd requests on the PCI Tsi301 HyperTransport to PCI User Manual 3-20...
  • Page 21 In this case, packets are routed to the End of Chain (EOC) logic in the unconnected link interface. The EOC logic drops responses and posted Tsi301 HyperTransport to PCI User Manual 3-20...

  • Page 22: Outbound Transactions

    Outbound requests to PCI are handed to the PCI interface to be driven out to the bus. Write data comes from the Rx data buffers. Read data is returned from the bus and placed in the PCI Response Data Buffer. Tsi301 HyperTransport to PCI User Manual 3-20...

  • Page 23: Inbound Transactions

    Transport PCI bridge makes this determination with medium DEVSEL# timing. When configured as a 64-bit target at power up, the HyperTransport PCI bridge asserts P_ACK64_N in response to P_REQ64_N for requests it accepts. Tsi301 HyperTransport to PCI User Manual 3-20 *Notice: The information in this document is subject to change without notice...
  • Page 24 The HyperTransport PCI bridge supports a variety of prefetching options configured under CSR control using the Read Control CSR (62h:60h), however: Tsi301 HyperTransport to PCI User Manual 3-20 *Notice: The information in this document is subject to change without notice...
  • Page 25 Otherwise, the transaction is disconnected as soon as all data from the initial reads is returned to the PCI bus. Tsi301 HyperTransport to PCI User Manual 3-20 *Notice: The information in this document is subject to change without notice...

  • Page 26: Interrupt Generation

    The HyperTransport PCI bridge interrupt controller consists of four blocks of generic interrupts, four inter- rupts per block, and one set of special interrupts. In Pass2, the special interrupts are not available. Tsi301 HyperTransport to PCI User Manual 3-20 *Notice: The information in this document is subject to change without notice...

  • Page 27: Pci Arbiter

    Warm reset of the HyperTransport PCI bridge is caused by the assertion of L_RST_N while leaving L_POWER_OK asserted. Once asserted, L_RST_N must remain asserted for at least 1 s. Tsi301 HyperTransport to PCI User Manual 3-20 *Notice: The information in this document is subject to change without notice...

  • Page 28: Reset Configuration

    Reserved for API Networks. Must be tied to 0. intDbgEn P_AD[9] Reserved for API Networks. Must be tied to 0. Table 3.1 Reset Configuration Strappings Tsi301 HyperTransport to PCI User Manual 3-20 *Notice: The information in this document is subject to change without notice...
  • Page 29 Inbound reads are retired as their responses return from HyperTransport and the data dropped. Outbound operations Tsi301 HyperTransport to PCI User Manual 3-20...

  • Page 30: Error Handling

    HyperTransport link. These errors are not localizable to individual transactions, and all can bring down the link through sync flooding. Tsi301 HyperTransport to PCI User Manual 3-20 *Notice: The information in this document is subject to change without notice...
  • Page 31 In general, these errors are signaled to the PCI bus in the same way as in a standard PCI-PCI bridge. HyperTransport PCI bridge HyperTransport master error settings are described in Table 3.4. Tsi301 HyperTransport to PCI User Manual 3-20 *Notice: The information in this document is subject to change without notice...

  • Page 32: Pci Errors

    PCI master errors refers to errors detected by the HyperTransport PCI bridge when acting as a master on the PCI bus. Master and Target Abort are defined in the PCI Local Bus Specification, Revision 2.2. Tsi301 HyperTransport to PCI User Manual 3-20...

  • Page 33: Test Features

    Several features are included in the HyperTransport PCI bridge to facilitate testing of the chip. Supported test modes are listed in Table 3.7 and are described in the following sections. Tsi301 HyperTransport to PCI User Manual 3-20 *Notice: The information in this document is subject to change without notice...

  • Page 34: Signal Setting

    DBGOUT[16] which pulses once for every nandtree output transition. DBGCLK is reserved for use by API NetWorks. The following inputs/bidirects are not covered by the nandtree test: • TMODE3 • TMODE2 Tsi301 HyperTransport to PCI User Manual 3-20 *Notice: The information in this document is subject to change without notice...
  • Page 35 Internal logic continually recalculates and assigns impedance values. The internal logic generated values may be overwritten by CSRs. See the CSR impedance section for CSR configuration of HyperTransport impedance values. Tsi301 HyperTransport to PCI User Manual 3-20 *Notice: The information in this document is subject to change without notice...
  • Page 36 Tsi301 Notes Tsi301 HyperTransport to PCI User Manual 3-20 *Notice: The information in this document is subject to change without notice...

  • Page 37: Chapter 4 Clock And Timing Relationships

    Chapter 4 Clock and Timing Relationships The HyperTransport PCI bridge has only one PLL. The PCI clock (REFCLK_H/L input) is 1/4 of the core Notes clock or 1/2 of the core clock. See Table 4.1 for core clock frequencies. 4.1 Clock Dividers The PLL has three dividers for generating divided VCO clocks.

  • Page 38: Performance Information

    Latency from Rx Sync FIFO through the Rx buffers to the header presented at the HyperTransport receive interface = 2 * Core Clock Tsi301 HyperTransport to PCI User Manual *Notice: The information in this document is subject to change without notice...
  • Page 39 (1 * Core Clock) + (2 * LDT Rx Clock) = 12.5 ns Clock Alignment Factor (maximim) = (2 * Core Clock) + (1 * LDT Rx Clock) = 17.5 ns Tsi301 HyperTransport to PCI User Manual *Notice: The information in this document is subject to change without notice...
  • Page 40 = (4 * 15) + (7 * 7.5) + (1.75 * 2.5) = 60 + 52.5 + 4.4 = 116.9 ns Note: Data Alignment Factor and Clock Alignment Factor do not apply. Tsi301 HyperTransport to PCI User Manual *Notice: The information in this document is subject to change without notice...
  • Page 41 Tsi301 Notes Tsi301 HyperTransport to PCI User Manual *Notice: The information in this document is subject to change without notice...
  • Page 42 Tsi301 Notes Tsi301 HyperTransport to PCI User Manual *Notice: The information in this document is subject to change without notice...

  • Page 43: Chapter 5 Configuration Registers

    Chapter 5 Configuration Registers To select many of the many options available on the HyperTransport PCI bridge, you write to its configura- Notes tion registers. Usually, these registers are programmed during system initialization and are not accessed during normal operation. This section describes the mechanism used to access the HyperTransport PCI bridge configuration regis- ters as well as the location and functional details of each register.
  • Page 44 HyperTransport Error Control 0000h 6Dh-6Ch HyperTransport Rx Data BufferAllocation 1515h HyperTransport Transmit Control PCI Control 2 Table 5.1 Function 0 Configuration Registers<Emphasis> (Continued) Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 45 5.2.1 CSR Space Map The following figure is a map of HyperTransport PCI bridge CSR space. For Pass2, Link Frequency is a new CSR. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 46 Serial ROM (SROM) Interface 0 Rx Serial ROM (SROM) Interface 0 Tx Serial ROM (SROM) Interface 1 Figure 5.1 CSR Function 0 Space Map Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...

  • Page 47: Interrupt Register

    BBlock 1, Interrupt 1 ABh–AAh Block 1, Interrupt 2 ADh–ACh Block 1, Interrupt 3 AFh–AEh Table 5.2 Interrupt Controller Addresses and Vectors Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 48 3C9) as belonging on the secondary bus. The HyperTransport PCI bridge does not support VGA palette snooping. Always reads 0. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 49 0 = HyperTransport PCI bridge has not received an NXA error response on HyperTransport. 1 = HyperTransport PCI bridge has received an NXA error response on Hyper- Transport. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 50 15:8 Subclass of the device. 04h indicates a PCI bridge. Programming Interface of the device. 00 indicates a positive decode device. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 51 Primary Bus Number - PCI bus number of the HyperTransport chain on which the HyperTransport PCI bridge is located. Not persistent through warm reset. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 52 4 KB granularity. Not persistent through warm reset. Capability - indicates the size of I/O addresses supported by the device, 32 bits. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 53 Address - bits 31:20 of the base of the memory range. Bits 19:0 are assumed to 15:4 000h be 0, leading to a 1 MB granularity. Not persistent through warm reset. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 54 Address - bits 39:32 of the prefetchable memory range base. Memory accesses above 1012 GB will not be accepted regardless of the setting of this register. Not persistent through warm reset. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 55 Address - bits 39:32 of the prefetchable memory range limit. Memory accesses above 1012 GB will not be accepted regardless of the setting of this register. Not persistent through warm reset. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 56 Register - the HyperTransport spec requires that this be a read/write register. Its value is not used internally. Not persistent through warm reset. Interrupt Pin Offset 3Dh Bits Type Reset Description Reserved. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 57 (indicated by asserting the FATAL_ERR_N or NONFATAL_ERR_N interrupt pins, as enabled) for posted requests. Not persistent through warm reset. Reserved. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 58 Type Reset Description Pointer - pointer to the next capability block. It always points to 0, indicating no additional capability blocks. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 59 Nonposted requests result in nonexistent address (NXA) error responses. It may only be set, not cleared, by software. Not persistent through warm reset. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 60 000b = 8 bit 000b 001b = 16 bit 011b = 32 bit The HyperTransport PCI bridge only supports 8-bit links. Reserved. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 61 CRC Start Test - writing a 1 to this bit causes hardware to initiate a CRC test sequence on the link. When the test sequence has completed, hardware will clear the bit. Not persistent through warm reset. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 62 Reset Description Pass1 000b Major - major revision ID of the HyperTransport specification supported by the HyperTransport PCI bridge. Pass2 001b Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 63 HyperTransport PCI bridge. Pass2 00000b Note: In rev 1.0 of the Tsi301 HyperTransport to PCI bridge, the HyperTransport Revision ID is given as 0.17. However, Pass1 is also compliant to LDT I/O Specification Revision 1.0, with the exceptions that the Tsi301 does not support 2 and 4 bit interfaces or standard frequency control.
  • Page 64 Prefetch Enable - this bit enables prefetching for prefetchable read requests. If clear, no prefetching of any kind is performed. Not persistent through warm reset. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 65 Persistent through warm reset. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 66 SERR assertion is detected. This bit controls whether the interrupt is Fatal or Nonfatal: 0 = Nonfatal Enable 1 = Fatal Enable Not persistent through warm reset. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 67 Protocol Error, Fatal Enable - if asserted, detection of a protocol error causes a fatal interrupt. Not persistent through warm reset. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 68 Note: In Pass1, this CSR did not exist. Hardware behaved as if this CSR was always set to 1. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 69 Not persistent through warm reset. Tx Select - enables use of CSR transmit impedance values. Not persistent through warm reset. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 70 Tx Denom - denominator value for Tx HyperTransport/Clock ratio. Values come from SROM. Rx Denominator - denominator value for HyperTransport/Clock ratio. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 71 Serial ROM (SROM) Interface 1 Tx Offset 97h–94h Bits Type Reset Description Numerator - numerator value for Hyper- 31:0 Values come from SROM. Transport/Clock ratio. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 72 Vector - lower two bits of interrupt vector. Not persistent through warm reset. 00 = Interrupt 0 See Table 5.2 01 = Interrupt 1 10 = Interrupt 2 11 = Interrupt 3 Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 73 Not persistent through warm reset. Active - if 1, the given pin has an asserted (level) interrupt. Not persistent through warm reset. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 74 Block Enable - indicates that the current group is being used. Not persistent through warm reset. Block Vector - upper vector bits for Block 1 interrupts. Not persistent through 000000b warm reset. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 75 RCmd - response command buffer threshold. Not persistent through warm 19:16 reset. 23:20 RData - response data buffer threshold. Not persistent through warm reset. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 76 Bit 3:0 = Rx, 1 = Tx Bit 4:0 = Port 0, 1 = Port 1 Bit 5:0 = Core Debug, 1 = HyperTransport Debug Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 77 Note: The value of this register is captured from the CRC logic following detection of a CRC error. The value is unaffected by any form of reset. The value is undefined at power up. Tsi301 HyperTransport to PCI User Manual 5-36...
  • Page 78 The value is unaffected by any form of reset. The value is undefined at power up. Scratch Offset FFh–FCh Bits Type Reset Description Scratch - read/write software scratch register. Not persistent through warm 31:0 00000000h reset. Tsi301 HyperTransport to PCI User Manual 5-36 *Notice: The information in this document is subject to change without notice...
  • Page 79 CORPORATE HEADQUARTERS for SALES: for Tech Support: 6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 email: ssdhelp@idt.com San Jose, CA 95138 fax: 408-284-2775 phone: 408-284-8208 www.idt.com Document: 80D3000_MA001_02 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice.

  • Page 80: Corporate Headquarters

    Koto-ku, Tokyo 135-0061, Japan www.renesas.com/contact/ www.renesas.com Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.

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