Summary of Contents for Achronix Speedster7t 7t1500
- Page 1 Speedster7t Pin Connectivity User Guide (UG084) Speedster FPGAs Preliminary Data Preliminary Data...
- Page 2 Copyright © 2020 Achronix Semiconductor Corporation. All rights reserved. Achronix, Speedcore, Speedster, and ACE are trademarks of Achronix Semiconductor Corporation in the U.S. and/or other countries All other trademarks are the property of their respective owners. All specifications subject to change without notice.
- Page 3 Speedster7t Pin Connectivity User Guide (UG084) Table of Contents Chapter - 1: Introduction ............5 Chapter - 2: Pin List and Connection Guidelines .
- Page 4 Speedster7t Pin Connectivity User Guide (UG084) Preliminary Data...
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Page 5: Chapter - 1: Introduction
Speedster7t Pin Connectivity User Guide (UG084) Chapter - 1: Introduction This user guide lists each of the I/O pin groups available in the Speedster7t 7t1500 device, their functionality and recommended connection guidelines. Refer to the Speedster7t Power User Guide (UG087) for detailed description on the power/ground pins. -
Page 6: Chapter - 2: Pin List And Connection Guidelines
Speedster7t Pin Connectivity User Guide (UG084) Chapter - 2: Pin List and Connection Guidelines Pin Name Type Description and Connection Guidelines Clock I/O Interface CLKIO_NE_MSIO_[N/P] A group of two clock buffers in each corner of the device that can be CLKIO_NW_MSIO_[N/P] used either as a single pseudo differential clock I/O or two single- Input... - Page 7 Speedster7t Pin Connectivity User Guide (UG084) Pin Name Type Description and Connection Guidelines IEEE1149.1/1149.6 JTAG (10) Interface Dedicated test clock used to advance the TAP controller and clock in JTAG_TCK Input data on TDI input and out on TDO output. The maximum frequency for TCK is 50MHz.
- Page 8 Speedster7t Pin Connectivity User Guide (UG084) Pin Name Type Description and Connection Guidelines Active-high configuration done output signal indicating that bitstream loading completed successfully and that the device is ready to enter user mode. Once high, it stays asserted until the FCU is power cycled or reset for a re-initialization sequence.If a device configuration error occurs, the CONFIG_DONE output will remain low.
- Page 9 Speedster7t Pin Connectivity User Guide (UG084) Pin Name Type Description and Connection Guidelines When asserted high, this signal enables the JTAG interface pins to be directly connected to the JTAG controller in the SerDes PMA blocks allowing SerDes configuration, debug and performance monitoring directly from the JTAG interface.
- Page 10 Speedster7t Pin Connectivity User Guide (UG084) Pin Name Type Description and Connection Guidelines Active-high control bit to indicate to the CPU the clock cycles when the CPU_DQ bus has valid read-back data. Synchronous to FCU_CPU_DQ_VALID Output FCU_CPU_CLK. FCU_LOCK Output Active-high status bit to indicate the FCU lock/unlock status. FCU status bits showing the FCU state are shown in Table: FCU_STATUS_[1:0]...
- Page 11 Speedster7t Pin Connectivity User Guide (UG084) Pin Name Type Description and Connection Guidelines High-impedance output pin to probe/force internal analog nodes SRDS_N03_ATEST Output (13) during system bring-up. SerDes reference clock supplied from either a single-ended or differential external source. There is single differential pair for each lane.
- Page 12 Speedster7t Pin Connectivity User Guide (UG084) Pin Name Type Description and Connection Guidelines Miscellaneous Analog I/O pins used for test access and calibration. These pins are Input TS_AN_IO_[1:0] used for internal temperature calibration purposes only. Leave /Output unconnected. DDR4 DDR4_S0_A17 Output Address input to SDRAM (used in x4 configuration only).
- Page 13 Speedster7t Pin Connectivity User Guide (UG084) Pin Name Type Description and Connection Guidelines Active-low chip select signals to external SDRAM. All commands are masked when CS_n is registered HIGH. CS_N provides external DDR4_S0_CS_N_[3:0] Output rank selection on systems with multiple ranks. Input DDR4_S0_UDQS_N_[8:0] Data Mask and data bus inversion signals to SDRAM.
- Page 14 Speedster7t Pin Connectivity User Guide (UG084) Pin Name Type Description and Connection Guidelines GDDR6_[E/W][3:0]_C[1:0] Output Differential data clock inputs to memory. _SD_WCK_[N/P]_[1:0] Reference resistor for ZQ calibration. Nominal 240Ω to ground ±1% GDDR6_[E/W] [3:0]_RREF Input tolerance. GDDR6_[E/W] [3:0]_SD_CLK_[N Output Differential clock inputs to memory. GDDR6_[E/W] [3:0] Output Active-low Reset to GDDR6 memory.
- Page 15 Speedster7t Pin Connectivity User Guide (UG084) Pin Name Type Description and Connection Guidelines Table Notes Unused I/O can be left unconnected. Do not leave this/these pin(s) unconnected. Connect directly to the configuration controller. These pins should be AC coupled. Leave all unused transmit pins unconnected. Connect unused receive pins to GND via an optional 50Ω...
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Page 16: Chapter - 3: Supporting Tables
Speedster7t Pin Connectivity User Guide (UG084) Chapter - 3: Supporting Tables Table 1: FCU Configuration Clock Selection Based on SYSCLK_BYPASS and CLKSEL Pin Selections SYSCLK_BYPASS CFG_CLKSEL CFG_MODESEL[3:0] Configuration Clock 0000, 0001, 0010 On-chip Oscillator 1000 to 1101 0000, 0001, 0010,1000 to 1101 CPU clock 0011, 01XX CPU clock... - Page 17 Speedster7t Pin Connectivity User Guide (UG084) Configuration Mode CFG_MODESEL[3:0] Flash Dual ×1 1000 Flash Dual ×1 1001 Flash Quad ×1 1010 Flash Quad ×4 1011 Flash Octa ×1 1100 Flash Octa ×4 1101 JTAG Always active mode Table 4: FCU_STATUS Bits Indicating FCU State FCU_STATUS State fcu_locked...
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Page 18: Revision History
Chapter - 4: Revision History Version Date Description 24 May 2019 Initial Achronix release. Removed double prefixes from FCU, JTAG and TS pin names. Renamed UDQS_T signals in DDR4 interface to DM_DBI_UDQS_T and DM_DBI_UDQS_C signals to UDQS_C. 11 Jun 2019...