Embedian SMARC-FiMX6 User Manual
  1. Manuals
  2. Brands
  3. Embedian Manuals
  4. Motherboard
  5. SMARC-FiMX6
  6. User manual

Embedian SMARC-FiMX6 User Manual

Smarc computer on module
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
Embedian, Inc.
SMARC-FiMX6 Computer on Module User's Manual v.1.2
SMARC Computer on Module
Freescale i.MX6 Cortex A9
24bits Parallel LCD/LVDS/HDMI
4 x COM Ports
2 x SDHC
1 x USB Host 2.0, 1 x USB OTG
1 x 10/100/1000M Gigabit Ethernet
2 x CAN Bus, 2 x SPIs, 4 x I2Cs
1 x PCIe, 1 x SATA, 1 x MIPI
SMARC-FiMX6
1

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the SMARC-FiMX6 and is the answer not in the manual?

Questions and answers

Related Manuals for Embedian SMARC-FiMX6

Summary of Contents for Embedian SMARC-FiMX6

  • Page 1 1 x USB Host 2.0, 1 x USB OTG 1 x 10/100/1000M Gigabit Ethernet 2 x CAN Bus, 2 x SPIs, 4 x I2Cs 1 x PCIe, 1 x SATA, 1 x MIPI SMARC-FiMX6 SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 2 Embedian, Inc. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 3 Embedian, Inc. Revision History Revision Date Changes from Previous Revision 2014/11/20 Initial Release 2015/2/25 Documentation Wording Fixed and add section 2.1.8 and add Ethernet MAC EEPROM information SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 4 This EMBEDIAN product is warranted against defects in material and workmanship for the warranty period from the date of shipment. During the warranty period, EMBEDIAN will at its discretion, decide to repair or replace defective products. Within the warranty period, the repair of products is free of charge as long as warranty conditions are observed.
  • Page 5 Embedian, Inc. EMBEDIAN will not be responsible for any defects or damages to other products not supplied by EMBEDIAN that are caused by a faulty EMBEDIAN product. Technical Support Technicians and engineers from EMBEDIAN and/or its subsidiaries and official distributors are available for technical support. We are committed to making our product easy to use and will help you use our products in your systems.

  • Page 6: Table Of Contents

      CHAPTER 3 CONNECTOR PINOUT ....................116   3.1 SMARC-FIMX6 CONNECTOR PIN MAPPING ................116   CHAPTER 4 POWER CONTROL SIGNALS BETWEEN SMARC-FIMX6 MODULE AND CARRIER147   4.1 SMARC-FIMX6 MODULE POWER ....................147   4.2 POWER SIGNALS .......................... 152  ...
  • Page 7 Embedian, Inc. Using this Manual This guide provides information about the Embedian SMARC-FiMX6 for Freescale i.MX6 embedded SMARC core module family. Conventions used in this guide This table describes the typographic conventions used in this guide: This Convention Is used for...
  • Page 8 Embedian, Inc. manual and related documentation for additional information. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...

  • Page 9: Chapter 1 Introduction

    This Chapter gives background information on the SMARC-FiMX6 Section include：  Features and Functionality  Module Variant  Block diagram  Software Support / Hardware Abstraction  Module Variant  Document and Standard References SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 10 Computer-On-Module with Freescale i.MX6 processor and offers a wide range of processor scalability with single, dual and quadcore processors. The X86 alike interfacing of SMARC-FiMX6 allows an easy integration in any kind of application. The module connector has 314 edge fingers that mate with a low profile 314 pin 0.5mm pitch right angle connector (this connector is sometimes identified...
  • Page 11 3.3V or 1.8V module IO support  Note1: SMARC-FiMX6-S (solo core) only has 512MB DDR3 on board SMARC-FiMX6-U (dual lite core) only has 1GB DDR3 memory on board (no 2GB option for this variant.) SMARC-FiMX6 Computer on Module User’s Manual v.1.2...

  • Page 12: Module Variant

    Embedian, Inc. 1.2 Module Variant The SMARC-FiMX6 module is available with various options based on processors in this family from Freescale, DDR3 memory configuration, voltage rail of VDDIO and operating temperature ranges. “S” (solo core running up to 1GHz) “U” (dual lite core running up to 1GHz) “D”...

  • Page 13: Block Diagram

    1.3 Block Diagram following diagram illustrates system organization SMARC-FiMX6. Arrows indicate direction of control and not necessarily signal flow. Figure 1: SMARC-FiMX6 Block Diagram Details for this diagram will be explained in the following chapters. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...

  • Page 14: Software Support / Hardware Abstraction

    (Board Support Package). The first SMARC-FiMX6 BSP targets Linux (Ubuntu 14.04 LTS and Yocto Project) and Android support. BSPs for other operating systems are planned. Check with your Embedian contact for the latest BSPs. This manual goes into a lot of detail on I/O particulars – information is provided on exactly how the various SMARC edge fingers tie into the Freescale i.MX6...
  • Page 15 1.5.3. Embedian Documents The following documents are listed for reference. The Module schematic is not usually available outside of Embedian, without special permission. The other schematics will be available. Contact your Embedian representative for more information. The SMARC Evaluation Carrier Board Schematic is particularly useful as an example of the implementation of various interfaces on a Carrier board.
  • Page 16 Embedian Linux BSP for SMARC-FiMX6 Module  Embedian Android BSP for SMARC-FiMX6 Module  Embedian Linux BSP User’s Guide  Embedian Android BSP User’s Guide 1.5.8. Freescale Design Network  SABRE  Wandboard  Nucleus  SMARC-FiMX6 Computer on Module User’s Manual v.1.2...

  • Page 17: Chapter 2 Specifications

    Embedian, Inc. Specifications This Chapter provides SMARC-FiMX6 specifications. Section include：  SMARC-FiMX6 General Functions SMARC-FiMX6 Debug   Mechanical Specifications  Electrical Specification  Environment Specification SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 18 Embedian, Inc. Chapter 2 Specifications 2.1 SMARC-FiMX6 General Functions 2.1.1. SMARC-FiMX6 Feature Set This section lists the complete feature set supported by the SMARC-FiMX6 module. SMARC Feature SMARC SMARC-FiMX6 SMARC-FiMX6 Specification Specification Feature Support Feature Support Maximum Number Instances Possible...
  • Page 19 2. Dual channel LVDS interface: 2 x 18 bpp OR 2 x 24 bpp (up to 170 MHz pixel clock e.g 1600x1200 @ 60 Hz + 35% blanking). 2.1.2. Form Factor module complies with General SMARC-FiMX6 SMARC Specification module size requirements in an 82mm x 50mm form factor. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 20 Embedian, Inc. 2.1.3. CPU The SMARC-FiMX6 implements Freescale’s i.MX6 ARM processor. Freescale CPU i.MX6 Solo i.MX6 DualLite i.MX6 Dual i.MX6 Quad Cores Note1 Clock 1GHz 1GHz 1GHz 1GHz Memory Speed DDR3-400 DDR3-400 DDR3-533 DDR3-533 Memory Bus 32-bit 64-bit 64-bit 64-bit...
  • Page 21 The following table shows the available options. SMARC Variants i.MX6 Solo i.MX6 DualLite i.MX6 Dual i.MX6 Quad 512MB DDR3 1GB DDR3 2GB DDR3 Check with your Embedian contact or on the Embedian web site for updated information. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 22 Encode: H.264 BP/CBP H.263 V2 MPEG-4 SP MPEG-2 MJPEG Baseline Hardware Accelerated Video Decode: MPEG2 MP/HP MPEG4/Xvid SP/ASP H.264 BP/MP/HP H.264 MVC BP/MP/HP H.263 V2 DivX v3/4/5/6 VC-1 SP/MP/AP MJPEG Baseline VP6/VebM VP8 SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 23 Embedian, Inc. 2.1.6. Onboard Storage The SMARC-FiMX6 module supports a 8GB eMMC flash memory device, 4MB SPI NOR flash and a 32Kb I2C serial EEPROM on the Module I2C_PM (I2C0) bus. The device used is an On Semiconductor 24C32 equivalent. The Module serial EEPROM is intended to retain Module parameter information, including a module serial number.
  • Page 24 170 MHz (e.g. UXGA 1600x1200 @ 60 Hz with 35% blanking). To use the split mode, you need a display supporting the dual channel LVDS mode in order to receive odd and even pixel data! SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 25 1.8V I/O. The voltage swing may be used directly with 1.8V capable Carrier Board LVDS transmitters, such as TI DS90C185. The following figure shows the parallel LCD block diagram. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 26 Red is LCD_D[23:16]; Blue is LCD_D[15:8] and Green is LCD_D[7:0]. For 24 bit implementations, all bits are used. For 18 bit implementations, in SMARC, the least significant bits (Red LCD_D[17:16], Green LCD_D[9:8], Blue LCD_D[1:0]) are dropped. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 27 LCD_D12  G4  ALT0 S106 IPU1_DISP0_DATA12 DISP0_DAT11__  LCD_D11  LCD_D11  G3  ALT0 S105 IPU1_DISP0_DATA11 ALT0 DISP0_DAT10__  S104 LCD_D10  LCD_D10  G2  IPU1_DISP0_DATA10 DISP0_DAT9__  LCD_D9  LCD_D9  G1  ALT0 S103 IPU1_DISP0_DATA09 DISP0_DAT8__  LCD_D8 (LSB) LCD_D8  G0  ALT0 S102 IPU1_DISP0_DATA08 SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 28 LCD_D5  B5  IPU1_DISP0_DATA05 DISP0_DAT4__  LCD_D4  LCD_D4  B4  ALT0 IPU1_DISP0_DATA04 DISP0_DAT3__  LCD_D3  LCD_D3  B3  ALT0 IPU1_DISP0_DATA03 DISP0_DAT2__  LCD_D2  LCD_D2  B2  ALT0 IPU1_DISP0_DATA02 ALT0 DISP0_DAT1__  LCD_D1  LCD_D1  B1  IPU1_DISP0_DATA01 DISP0_DAT0__  LCD_D0 (LSB) LCD_D0  B0  ALT0 IPU1_DISP0_DATA00 SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 29 For instance, to connect an 18 bit display, R0, R1, G0, G1, B0 and B1 will remain unused, and R2, G2 and B2 become the LSBs for this configuration. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 30 CMOS Horizontal Sync – high pulse indicates the VDD_IO start of a new horizontal display line LCD_VS Output CMOS Vertical Synch – high pulse indicates the start VDD_IO of a new display frame SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 31 Output CMOS Display backlight PWM control VDD_IO I2C_LCD_DAT Bi-Dir CMOS I2C data – to read LCD display EDID EEPROMs VDD_IO I2C_LCD_DK Output CMOS I2C clock – to read LCD display EDID EEPROMs VDD_IO SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 32 Embedian, Inc. 2.1.10 LVDS Interface The SMARC-FiMX6 implements two 18 / 24 bit single channel LVDS output stream (the other LVDS is defined on AFB) for the Primary displays. They can also be configured as an 18 / 24 bit dual channel LVDS directly out of the SMARC Module.
  • Page 33 Embedian, Inc. The following figure shows the LVDS LCD block diagram. Figure 3: SMARC-FiMX6 LVDS LCD Diagram SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 34 AFB_DIFF2‐  differential pairs 3 ALT0 LVDS1_TX3_P  AFB_DIFF4+ AFB_DIFF4+  LVDS1 LCD data ALT0 channel LVDS1_TX3_N  AFB_DIFF4‐ AFB_DIFF4‐  differential pairs 4 ALT0 LVDS1_CLK_P  AFB_DIFF3+ AFB_DIFF3+  LVDS1 LCD ALT0 differential clock pairs LVDS1_CLK_N  AFB_DIFF3‐ AFB_DIFF3‐  ALT0 SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 35 Digital Visual Interface (DVI) carrying digital video. The SMARC-FiMX6 provides HDMI connection directly from the Freescale® i.MX6 processor. Video data is provided through three differential TMDS data pairs (HDMI_D0± to HDMI_D2±) and one differential clock pair (HDMI_CLK±).
  • Page 36 Embedian, Inc. The following figure shows the HDMI block diagram. Figure 4: SMARC-FiMX6 HDMI Diagram SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 37 HDMI_CEC  HDMI_CEC  P107 HDMI Consumer Electronics Control 1 – wire peripheral control interface I2C Dedicate for HDMI  ALT4 KEY_ROW3__  P106 HDMI_CTRL_DAT HDMI_CTRL_DAT  I2C Data I2C2_SDA  KEY_COL3__  HDMI_CTRL_CLK HDMI_CTRL_CLK  I2C Clock  ALT4 P105 I2C2_SCL  SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 38 HDMI_HPD signal. There are a number of single chip devices on the market that perform ESD protection and control signal level shifting for HDMI interfaces. The Texas Instruments TPD12S016 is one such device. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 39 Embedian, Inc. 2.1.12 USB Interface The Embedian SMARC-FiMX6 module supports two USB ports (USB 0:1). Per the SMARC specification, the module supports a USB “On-The-Go” (OTG) port capable of functioning either as a client or host device, on the SMARC USB0 port. The SMARC-FiMX6 module also supports one additional USB2.0 host ports, on SMARC USB1.
  • Page 40 Embedian, Inc. USB interface signals are exposed on the SMARC-FiMX6 edge connector as shown below: Freescale i.MX6 CPU SMARC-FiMX6 Edge Net Names Note Golden Finger Ball Mode Pin Name Pin# Pin Name USB0 Port (OTG) USB_OTG_DP  USB0+  USB0+  USB0 port data pair USB_OTG_DN ...
  • Page 41 Further details may be found in Section 2.1.12.3 USBx_EN_OC# Discussion below. USB0_VBUS_DET Input USB VBUS USB host power detection, when this port is used as a device. USB0_OTG_ID Input CMOS USB OTG ID input, active high. 3.3V SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 42 1 microampere or less, at a 3.3V enable voltage level. 2) The Module drives USBx_EN_OC# low to disable the power delivery to the USBx device. 3) The Module floats USBx_EN_OC# to enable power delivery. The line is SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 43 In these cases, the USBx_EN_OC# pins may be left unused, or they may be used as USBx power enables, without making use of the over-current detect Module input feature. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 44 Embedian, Inc. The SMARC-FiMX6 Module USB power enable and over current indication logic implementation is shown in the following block diagram. There are 10k pull-up resistors on the Module on the SMARC USBx_EN_OC# lines. Outputs driving the USBx_EN_OC# lines are open-drain. The Carrier board USB power switch, if present, is enabled by USBx_EN_OC# after a device connection is detected on the DP/DM lines.
  • Page 45 No pull-up is required on the USB power switch Enable or OC# line on carrier board; they are tied together on the Carrier and fed to the Module USBx_EN_OC# pin. Figure 6. USB Power Distribution Implementation on Carrier SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 46 GBE0_MDI0± to GBE0_MDI3± plus control signals for link activity indicators. These signals can be used to connect to a 10/100/1000 BaseT RJ45 connector with integrated or external isolation magnetics on the carrier board. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 47 Embedian, Inc. This is diagrammed below. Figure 7: Gigabit Ethernet Connection from i.MX6 to Qualcomm Atheros AR8035 SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 48 RGMII_RXC__  RX_CLK  RGMII_RXC  ALT1 Reference clock RGMII_RXC  ALT1 RGMII_RX_CTL__ RX_DV  RGMII_RX_CTL Indicates both the RGMII_RX_CTL  receive data valid (RXDV) and receive error (RXER) functions per the RGMII specification. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 49 ALT1 The MAC transmits RGMII_TD2  data to the transceiver using this signal. ALT1 RGMII_TXC__  GTX_CLK  RGMII_TXC  Used to latch data RGMII_TXC  from the MAC into the PHY. 1000BASE-T: 125MHz 100BASE-TX: 25MHz 10BASE-T: 2.5MHz SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 50 Negative Channel 1 GbE_MDI2+  GBE_MDI2+  TRXP2  Differential Transmit/Receive Positive Channel 2 GbE_MDI2‐  GBE_MDI2‐  TRXN2  Differential Transmit/Receive Negative Channel 2 TRXP3  GbE_MDI3+  GBE_MDI3+  Differential Transmit/Receive Positive Channel 3 GbE_MDI3‐  GBE_MDI3‐  TRXN3  Differential Transmit/Receive Negative Channel 3 SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 51 Note: 470 Mbps (total for Tx and Rx) due to internal bus throughput limitations. The actual measured performance in optimized environment is up to 400 Mbps. For more information, consult Freescale’s Errata ERR004512. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 52 Blinks on Activity Could be able to sink 24mA or more Carrier LED current GBE_CTREF Output Reference Center-Tap reference voltage for GBE0 Carrier board Ethernet magnetic (not required by the Module GBE PHY) Voltage SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 53 Halo TG1G-S002NZRL 24-pin C~70 HP Auto-MDIX SOIC-W For industrial temperature (-40 C ~85 C) products. Vendor Package Cores Temp Configuration RB1-BA6BT9WA Integrated C~85 HP Auto-MDIX RJ45 Halo TG1G-E012NZRL 24-pin C~85 HP Auto-MDIX SOIC-W SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 54 Embedian, Inc. 2.1.14. PCIe Interface The SMARC-FiMX6 offers one PCI Express lane. The PCIe signals are routed from the Freescale® i.MX6 processor to the PCI Express port A of the SMARC-FiMX6 edge finger. These signals support PCI Express Gen. 2.0 interfaces at 5 Gb/s and are backward compatible to Gen.
  • Page 55 Embedian, Inc. PCI Express interface signals are exposed on the SMARC-FiMX6 edge connector as shown below: Freescale i.MX6 CPU SMARC-FiMX6 Edge Net Names Note Golden Finger Ball Mode Pin Name Pin# Pin Name PCI Express Port A SD1_CLK__  PCIE_A_RST#  PCIE_A_RST# ...
  • Page 56 Edge Golden Direction Type Description Finder Tolerance Signal Name PCIE_WAKE# Input CMOS 3.3V PCIe wake up interrupt to host – common to PCIe links A, B, C – pulled up or terminated on Module SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 57 Embedian, Inc. 2.1.15. SATA Interface The Freescale® i.MX6 Cortex A9 processor on the SMARC-FiMX6 supports one SATA port. The supported signals are coupled with 10nF capacitors and then routed to SMARC-FiMX6 edge finger per defined in SMARC specification. The SMARC-FiMX6 offers this SATA port on the MXM connector.
  • Page 58 Embedian, Inc. The following figure shows the SATA port A block diagram. Figure 9. SATA Block Diagram SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 59 Embedian, Inc. SATA interface signals are exposed on the SMARC-FiMX6 edge connector as shown below: Freescale i.MX6 CPU SMARC-FiMX6 Edge Net Names Note Golden Finger Ball Mode Pin Name Pin# Pin Name SATA SATA_RXP  SATA_RX+  SATA_RX+  Receive Input differential pair.
  • Page 60 SATA_RX- Series coupling caps is on the Module Caps is 0402 package 0.1uF SATA_ACT# Output CMOS Active low SATA activity indicator 3.3V It is able to sink 24mA or more Carrier LED current SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 61 The SMARC specification defines serial and parallel camera interface on the same pins. We can either implement it as serial or parallel camera interfaces. The camera interface on SMARC-FiMX6 is designed as serial interfaces on CSI1 pin groups that can support 4 lanes or 2 lanes. The CSI0 interface is not connected on edge golden finger connector.
  • Page 62 Embedian, Inc. The following figure shows the serial camera interface block diagram. Figure 10. MIPI/Serial Camera Interface Block Diagram SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 63 Embedian, Inc. MIPI/Serial Camera interface signals are exposed on the SMARC-FiMX6 edge connector as shown below: Freescale i.MX6 CPU SMARC-FiMX6 Edge Net Names Note Golden Finger Ball Mode Pin Name Pin# Pin Name MIPI/Serial Camera Interface NANDF_CS2__  CAM_MCK  CAM_MCK  ALT4 Master clock CCM_CLKO2 ...
  • Page 64 GND on module if module supports a parallel camera interface on SMARC CSI1 group. SMARC-FiMX6 supports serial camera interface only and hence we leave this pin floating. The CSI0 camera group is not used in SMARC-FiMX6, PCAM_ON_CS0# is also floating on module. 2.1.16.2. Camera I2C Support The I2C_CAM_ port is intended to support serial and parallel cameras.
  • Page 65 Finder Tolerance Signal Name CSI1_D[0:3]+ Input LVDS D-PHY CSI1 differential data inputs CSI1_D[0:3]- CSI1_CK+ Input LVDS D-PHY CSI1 differential clock inputs CSI1_CK- CAM_MCK Output CMOS Master clock output for CSI1 camera support VDD_IO SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 66 Embedian, Inc. 2.1.17. SD/SDMMC Interface SMARC-FiMX6 is configured to support three MMC controllers. One is used for internal 8-bit eMMC support, and the other two could be used for external SDHC/SDIO interfaces. The SMARC-FiMX6 module supports two 4bit SDIO interface, per the SMARC specification. From the definition of SMARC specification, one will be interfaced to SD/SDHC card or device, and the other could be interfaced to external eMMC flash.
  • Page 67 SD2_CMD__  SDIO_CMD  SDIO_CMD  ALT0 SDIO Command SD2_CMD  signal ALT5 ENET_TX_EN__  SDIO_CD#  SDIO_CD#  SDIO card detect GPIO1_IO28  ALT0 SD2_CLK__  SDIO_CK  SDIO_CK  SDIO Clock Signal SD2_CLK  ENET_TX_EN__  SDIO_PWR_EN  SDIO_PWREN  SD card power ALT5 GPIO1_IO28  enable SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 68 3. SDIO_WP and SDIO_CD# are 10k pull up to 3.3V on module. 4. If users would like to implement SDMMC interface as SD/SDIO, you can use other GPIOs for WP and CD# signals and use 10k pull-up resistors to 3.3V. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 69 Output CMOS 3.3V SD Card Power Enable Note: SD Cards are not typically available with a 1.8V I/O voltage. The Module SD Card I/O level is specified as 3.3V and not CMOS VDD_IO. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 70 The SMARC Module pin definition allows for an 8 bit eMMC interface. However, SMARC-FiMX6 a l l o w s 4 b i t eMMC interface on carrier board. There is an on-module 8 bit 8GB eMMC. Bothe the on-module and on-carrier eMMC be selected as the Boot Device –...
  • Page 71 The 4MB onboard SPI NOR flash uses the SPI0 interface with different chip select signal. The onboard SPI NOR flash on SMARC-FiMX6 is used as first stage bootloader device. The module will always boot up from SPI NOR...
  • Page 72 ALT0 KEY_COL1__  SPI1_DIN  SPI1_MISO  SPI1 Master Data ECSPI1_MISO  input (input to CPU, output from SPI device) KEY_ROW0__  SPI1_DO  SPI1_MOSI  ALT0 SPI1 Master Data ECSPI1_MOSI  output (output from CPU, input to SPI device) SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 73 SPI0 Master Clock output VDDIO SPI0_DIN Input CMOS SPI0 Master Data input (input to CPU, output VDDIO from SPI device) SPI0_DO Output CMOS SPI0 Master Data output (output from CPU, VDDIO input to SPI device) SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 74 SPI1 Master Clock output VDDIO SPI1_DIN Input CMOS SPI1 Master Data input (input to CPU, output VDDIO from SPI device) SPI1_DO Output CMOS SPI1 Master Data output (output from CPU, VDDIO input to SPI device) SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 75 I2S protocol is part of the protocols supported by the Freescale® i.MX6 Cortex A9 processor. The SSI supports up to 1.4 Mbps. I2S interface signals are exposed on the SMARC-FiMX6 golden finger edge connector as shown below: Freescale i.MX6 CPU...
  • Page 76 Left& Right audio synchronization clock VDDIO I2S0_SDOUT Output CMOS Digital audio Output VDDIO I2S0_SDIN Input CMOS Digital audio Input VDDIO I2S0_CK Bi-Dir CMOS Digital audio clock VDDIO I2S0_MCK Output CMOS Master clock output to Audio codecs VDDIO SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 77 Embedian, Inc. 2.1.20 SPDIF Interface SPDIF interface signals are exposed on the SMARC-FiMX6 golden finger edge connector as shown below: Freescale i.MX6 CPU SMARC-FiMX6 Net Names Note Edge Golden Finger Ball Mode Pin Name Pin# Pin Name ALT4 GPIO_17__  SPDIF_OUT ...
  • Page 78 Embedian, Inc. 2.1.21. Asynchronous Serial Port The SMARC-FiMX6 module supports four UARTs (SER0:3). UART SER0 and SER2 support flow control signals (RTS#, CTS#). UART SER1 and SER3 do not support flow control (TX, RX only). When working with software, SER 3 is used for SMARC-FiMX6 debugging console port.
  • Page 79 Clear to Send UART4_CTS_B  handshake line for SER2 SER3 Port (Debugging Port) CSI0_DAT14__  SER3_TX  SER3_TX  ALT3 P140 Asynchronous UART5_TX_DATA  serial port data out ALT3 CSI0_DAT15__  P141 SER3_RX  SER3_RX  Asynchronous UART5_RX_DATA  serial port data in  SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 80 SER[0]_CTS# Input CMOS Clear to Send handshake line for SER0 VDDIO SER[2]_RTS# Output CMOS Request to Send handshake line for SER2 VDDIO SER[2]_CTS# Input CMOS Clear to Send handshake line for SER2 VDDIO SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 81 SMARC specification: PM (Power Management), LCD (Liquid Crystal Display), GP (General Purpose), CAM (Camera) and HDMI. SMARC-FiMX6 defines all of the five I2C buses and supports multiple masters and slaves in fast mode (400 KHz operation). The I2C_PM is implemented directly from Freescale i.MX6 I2C1 interfaces.
  • Page 82 (for parallel and LVDS LCD,) I2C_CAM I2C32 Serial / Parallel General Purpose CMOS camera VDDIO I2C_HDMI I2C2 Dedicated to HDMI CMOS VDDIO Note: The 2.2k pull-up resistors for I2C_SCL and I2C_SDA signals are on module. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 83 The Ball of I2C3_SCL is F21 and is configured as ALT6, and pin name is EIM_D17__I2C3_SCL. The Ball of I2C3_SDA is D24 and is configured as ALT6 as well, and the pin name is EIM_D18__I2C3_SDA. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 84 Embedian, Inc. There are three I2C devices on the SMARC-FiMX6 Module and two of them are on the I2C_PM (I2C1) bus and are operated at 1.8V. The other one is on I2C3 bus. Those devices and their address details are listed in the following...
  • Page 85 The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a high level of security. The SMARC-FiMX6 module supports two CAN bus interfaces. CAN interface signals are exposed on the SMARC golden finger edge connector as shown below: Freescale i.MX6 CPU...
  • Page 86 Input CMOS CAN0 Receive input VDDIO 2.1.23.2. CAN1 BUS Signals Edge Golden Direction Type Description Finder Tolerance Signal Name CAN1_TX Output CMOS CAN1 Transmit output VDDIO CAN1_RX Input CMOS CAN1 Receive input VDDIO SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 87 Embedian, Inc. 2.1.24. GPIOs The SMARC-FiMX6 module supports 12 GPIOs, per the SMARC specification. Specific alternate functions are assigned to some GPIOs such as PWM / Tachometer capability, Camera support, CAN Error Signaling and HD Audio reset. All pins are capable of bi-directional operation. A default direction of operation is assigned, with half of them (GPIO0 –...
  • Page 88 ALT5 P116 CAN0 Error GPIO2_IO04  signal, active low input NANDF_D0__  GPIO9/CAN1_ERR#  GPIO9  ALT5 P117 CAN1 Error GPIO2_IO00  signal, active low input NANDF_D5__  GPIO10  GPIO10  ALT5 P118 GPIO2_IO05  NANDF_ALE__  GPIO11  GPIO11  ALT5 P119 GPIO6_IO08  SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 89 PCAM_FLD (Field) signal input VDDIO Input CMOS GPIO8/CAN0_ERR#  CAN0 Error signal, active low input VDDIO Input CMOS GPIO9/CAN1_ERR#  CAN1 Error signal, active low input VDDIO Input CMOS GPIO10  VDDIO Input CMOS GPIO11  VDDIO SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 90 Embedian, Inc. 2.1.25. Watchdog Timer Interface i.MX6 features an internal WDT. Embedian’s Linux kernel enables the internal i.MX6 WDT and makes this functionality available to users through the standard Linux Watchdog API. A description of the API is available following the link below: http://www.kernel.org/doc/Documentation/watchdog/watchdog-api.txt...
  • Page 91 Embedian, Inc. 2.1.26. JTAG Figure 14 shows the SMARC-FiMX6 JTAG connectors location and pin out. Figure 14: JTAG Connector Location and Pinout JTAG functions for CPU debug and test are implemented on separate small form factor connector (CN3: JST SM10B-SRSS-TB, 1mm pitch R/A SMD Header).
  • Page 92 Ground  Ground 2.1.27. Boot ID EEPROM The SMARC-FiMX6 module includes an I2C serial EEPROM available on the I2C_PM bus. An On Semiconductor 24C32 or equivalent EEPROM is used in the module. The device operates at 1.8V. The Module serial EEPROM is placed at I2C slave addresses A2 A1 A0 set to 0 (I2C slave address 50 hex, 7 bit address format or A0 / A1 hex, 8 bit format) (for I2C EEPROMs, address bits A6 A5 A4 A3 are set to binary 0101 convention).
  • Page 93 4  Header  MSB 0xEE3355AA LSB 8  Board Name  Name for Board in ASCII “SMCMXQ1G” = Embedian SMARC-FiMX6 Computer on Module with Quad Core and 1GB DDR3 Configuration “SMCMXQ2G” = Embedian SMARC-FiMX6 Computer on Module with Quad Core and 2GB DDR3 Configuration “SMCMXD1G”...

  • Page 94: Smarc-Fimx6 Debug

    Out of these 4 serial ports, SER3 is set as the serial debug port use for i.MX6 from Embedian. Users can change to any port they want to. SER3 is exposed (along with all other serial ports available on the module) in the SMARC-FiMX6 Evaluation Carrier.
  • Page 95 Embedian, Inc. 2.3.4. Mechanical Drawings The mechanical information is shown in Figure 15: SMARC-FiMX6 Mechanical Drawings (Top View) and Figure 16: SMARC-FiMX6 Mechanical Drawings (Bottom View)) Figure 15. SMARC-FiMX6 Mechanical Drawings (Top View) SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 96 Embedian, Inc. Figure 16. SMARC-FiMX6 Mechanical Drawings (Bottom View) The figure on the following page details the 82mm x 50mm Module mechanical attributes, including the pin numbering and edge finger pattern. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 97 Embedian, Inc. Figure 17: SMARC-FiMX6 Module Mechanical Outline SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 98 Embedian, Inc. Top side major component (IC and Connector) information is shown in Figure 18: SMARC-FiMX6 Top side components. Figure 18. SMARC-FiMX6 Top Side Components SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 99 Embedian, Inc. Bottom side major component (IC and Connector) information is shown in Figure 19: SMARC-FiMX6 Bottom side components. Figure 19. SMARC-FiMX6 Bottom Side Components SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 100 Embedian, Inc. SMARC-FiMX6 height information from Carrier board Top side to tallest Module component is shown in Figure 20: SMARC-FiMX6 Minimum “Z” Height: Figure 20. SMARC-FiMX6 Minimum “Z” Height The SMARC connector board-to-board stack heights that are available may result in the use of non-standard spacer lengths. The board-to-board stack heights available include 1.5mm, 2.7mm and 5mm.
  • Page 101 2.3.6. Module Assembly Hardware The SMARC-FiMX6 module is attached to the carrier with four M2.5 screws. A 4mm length screw is usually used. The attachment holes are located on the corners of the module. Attachment holes have a 6mm diameter pad, 2.7...
  • Page 102 Embedian, Inc. mm dia drill hole as shown Figure 15: SMARC-FiMX6 Mechanical Drawings (Top View) 2.3.7. Carrier Board Standoffs Figure 22: Screw Fixation Standoffs secured to the Carrier board are expected. The standoffs are to be used with M2.5 hardware. Most implementations will use Carrier board standoffs that have M2.5 threads (as opposed to clearance holes).
  • Page 103 CM. Their use is common in the industry. The standoff OD and Carrier PCB hole size requirements are different from the PEM SMTSO standoffs described above. 2.3.8. Carrier Connector Figure 23: MXM3 Carrier Connector SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 104 1.56mm 4.0mm 10 u-in Black Speedtech B35P101-02012-H 1.56mm 4.0mm 10 u-in Speedtech B35P101-02113-H 1.56mm 4.0mm 15 u-in Black Speedtech B35P101-02013-H 1.56mm 4.0mm 15 u-in Aces 91781-314 2 8-001 2.7mm 5.2mm 3 u-in Black SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 105 2. The vendor drawings for the connectors listed above show a PCB footprint pattern for use with an MXM3 graphics card. This footprint, and the associated pin numbering, is not suitable for SMARC use. The SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 106 SMARC Module. The heat spreader plate ‘Y’ dimension is deliberately set at 42mm and not 50mm, to allow the plate to clear the SMARC MXM3 connector. The plate is shown in the figures below. Figure 24: Heat Spreader SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 107 Dimensions in the figure above are in millimeters. “TIM” stands for “Thermal Interface Material”. The TIM takes up the small gap between the SOC top and the Module - facing side of the heat spreader. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 108 M3 threaded holes the attachment of a heat sink to the heat spreader, or to allow the heat spreader to be secured to a chassis wall that can serve as a heat sink. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...

  • Page 109: Electrical Specifications

    Embedian, Inc. 2.4 Electrical Specifications 2.4.1. Supply Voltage The SMARC-FiMX6 module operates over an input voltage range of 3.0V to 5.25V. Power is provided from the carrier through 10 power pins as defined by the SMARC specification. A single 5V DC input is recommended.
  • Page 110 The power consumption values listed in this document were measured under a controlled environment. The hardware used for testing includes an SMARC-FiMX6 module, carrier board for SMARC ARM, TFT monitor, micro-SD card and USB keyboard. The carrier board was powered externally by a power supply unit so that it does not influence the power consumption value that is measured for the module.
  • Page 111 P/N: SMARC-FiMX6-U Freescale i.MX6 Cortex A9 1GHz Dual Lite Core 512KB L2 Cache Memory Size Operating System Ubuntu 14.04 Power States Desktop Idle 100% workload Max. power consumption Power Consumption 0.26A/1.3W 0.44A/2.2W 0.66A/3.3W (Amp/Watts) SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 112 P/N: SMARC-FiMX6-Q-1G Freescale i.MX6 Cortex A9 1GHz Quad Core 1MB L2 Cache Memory Size Operating System Ubuntu 14.04 Power States Desktop Idle 100% workload Max. power consumption Power Consumption 0.3A/1.5W 0.72A/3.6W 0.92A/4.6W (Amp/Watts) SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 113 P/N: SMARC-FiMX6-Q-2G Freescale i.MX6 Cortex A9 1GHz Quad Core 1MB L2 Cache Memory Size Operating System Ubuntu 14.04 Power States Desktop Idle 100% workload Max. power consumption Power Consumption 0.3A/1.5W 0.74A/3.7W 0.94A/4.7W (Amp/Watts) SMARC-FiMX6 Computer on Module User’s Manual v.1.2...

  • Page 114: Environmental Specifications

    Embedian, Inc. 2.5 Environmental Specifications 2.5.1. Operating Temperature The SMARC-FiMX6 module operates from 0°C to 60°C air temperature, without a passive heat sink arrangement. Industrial temperature (-40 C is also available with different part number SMARC-FiMX6-I). 2.5.2. Humidity Operating: 10% to 90% RH (non-condensing).

  • Page 115: Chapter 3 Connector Pinout

    Embedian, Inc. Connector PinOut This Chapter gives detail pinout of SMARC-FiMX6 golden finger edge connector. Section include：  SMARC-FiMX6 Connector Pin Mapping SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 116 The Secondary (Bottom) side faces the Carrier board when a normal or standard Carrier connector is used. The SMARC-FiMX6 module pins are deliberately numbered as P1 – P156 and S1 – S158 for clarity and to differentiate the SMARC Module from MXM3 graphics modules, which use the same connector but use the pins for very different functions.
  • Page 117 Embedian, Inc. Figure 26: SMARC-FiMX6 edge finger secondary pins The next tables describe each pin, its properties, and its use on the module and development board. The “SMARC Edge Finger” column shows the connection of the signals defined in the SMARC specification. The “Freescale i.MX6 CPU” column shows the connection of the CPU signals on the module.
  • Page 118 Ground CSI1_D2+ /  CSI_D2P  CSI1 differential PCAM_D6  data inputs CSI1_D2‐ /  CSI_D2M  CSI1 differential PCAM_D7  data inputs GND  Ground CSI1_D3+ /  CSI_D3P  CSI1 differential PCAM_D8  data inputs CSI1_D3‐ /  CSI_D3M  CSI1 differential PCAM_D9  data inputs GND  Ground SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 119 Transmit/Receive Positive Channel 2 GbE_LINK_ACT#  Link / Activity Indication LED Driven low on Link (10, 100 or 1000 mbps) Blinks on Activity Could be able to sink 24mA or more Carrier LED current SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 120 Transmit/Receive Positive Channel 1 GbE_CTREF  Qualcomm AR8035 Center tap reference voltage for GBE Carrier board Ethernet magnetic GbE_MDI0‐  Qualcomm AR8035 Differential Transmit/Receive Negative Channel 0 GbE_MDI0+  Qualcomm AR8035: Differential Transmit/Receive Positive Channel 0 SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 121 SPI0 Master Chip GPIO3_IO24  Select 0 output, reserved for on-module NOR flash SPI0_CK  ALT2 CSI0_DAT8__  SPI0 Master ECSPI2_SCLK  Clock output SPI0_DIN  CSI0_DAT10__E ALT2 SPI0 Master Data CSPI2_MISO  input (input to CPU, output from SPI device) SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 122 Clock output SPI1_DIN  KEY_COL1__  ALT0 SPI1 Master Data ECSPI1_MISO  input (input to CPU, output from SPI device) SPI1_DO  ALT0 KEY_ROW0__  SPI1 Master Data ECSPI1_MOSI  output (output from CPU, input to SPI device) GND  Ground SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 123 USB0_VBUS_DET  E9 Turn on  USB host power USB_OTG_VBUS detection, when this port is used as a device USB0_OTG_ID  ENET_RX_ER__ ALT0 USB OTG ID USB_OTG_ID  input, active high USB1+  USB_H1_DP  Differential USB0 data pair USB1‐  USB_H1_DN  SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 124 PCIE_A_RST#  ALT5 SD1_CLK__  Reset Signal for GPIO1_IO20  external devices. PCIE_C_CKREQ#  Not used PCIE_B_CKREQ#  Not used PCIE_A_CKREQ#  A21 SD1_DAT0__  ALT5 PCIe Port A GPIO1_IO16  clock request input GND  Ground PCIE_C_REFCK+  Not used SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 125 0 PCIE_A_TX‐  PCIE_TXM  Differential PCIe Link A transmit data pair 0 GND  Ground HDMI_D2+  HDMI_D2P  TMDS / HDMI data differential pair 2 HDMI_D2‐  HDMI_D2M  TMDS / HDMI data differential pair 2 SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 126 HDMI_CK‐  HDMI_CLKM  HDMI differential clock output pair P103 GND  Ground HDMI_HPD  HDMI_HPD  P104 HDMI Hot Plug Detect input HDMI_CTRL_CK  KEY_COL3__  P105 ALT4 I2C Clock I2C2_SCL  P106 HDMI_CTRL_DAT  T7 ALT4 KEY_ROW3__  I2C Data I2C2_SDA  SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 127 GPIO6_IO07  signal input PCAM_FLD  GPIO8 /  NANDF_D4__  P116 ALT5 CAN0 Error signal, GPIO2_IO04  active low input CAN0_ERR#  P117 GPIO9 /  ALT5 NANDF_D0__  CAN1 Error signal, GPIO2_IO00  active low input CAN1_ERR#  GPIO10  NANDF_D5__  P118 ALT5 GPIO2_IO05  SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 128 Module. Driven by OD part on Carrier. BOOT_SEL2#  P125 SYSBOOT and Line De-multiplexer Logic Pulled up on Module. Driven by OD part on Carrier. RESET_OUT#  P126 General purpose reset output to Carrier board. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 129 ALT4 EIM_D20__  Clear to Send UART1_CTS_B  handshake line for SER0 GND  P133 Ground SER1_TX  EIM_D26__  P134 ALT4 Asynchronous UART2_TX_DATA serial port data out SER1_RX  EIM_D27__  P135 ALT4 Asynchronous UART2_RX_DATA serial port data in  SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 130 P146 CAN1_RX  ALT0 KEY_ROW4__  CAN1 Receive FLEXCAN2_RX  input VDD_IN  P147 Power in VDD_IN  P148 Power in P149 VDD_IN  Power in VDD_IN  P150 Power in VDD_IN  P151 Power in VDD_IN  P152 Power in SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 131 Embedian, Inc. SMARC Edge Finger Freescale i.MX6 CPU Type Description Pin Name  Signal Name Pin# Ball Mode P153 VDD_IN  Power in P154 VDD_IN  Power in VDD_IN  P155 Power in VDD_IN  P156 Power in SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 132 Camera I2C bus data CSI0_CK+ /  Not used PCAM_D10  CSI0_CK‐ /  Not used PCAM_D11  GND  Ground CSI0_D0+ /  Not used PCAM_D12  CSI0_D0‐ /  Not used PCAM_D13  GND  Ground CSI0_D1+ /  Not used PCAM_D14  CSI0_D1‐ /  Not used PCAM_D15  GND  Ground SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 133 Ground SDMMC_D0  ALT0 SD3_DAT0__  4-bit eMMC Data 0 SD3_DATA0  SDMMC_D1  ALT0 SD3_DAT1__  4-bit eMMC Data 1 SD3_DATA1  SDMMC_D2  SD3_DAT2__  ALT0 4-bit eMMC Data 2  SD3_DATA2  SDMMC_D3  SD3_DAT3__  ALT0 4-bit eMMC Data 3  SD3_DATA3  SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 134 CSI0_DAT5__  Digital audio Output AUD3_TXD  I2S0_SDIN  CSI0_DAT7__  ALT4 Digital audio Input AUD3_RXD  I2S0_CK  CSI0_DAT4__  ALT4 Digital audio clock AUD3_TXC  I2S1_LRCK  Not used I2S1_SDOUT  Not used I2S1_SDIN  Not used I2S1_CK  Not used GND  Ground SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 135 GPIO_3__  Serial ATA Led. GPIO1_IO03  Open collector output pin driven during SATA command activity. AFB8_PTIO  Not used AFB9_PTIO  Not used PCAM_ON_CSI0#  Not used PCAM_ON_CSI1#  Not used SPDIF_OUT  ALT4 GPIO_17__  Digital Audio Out SPDIF_OUT  SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 136 3 AFB_DIFF2‐  LVDS1_TX2_N  ALT0 LVDS1 LCD data channel differential pairs 3 GND  Ground AFB_DIFF3+  LVDS1_CLK_P  ALT0 LVDS1 LCD differential clock pairs AFB_DIFF3‐  LVDS1_CLK_N  ALT0 LVDS1 LCD differential clock pairs GND  Ground SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 137 Ground PCIE_C_TX+  Not used PCIE_C_TX‐  Not used GND  Ground PCIE_B_REFCK+  Not used PCIE_B_REFCK‐  Not used GND  Ground PCIE_B_RX+  Not used PCIE_B_RX‐  Not used GND  Ground PCIE_B_TX+  Not used PCIE_B_TX‐  Not used GND  Ground SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 138 LS bits (D0, D1) not LCD_D3  ALT0 DISP0_DAT3__  connected IPU1_DISP0_DATA03  LCD_D4  ALT0 DISP0_DAT4__  IPU1_DISP0_DATA04  LCD_D5  DISP0_DAT5__  ALT0 IPU1_DISP0_DATA05  LCD_D6  DISP0_DAT6__  ALT0 IPU1_DISP0_DATA06  S100 LCD_D7  ALT0 DISP0_DAT7__  IPU1_DISP0_DATA07  GND  S101 Ground SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 139 (D8, D9) not LCD_D11  DISP0_DAT11__  S105 ALT0 connected IPU1_DISP0_DATA11 LCD_D12  DISP0_DAT12__  S106 ALT0 IPU1_DISP0_DATA12 S107 LCD_D13  ALT0 DISP0_DAT13__  IPU1_DISP0_DATA13 LCD_D14  DISP0_DAT14__  S108 ALT0 IPU1_DISP0_DATA14 LCD_D15  DISP0_DAT15__  S109 ALT0 IPU1_DISP0_DATA15 GND  S110 Ground SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 140 DI0_PIN3__  Vertical Sync- IPU1_DI0_PIN03  high pulse indicates the start of a new display frame S122 LCD_HS  ALT0 DI0_PIN2__  Horizontal Sync - IPU1_DI0_PIN02  high pulse indicates the start of a new horizontal display line SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 141 LVDS0 LCD data channel differential pairs 3 LVDS0_TX2_N  LVDS2‐  ALT0 S132 LVDS0 LCD data channel differential pairs 3 ALT5 S133 LCD_VDD_EN  High enables panel GPIO_2__ GPIO1_IO02 LVDS_CK+  LVDS0_CLK_P  S134 ALT0 LVDS0 LCD differential clock pairs SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 142 LCD_DUAL_PCK  Not used S142 GND  S143 Ground RSVD / EDP_HPD  Not used S144 S145 WDT_TIME_OUT#  ALT1 GPIO_9__ Watchdog-Timer WDOG1_B Output PCIE_WAKE#  SD1_DAT2__  S146 ALT5 PCI Express Wake GPIO1_IO19  Event: Sideband wake signal asserted by components requesting wakeup. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 143 Sleep button or Carrier logic. Carrier to float the line in in-active state. Active low, level sensitive. Should be de-bounced on the Module. Pulled up on Module. Driven by OD part on Carrier. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 144 Pulled up on Module. Driven by OD part on Carrier. CHARGER_PRSNT#  S152 CARRIER_STBY#  S153 ALT3 GPIO_18__ The Module shall GPIO7_IO13 drive this signal low when the system is in a standby power state SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 145 Pulled up on Module. Driven by OD part on Carrier. VDD_IO_SEL#  S158 If the Carrier supports only 1.8V I/O, then the Carrier shall tie the VDD_IO_SEL# pin directly to GND. Otherwise floating this pin. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...

  • Page 146: Smarc-Fimx6 Module Power

    This Chapter points out the handshaking rule between SMARC module and carrier. Section include：  SMARC-FiMX6 Module Power  Power Signals  Power Flow and Control Signals Block Diagram Power States   Power Sequences  Terminations  Boot Select SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 147 4.1 SMARC-FiMX6 Module Power 4.1.1. Input Voltage / Main Power Rail The allowable Module DC input voltage range for SMARC-FiMX6 is from 3.0V to 5.25V. This voltage is brought in on the VDD_IN pins and returned through the numerous GND pins on the connector. A single 5V DC input is recommended if device is not operated by battery.
  • Page 148 2.0V to 3.25V. The VDD_RTC rail is sourced from a Carrier based Lithium cell, or it may be left open if the RTC backup functions are not required. SMARC-FiMX6 module is able to boot without a VDD_RTC voltage source.
  • Page 149 1.8V I/O, then the Carrier will tie the VDD_IO_SEL# pin directly to GND. If the Carrier supports only 3.3V VDD_IO, Carriers will float the signal for 3.3V. 3.3V SMARC-FiMX6 will not power up if module senses a 1.8V VDD_IO Carrier on the VDD_IO_SEL# (due to the Carrier pulling the line down) to protect the module.
  • Page 150 The Carrier Circuits domain includes “everything else” (and does not include items from the Battery Charger and Module domain, even though they may be mounted on the Carrier). This is illustrated in the figure below. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 151 Embedian, Inc. Figure 27 System Power Domains SMARC-FiMX6 Computer on Module User’s Manual v.1.2...

  • Page 152: Power Signals

    S110, S119, P120, S124, S130, P133, S136, P142, S143 S147 VDD_RTC  I 3.3V RTC supply, can be left unconnected if internal RTC is not used 5V is recommended for non-battery operated system. Note: SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 153 Power-button input from Carrier board. Carrier to float the line in in-active state. Active low, level sensitive. It is de-bounced on the Module Pulled up on Module. Driven by OD part on Carrier. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 154 Driven by OD part on Carrier. S151 CHARGING#  Strap VDD_IO Held low by Carrier during battery charging. Carrier to float the line when charge is complete. Pulled up on Module. Driven by OD part on Carrier. SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 155 Pulled up on Module. Driven by OD part on Carrier. 4.2.4. Special Control Signals (TEST#) SMARC-FiMX6 module boots up from an onboard NOR Flash first. The firmware (u-boot) in boot rom will read the BOOT_SEL configuration and decides where to load the kernel.

  • Page 156: Power Flow And Control Signals Block Diagram

    Embedian, Inc. 4.3 Power Flow and Control Signals Block Diagram Following figures shows the power flow and control signals block diagram. Figure 28: Power Block Diagram SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 157 VDD_IO_SEL# will be floating on carrier that represents a 3.3V VDD_IO carrier or connecting to GND on carrier for 1.8V VDD_IO. These two signals will turn on the PMIC on module to power on the module. If SMARC-FiMX6 supports 3.3V I/O only, the carrier needs to float VDD_IO_SEL# pin. The...

  • Page 158: Power States

    Embedian, Inc. 4.4 Power States The SMARC-FiMX6 module supports different power states. The table below describes the behavior in the different states and which power rails and peripherals are active. Additional power states can be implemented if required using available GPIOs to control additional power domains and peripherals.

  • Page 159: Power Sequences

    The module main voltage rail (VDD_IN) can be removed and applied again. If needed, this could also be done with a button and a small circuit. SMARC-FiMX6 module supports being power cycled by asserting the RESET_IN# signal (e.g. by pressing the reset button or shunt and relief the reset jumper), please consult the associated module datasheet for more information about the support power cycle methods.
  • Page 160 Check the datasheet of all peripheral components on the carrier board for a proper sequencing. The SMARC-FiMX6 modules guarantees to apply the reset output RESET_OUT# not earlier than 100ms after the CARRIER_PWR_ON goes high.
  • Page 161 The lower voltages (e.g. peripheral 3.3V) need to ramp down before the higher ones do (e.g. peripheral 5V). Figure 31: Shutdown Sequence SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 162 This guarantees a minimum reset time of 1ms even if the reset input RESET_IN# is triggered for a short time. Figure 32: Reset Sequence SMARC-FiMX6 Computer on Module User’s Manual v.1.2...

  • Page 163: Terminations

    2.2K pull-up to VDD_IO I2C_CAM_DAT  2.2K pull-up to VDD_IO I2C_CAM_CK  2.2K pull-up to VDD_IO I2C_GP_DAT  2.2K pull-up to VDD_IO I2C_GP_CK  2.2K pull-up to VDD_IO SDIO_CD#  10k pull-up to 3.3V SDIO_WP  10k pull-up to 3.3V SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 164 100k pull-up to VIN PCIE_A_TX+  0.1 uF 0402 capacitor PCIE_A_TX‐  0.1 uF 0402 capacitor SATA0_TX+  0.1 uF 0402 capacitor SATA0_TX‐  0.1 uF 0402 capacitor SATA0_RX+  0.1 uF 0402 capacitor SATA0_RX‐  0.1 uF 0402 capacitor SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 165 LED with the anode tied to Carrier 3.3V, is typical. LVDS LCD  100 ohm resistive termination across the differential pairs at the endpoint of the signal path, usually on the display assembly SMARC-FiMX6 Computer on Module User’s Manual v.1.2...
  • Page 166 Texas Instruments TPD12S016. If discrete Carrier pull-ups are used, they should be 10K. PCIE_A_RX  Series coupling caps near the TX pins of the Carrier board PCIe device SMARC-FiMX6 Computer on Module User’s Manual v.1.2...

  • Page 167: Boot Device Selection

    Carrier board user to select from eight possible boot devices. The first stage of bootloader on SMARC-FiMX6 will boot up to SPI NOR flash first. The firmware on NOR flash will read the boot device configuration and load the second stage bootloader from selected boot devices.

Table of Contents