Cirrus Logic CS5374 Manual

Dual high-performance amplifier & modulator
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Dual High-performance Amplifier &
Features
High Input Impedance Differential Amplifier
• Ultra-low input bias: < 1 pA
• Max signal amplitude: 5 Vpp differential
Fourth Order Delta-Sigma (ΔΣ) Modulator
• Signal Bandwidth: DC to 2 kHz
• Common mode rejection: 110 dB CMRR
Differential Analog Input, Digital ΔΣ Output
• Multiplexed inputs: INA, INB, 800Ω termination
• Selectable Gain: 1x, 2x, 4x, 8x, 16x, 32x, 64x
Excellent Amplifier Noise Performance
• 1.5 μVpp between 0.1 Hz and 10 Hz
• 11 nV /
Hz from 200 Hz to 2 kHz
High Modulator Dynamic Range
• 126 dB SNR @ 215 Hz BW (2 ms sampling)
• 123 dB SNR @ 430 Hz BW (1 ms sampling)
Low Total Harmonic Distortion
• –118 dB THD typical (0.000126%)
• –108 dB THD maximum (0.0004%)
Low Power Consumption
• Normal operation: 6.5 mA per channel
• Power down: 15 μA per channel max
Dual Power Supply Configuration
• VA+ = +2.5 V; VA– = –2.5 V; VD = +3.3 V
Preliminary Product Information
http://www.cirrus.com
GUARD1
INA1+
+
INB1+
-
MUX1
-
INA1-
INB1-
+
VA+
VA-
INA2+
+
INB2+
-
MUX2
-
INA2-
INB2-
+
GUARD2
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright  Cirrus Logic, Inc. 2010
Description
The CS5374 combines two marine seismic analog mea-
surement channels into one 7 mm x 7 mm QFN
package. Each measurement channel consists of a high
input impedance programmable gain differential amplifi-
er that buffers analog signals into a high-performance,
fourth-order ΔΣ modulator. The low-noise ΔΣ modulator
converts the analog signal into a one-bit serial bit stream
suitable for the CS5376A digital filter.
Each amplifier has two sets of external inputs, INA and
INB, to simplify system design as inputs from a hydro-
phone sensor or the CS4373A test DAC. An internal
800Ω termination can also be selected for noise tests.
Gain settings are binary weighted (1x, 2x, 4x, 8x, 16x,
32x, 64x) and match the CS4373A test DAC output at-
tenuation settings for full-scale testing at all gain ranges.
Both the input multiplexer and gain are set by registers
accessed through a standard SPI™ port.
Each fourth-order ΔΣ modulator has very high dynamic
range combined with low total harmonic distortion and
low power consumption. It converts differential analog
signals from the amplifier to an oversampled ΔΣ serial bit
stream which is decimated by the CS5376A digital filter
to a 24-bit output at the final output word rate.
ORDERING INFORMATION
See
page
43.
OUT1+ OUT1-
INR1-
INF1- INF1+INR1+
Synchronization
th
4
Modulator
CS5374
th
4
Modulator
OUT2+
OUT2-
INR2-
INF2-
INF2+
INR2+
(All Rights Reserved)
CS5374
ΔΣ
Modulator
VA-
VA+
Reset, Clock,
RST
and
MCLK
MSYNC
Order
MDATA1
MFLAG1
VD
GND
Order
MDATA2
MFLAG2
SDO
TM
SDI
SPI
Serial
Interface
SCLK
CS
VREF+
VREF-
SEP '10
DS862F2

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Summary of Contents for Cirrus Logic CS5374

  • Page 1 INF2- INF2+ INR2+ VREF+ VREF- This document contains information for a new product. Preliminary Product Information Cirrus Logic reserves the right to modify this product without notice. Copyright  Cirrus Logic, Inc. 2010 SEP '10 (All Rights Reserved) http://www.cirrus.com DS862F2...
  • Page 2: Table Of Contents

    5.3.4 ADCCFG — 0x03....................24 5.3.5 PWRCFG — 0x04 ....................24 Example: CS5374 Configuration by an External SPI Master ........24 Example: CS5374 Configuration by the CS5376A SPI 2 Port ........25 5.5.1 CS5376A SPI 1 Transactions ................25 6. POWER MODES ........................29 Normal Operation ......................
  • Page 3 Table 3. Digital Selections for Gain and Input Mux Control ............23 Table 4. Example SPI Transactions to Write and Read the CS5374 Configuration Registers ..24 Table 5. Example CS5376A SPI 1 Transactions to Write and Read the GPCFG0 Register ..25 Table 6.
  • Page 4: Characteristics And Specifications

    CS5374 CS5374 CHARACTERISTICS AND SPECIFICATIONS • Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. • Typical performance characteristics and specifications are derived from measurements taken at nom- inal supply voltages and T = 25°C. • GND = 0 V, all voltages with respect to 0 V.
  • Page 5: Thermal Characteristics

    CS5374 CS5374 THERMAL CHARACTERISTICS Parameter Symbol Unit Ambient Operating Temperature °C Storage Temperature Range °C Allowable Junction Temperature °C θ Junction to Ambient Thermal Impedance (4-layer PCB) °C / W ANALOG CHARACTERISTICS Parameter Symbol Unit Amplifier Inputs Signal Frequencies 2000...
  • Page 6: Figure 1. External Anti-Alias Filter Components

    CS5374 CS5374 ANALOG CHARACTERISTICS (CONT.) Parameter Symbol Unit Modulator Inputs Input Signal Frequencies (Note 9) 2000 Full-scale Differential AC Input Full-scale Differential DC Input -2.5 Input Common Mode Voltage (VA-)+2.5 Input Voltage Range (V ± Signal ) (VA-)+0.7 (VA+)-1.25 Differential Input Impedance INR±...
  • Page 7: Performance Specifications

    13. Tested with a 31.25 Hz sine wave at 1 ms sampling rate and -1 dB amplitude. CS5374 Amplifier In-Band Noise CS5374 Amplifier Wide Band Noise 1000 1200 1400 1600 1800 2000 100k Frequency (Hz) Frequency (Hz) Figure 2. CS5374 Amplifier Noise Performance...
  • Page 8 CS5374 analog inputs at 1x gain. Value is offset corrected. 15. Absolute gain accuracy tests the matching of 1x gain across multiple CS5374 channels in a system. 16. Relative gain accuracy tests the tracking of 2x, 4x, 8x, 16x, 32x, 64x gain relative to 1x gain on a single CS5374 channel.
  • Page 9: Channel Performance Plots

    CS5374 CS5374 CHANNEL PERFORMANCE PLOTS Figure 3. CS5374 Noise Performance (1x Gain) Figure 4. CS5374 + CS4373A Test DAC Dynamic Performance...
  • Page 10: Digital Characteristics

    0.9 * VD 0.1 * V D Figure 5. Digital Rise and Fall Times SYNC from external system. SYNC MCLK MSYNC MDATA MFLAG TDATA Figure 6. System Synchronization Diagram SYNC from External. MCLK, MSYNC, TDATA from CS5376A. MDATA, MFLAG from CS5374.
  • Page 11: Figure 7. Mclk / Msync Timing Detail

    0xA2E736 0x5D18CA Notes: 23. MCLK is generated by the CS5376A digital filter. If MCLK is disabled, the CS5374 device automatically enters a power-down state. See Power Supply Characteristics for typical power-down timing. 24. MSYNC is generated by the CS5376A digital filter and is latched by CS5374 on MCLK falling edge, synchronization instant (t ) is on the next MCLK rising edge.
  • Page 12: Spi™ Interface Timing (External Master)

    CS5374 CS5374 SPI™ INTERFACE TIMING (EXTERNAL MASTER) Parameter Symbol Unit SDI Write Timing CS Enable to Valid Latch Clock Data Set-up Time Prior to SCK Rising Data Hold Time After SCK Rising SCK High Time SCK Low Time SCK Falling Prior to CS Disable...
  • Page 13: Power Supply Characteristics

    CS5374 CS5374 POWER SUPPLY CHARACTERISTICS Parameter Symbol Unit Power Supply Current, ch1 + ch2 combined Analog Power Supply Current (Note μA Digital Power Supply Current (Note Power Supply Current, ch1 or ch2 only Analog Power Supply Current (Note μA Digital Power Supply Current...
  • Page 14: General Description

    Figure 11 Figure 12 shows connection dia- 2x, 4x, 8x, 16x, 32x, 64x) and match the CS4373A grams for the CS5374 device when connected to test DAC output attenuation settings for full-scale the CS5376A digital filter. testing at all gain ranges. Both the input multiplex-...
  • Page 15: Figure 11. Cs5374 Connection Diagram

    Synchronization MSYNC MSYNC MDATA1 MDATA1 Order ΔΣ Modulator MFLAG1 MFLAG1 CS5374 CS5376A Modulator Data Interface MDATA2 MDATA2 Order ΔΣ Modulator MFLAG2 MFLAG2 SPI 2 Serial Serial Peripheral Communications Interface 2 Interface SCLK SCK2 Figure 12. CS5374 to CS5376A Digital Interface...
  • Page 16: Amplifier Operation

    2 kHz. They have multiplexed inputs and pro- grammable gains of 1x, 2x, 4x, 8x, 16x, 32x, and The CS5374 supports gain ranges of 1x, 2x, 4,x 8x, 64x. The performance of this amplifier makes it 16x, 32x, and 64x. Amplifier gain is selected using...
  • Page 17: Differential Signals

    CS5374 CS5374 selected differential input signal, and will vary as the signal common mode varies. The GUARD out- put will not drive a significant load, as it can only provide a shielding voltage. 3.3 Differential Signals Analog signals into and out of the amplifiers are...
  • Page 18: Modulator Operation

    The companion CS5376A digital filter generates Figure 1 on page 6 illustrates the CS5374 amplifi- the clock and synchronization inputs for the modu- er-to-modulator analog connections with input lators while receiving the one-bit data and over- anti-alias filter components. Filter components on range flag outputs.
  • Page 19: Modulator Inputs - Inr, Inf

    4.3 Modulator Output — MDATA pacitor ‘rough charge’ inputs that pre-charge the internal analog sampling capacitor before it is con- The CS5374 modulators are designed to operate nected to the INF± fine input pins. with the CS5376A digital filter. The digital filter generates the modulator clock and synchronization 4.2.1 Modulator Input Impedance...
  • Page 20: Modulator Stability - Mflag

    The CS5376A digital filter generates the master clock for the CS5374, typically 2.048 MHz, from a synchronous clock input from the external system. CS5376A Digital Filter...
  • Page 21: Spi Tm Serial Port

    Figure 15. SPI Interface Block Diagram SERIAL PORT 5.2 SPI Serial Transactions The CS5374 SPI interface is a slave serial port de- signed to interface with the CS5376A SPI 2 port. Following reset, master mode serial transactions to SPI commands from the CS5376A write and read...
  • Page 22: Figure 16. Cs5374 (Slave) Serial Transactions With Cs5376A (Master)

    CS5374 SPI Write from CS5376A SPI2 0x02 ADDR DATA SPI2CMD[15:8] SPI2CMD[7:0] SPI2DAT[23:16] CS5374 SPI Read from CS5376A SPI2 ADDR 0x03 SPI2CMD[15:8] SPI2CMD[7:0] DATA SPI2DAT[23:16] SPI Mode 0 Transaction Details Cycle SCLK Figure 16. CS5374 (Slave) Serial Transactions with CS5376A (Master)
  • Page 23: Spi Registers

    5.3.2 AMP1CFG — 0x01 5.3 SPI Registers The AMP1CFG register controls the amplifier The CS5374 SPI registers are 8-bit registers that MUX and GAIN settings for channel 1. It also en- control the CS5374 hardware configuration. See ables PWDN mode for the channel 1 amplifier plus “SPI...
  • Page 24: Adccfg - 0X03

    Returned data byte on the SO pin. SI: 03 | 04 | 00 Read PWRCFG register (0x04). SO: ---------- | 8F Returned data byte on the SO pin. Table 4. Example SPI Transactions to Write and Read the CS5374 Configuration Registers...
  • Page 25: Example: Cs5374 Configuration By The Cs5376A Spi 2 Port

    CS5374 CS5374 5.5 Example: CS5374 Configuration by the CS5376A SPI 2 Port The CS5374 SPI port was designed to connect to contain internal commands to write the CS5376A the CS5376A secondary SPI 2 port as shown in digital filter registers that control the SPI 2 hard- Figure 12 on page 15.
  • Page 26: Table 6. Example Cs5376A Spi 1 Transactions To Write The Cs5374 Amp1Cfg Register

    SPI Command : 0x02 : Write MISO: ----------------------------------------------------------- SPI Address : 0x03 : SPICMD SPICMD : 0x000001: Write Register SPIDAT1 : 0x000010 : SPI2CTRL SPIDAT2 : 0x3F4162 : CS1 Transaction Table 6. Example CS5376A SPI 1 Transactions to Write the CS5374 AMP1CFG Register...
  • Page 27: Table 7. Example Cs5376A Spi 1 Transactions To Write Amp2Cfg And Adccfg

    CS5374 CS5374 Transaction CS5376A Primary SPI 1 Write Description MOSI: 02 | 03 | 00 00 01 | 00 00 11 | 00 02 02 SPI Command : 0x02 : Write MISO: ----------------------------------------------------------- SPI Address : 0x03 : SPICMD SPICMD : 0x000001 : Write Register...
  • Page 28: Table 8. Example Cs5376A Spi 1 Transactions To Write The Cs5374 Pwrcfg Register

    SPI Command : 0x02 : Write MISO: ----------------------------------------------------------- SPI Address : 0x03 : SPICMD SPICMD : 0x000001: Write Register SPIDAT1 : 0x000010 : SPI2CTRL SPIDAT2 : 0x3F4162 : CS1 Transaction Table 8. Example CS5376A SPI 1 Transactions to Write the CS5374 PWRCFG Register...
  • Page 29: Power Modes

    When With MCLK active and all amplifiers and modula- used with the CS5376A digital filter, the CS5374 is tors disabled (PWDN = 1) the CS5374 is placed in this lowest power-down state immediately after into a power-down state.
  • Page 30: Voltage Reference

    0.1 μF 0.1 μF Figure 18. Voltage Reference Circuit VOLTAGE REFERENCE The CS5374 modulators require a 2.500 V preci- A separate RC filter is required for each device ± sion voltage reference to be supplied to the VREF connected to the voltage reference output. Signal- pins.
  • Page 31: Vref Accuracy

    Gain drift specifications of the CS5374 do not include the temperature drift effects of external passive components or of the voltage reference device it-...
  • Page 32: Power Supplies

    8.1 Analog Power Supplies digital power supply across the VD+ and GND pins The analog power pins of the CS5374 are to be sup- is specified to be +3.3 V. plied with a total of 5 V between VA+ and VA–...
  • Page 33: Pcb Layers And Routing

    For similar reasons, care should be taken to connect It is also recommended to dedicate a full PCB layer the CS5374 thermal pad on the bottom of the pack- to a solid ground plane, without splits or routing. age to VA–, not system ground (GND), since it in- All bypass capacitors should connect between the ternally connects to VA–...
  • Page 34: Spi Tm Register Summary

    CS5374 CS5374 REGISTER SUMMARY The CS5374 Configuration Registers contain the hardware configuration settings. Name Addr. Type # Bits Description VERSION 0x00 Device Version ID AMP1CFG 0x01 Amplifier 1 configuration AMP2CFG 0x02 Amplifier 2 configuration ADCCFG 0x03 Modulator 1 & 2 configuration...
  • Page 35: Version: 0X00

    CS5374 CS5374 9.1 VERSION: 0x00 Figure 20. Hardware Version ID Register VERSION Address: 0x00 (MSB)7 (LSB)0 VER7 VER6 VER5 VER4 VER3 VER2 VER1 VER0 Not defined (read as 0) Readable Writable Reset Condition : 0100_0001 (0x41) : Default value Readable...
  • Page 36: Amp1Cfg: 0X01

    CS5374 CS5374 9.2 AMP1CFG: 0x01 Figure 21. Amplifier 1 Configuration Register AMP1CFG Address: 0x01 (MSB)7 (LSB)0 PWDN1 MUX1_1 MUX1_0 GUARD GAIN1_2 GAIN1_1 GAIN1_0 Not defined (read as 0) Readable Writable Readable Reset Condition : 0000_0000 (0x00) : Default value and Writable...
  • Page 37: Amp2Cfg: 0X02

    CS5374 CS5374 9.3 AMP2CFG: 0x02 Figure 22. Amplifier 2 Configuration Register AMP2CFG (MSB)7 (LSB)0 Address: 0x02 PWDN2 MUX2_1 MUX2_0 GAIN2_2 GAIN2_1 GAIN2_0 Not defined (read as 0) Readable Writable Readable Reset Condition : 0000_0000 (0x00) : Default value and Writable...
  • Page 38: Adccfg: 0X03

    CS5374 CS5374 9.4 ADCCFG: 0x03 Figure 23. Modulator 1 & 2 Configuration Register ADCCFG (MSB)7 (LSB)0 Address: 0x03 OFST PWDN2 PWDN1 Not defined (read as 0) Readable Writable Reset Condition : 0000_0000 (0x00) : Default value Readable and Writable Normal Operation : 0100_0000 (0x40) : HP mode enabled...
  • Page 39: Figure 24. Power Configuration Register Pwrcfg

    CS5374 CS5374 Figure 24. Power Configuration Register PWRCFG Address: 0x04 (MSB)7 (LSB)0 adc_lpwr amp_i1_1 amp_i1_0 rough i1_tail amp_i5_1 amp_i5_0 Not defined (read as 0) Readable Writable Reset Condition : 0000_0000 (0x00) : Default value Readable and Writable Normal Operation : 1000_1111 (0x8F) : Reduced power...
  • Page 40: Pin Descriptions

    CS5374 CS5374 10. PIN DESCRIPTIONS Pin 1 Location Indicators INA1+ MCLK INA1- MSYNC INB1- MDATA1 INB1+ MFLAG1 THERMAL MDATA2 CONNECT MFLAG2 TO VA- INB2+ INB2- INA2- SCLK INA2+ Top-Down (Though Package) View Name Number Type Description Power Supplies 6, 39 Analog power supply.
  • Page 41 CS5374 CS5374 Differential Amplifier Analog Outputs OUT1–, Channel 1 differential analog output. OUT1+ Guard output voltage for analog input Channel 1. GUARD1 GUARD2 Guard output voltage for analog input Channel 2. OUT2+, Channel 2 differential analog output. OUT2– Modulator Analog Inputs INR1+, Channel 1 analog differential rough and fine inputs.
  • Page 42: Package Dimensions

    CS5374 CS5374 11. PACKAGE DIMENSIONS 48-PIN QFN (7MM X 7MM)
  • Page 43: Ordering Information

    CS5374 CS5374 12. ORDERING INFORMATION Model Number Temperature Package CS5374-CNZ, lead (Pb) free -10 to +70 °C 48-Pin QFN 13. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Peak Reflow Temp MSL Rating* Max Floor Life CS5374-CNZ, lead (Pb) free 260 °C...
  • Page 44: Revision History

    TORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.

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