Maxim MAX3421E Programming Manual

Usb peripheral and host controller with spi interface

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Programming Guide

USB Peripheral and Host Controller

Abstract: The MAX3421E adds USB host or peripheral capability to any system with an SPI

interface. This Programming Guide describes every register and bit for host operation. For

operation of the MAX3421E as a peripheral, consult the MAX3420E Programming Guide

For more information on the MAX3421E, please visit:

For more information on USB and Maxim's USB products, see:

SPI is a trademark of Motorola, Inc.

The Maxim logo is a registered trademark of Maxim Integrated Products, Inc.

The Dallas Semiconductor logo is a registered trademark of Dallas Semiconductor Corp.

June 2006

MAX3421E

with SPI Interface

Vcc

D+

D-

GPIN[7:0]

GPOUT[7:0]

VBCOMP

RES#

GND

SCK

MOSI

MISO

SS#

INT

GPX

www.maxim-ic.com/max3421e

www.maxim-ic.com/usb

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Summary of Contents for Maxim MAX3421E

Page 1 USB Peripheral and Host Controller with SPI Interface Abstract: The MAX3421E adds USB host or peripheral capability to any system with an SPI interface. This Programming Guide describes every register and bit for host operation. For operation of the MAX3421E as a peripheral, consult the MAX3420E Programming Guide...
Page 2: About This Programming Guide
MAX3420E code, keep the HOST bit set to 0 (the default), and consult the MAX3420E Programming Guide for programming details. If you plan to use the MAX3421E only as a USB peripheral but want to take advantage of the new peripheral features, read about the added registers R21 to R24 and the added bits PULSEWID1/0, SEPIRQ, and HOST in this Programming Guide.
Page 3 Table 1. MAX3421E HOST Registers (Host Bit = 1) Name — — RCVFIFO SNDFIFO — — SUDFIFO — RCVBC SNDBC — — — — — — — — — — USBIRQ VBUSIRQ NOVBUSIRQ OSCOKIRQ USBIEN VBUSIE NOVBUSIE OSCOKIE USBCTL CHIPRES...
Page 4 Table 2. All MAX3421E Register Bits, for both PERIPHERAL and HOST Modes (Shaded bits do not change during mode (HOST bit) changes.) Perip.Name Host Name EP0FIFO — — EP1OUTFIFO RCVFIFO EP2INFIFO SNDFIFO EP3INFIFO — SUDFIFO SUDFIFO EP0BC — EP1OUTBC RCVBC...
Page 5 USB activities. To clarify which entity—CPU or MAX3421E—sets or clears a register bit, this document uses the terms quite specifically and consistently. SIE indicates that the MAX3421E sets or clears the bit; CPU indicates that the SPI master attached to the MAX3421E sets or clears the bit.
Page 6 SIE clears certain register bits. The following section explains the effect of each reset source. MAX3421E register bits are clocked from two sources: 1. The internal 12MHz oscillator 2. The SCLK signal that the CPU supplies to the SPI interface.
Page 7 • INTLEVEL • POSINT • GPX[B:A] • GPOUT[7:0] • DPPULLUP/DN Note: These resets set HOST = 0, selecting peripheral operation. Changing the MODE Bit Peripheral to Host The SIE clears register bits that do not apply to host operation. The CPU should not write these bits with anything but 0 when HOST = 1.
Page 8 31. The direction bit sets the direction for subsequent bytes in the transfer. The ACKSTAT bit duplicates a USB control bit (R9 bit 6), and is valid only when the MAX3421E operates as a USB peripheral. The SIE ignores the ACKSTAT bit when HOST = 1.
Page 9 The first eight bits of an SPI access constitute the command byte, clocked into the MOSI pin. The MAX3421E sends status data on the MISO pin while the command byte is clocked into the MOSI pin. The status bits ,while operating in HOST mode, are shown in...
Page 10 CPU does not need to load the SNDFIFO again. It just launches the same transfer by rewriting the HXFR register. The MAX3421E does the USB housekeeping work. Set up the above bits, launch the transfer by writing the HXFR register, wait for a completion interrupt, and check the HRSLT bits (Host Result) to see transfer results.
Page 11 PID values—DATA0, DATA1, DATA0, etc. The MAX3421E provides four bits to maintain the data toggles. After a data transfer to an endpoint, the SIE updates bits RCVTOGRD and SNDTOGRD (page 36) to indicate the toggle values for the selected endpoint.
Page 12 Programming BULK-OUT Transfers The MAX3421E sends BULK data to a peripheral using OUT packets, SNDFIFO data, and handshakes. The CPU first checks for SNDBAVIRQ = 1 (page 56) to see if the send buffer is available for loading. (The SIE sets this interrupt request bit whenever an OUT transfer successfully completes.) If the buffer is available, the CPU writes up to 64 data bytes into the SNDFIFO...
Page 13 Programming BULK-IN Transfers The CPU issues an IN token to request a peripheral to send it BULK data . Then the SIE transfers data into its RCVFIFO, and ACKS the transfer. The CPU writes HXFR = 0000eeee (Table 4) to initiate the IN transfer, where eeee is the desired endpoint address.
Page 14 A STATUS packet is a BULK-OUT or BULK-IN transfer that contains no data and which always uses the DATA1 PID. The programmer could send these transfers by programming standard BULK transfers. For convenience, however, the MAX3421E provides special HS-OUT and HS-IN launch codes for handshakes so the SIE can do the work.
Page 15 1-millisecond frame), the USB spec requires the host to deliver or consume that number of bytes every frame. This gives rise to special consideration for the MAX3421E, which may be connected to a slow SPI interface or CPU. The controller must keep pace with the scheduling requirements. If there is...
Page 16 This case applies for a single 64-byte packet, or if the final data payload of a multibuffer transfer is exactly 64 bytes. The CPU loads the SNDFIFO with 64 bytes and writes SNDBC = 64, waits for SNDBAVIRQ = 1, then writes SNDBC = 0 to indicate the end of the transfer. MAX3421E Programming Guide...
Page 17 OUT Payload Greater than 64 Bytes The CPU loads the SNDFIFO with 64 bytes of data, then writes SNDBC = 64. If SNDBAVIRQ = 1, it can load the second portion of the data packet into the SNDFIFO, after which it again writes the SNDBC register with the byte count.
Page 18 • Some IRQ Bits and the IE Bit Table 2 shows the registers and bits that persist when the SPI master commands a MAX3421E mode change, either from peripheral to host or from host to peripheral. Therefore, a mode change does not disturb the SPI interface configuration or the GPOUT pin values.
Page 19 BUSEVENTIRQ, BUSEVENTIE Meaning: BUSEVENTIRQ: One of two bus events has occurred. BUSEVENTIE: Enable the BUSEVENTIRQ. Mode: Host only The SIE sets the BUSEVENTIRQ bit when it completes signaling one of two USB bus events: Bus Reset (when BUSRST 1 → Bus Resume (when BUSRSM 1 →...
Page 20 2. Test for BUSRST = 0 or respond to the BUSEVENTIRQ. 3. Turn on frame markers by setting SOFKAENAB = 1. 4. Wait for at least one FRAMEIRQ. Step 4 ensures that the host logic is ready to generate the first host transaction. MAX3421E Programming Guide...
Page 21 The CPU clears this bit to take the chip out of reset. Programming Notes The CPU can clear this bit immediately after setting it. Resetting the MAX3421E either at power on or by setting the CHIPRES bit clears most register bits, including the HOST bit, and therefore sets up the MAX3421E to operate as a USB peripheral device.
Page 22 To detect a peripheral connect or disconnect, the CPU should first set HOST = 1 to put the MAX3421E into host mode. It should then set DPPULLDN = 1 and DMPULLDN = 1 to establish logic low levels for the D+ and D- signals.
Page 23 MAX3421E automatically generates the next SOF packet. Since the MAX3421E can be connected to any speed SPI master, and since there is no guarantee that the controlling firmware will write the HXFR register early enough in every frame to guarantee delivery, the SIE provides the DELAYISO bit to control the behavior when a packet is scheduled too late in a frame.
Page 24 SOF, the SIE defers sending the IN packet until after the next frame. In this case the SIE asserts the FRAMEIRQ for the next frame, sends the ISO-IN packet, transfers the IN data, and asserts the HXFRDNIRQ with HRSLT[3:0] = 0x00 (hrSUCCESS). MAX3421E Programming Guide...
Page 25 Note: If ISO scheduling problems are detected, the system must be modified to dispatch the ISO packets earlier in each frame, perhaps by speeding up the SPI interface, tuning the firmware, or both.
Page 26 1500kΩ resistor from D+ to 3.3V. Because the bus is weakly pulled down, the SIE can detect not only when a peripheral has plugged in, but also its speed. If the MAX3421E is operating as a peripheral (HOST = 0), these bits should both be set to zero (their default values).
Page 27 FDUPSPI Meaning: Full-Duplex SPI port operation Mode: Peripheral and Host The CPU sets this bit to operate the SPI port in full-duplex mode. The CPU clears this bit to operate in half-duplex mode. POR: FDUPSPI = 0 (half-duplex) Chip Reset: No change Bus Reset: No change Pwr Down:...
Page 28 Following the command byte, the SPI master issues one or more groups of 8-SCK clocks to clock byte data into or out of the MAX3421E. When accessing a FIFO, as long as CS# remains low, the register address clocked in with the command remains in effect. This ability to burst bytes is convenient when reading or writing the endpoint FIFOS.
Page 29 the inactive level of the SCK signal, low for mode (0,0) and high for mode (1,1). In both modes the MOSI and MISO data sampled by the rising edge of SCK is the same. Figure 6. SPI interface operating in mode (0,0). Figure 7.
Page 30 The CPU sets and clears the FRAMEIE bit. When FRAMEIE = 1, the FRAMEIRQ is enabled as a source to activate the INT pin. Programming Notes At full speed, the SIE sets the FRAMEIRQ interrupt at the beginning of the SOF packet. MAX3421E Programming Guide...
Page 31 The SIE clears this bit to indicate that it has completed the operation. Programming Notes This bit has meaning only when the MAX3421E is operating as a full-speed host. (When operating as a low-speed host, there is no SOF packet or frame count.) After setting FRMRST = 1, the next SOF packet will contain a frame count of zero.
Page 32 The CPU sets a GPIN Interrupt Enable bit to pass the corresponding IRQ bit through to the interrupt logic feeding the MAX3421E INT pin. If IE = 1, an enabled IRQ appears either on the INT pin if SEPIRQ = 0, or on the GPX pin if SEPIRQ = 1 and GPX[B:A] = 10.
Page 33 GPOUT(0 through 7) Meaning: General-Purpose Output pins 0 through 7 Mode: Peripheral and Host The CPU sets and clears these bits. Programming Notes The CPU writes these bits to control the states of the GPOUT pins. The output voltages are referenced to the voltage on the VL pin.
Page 34 GPIN pins makes a 0-1 or 1-0 transition. In this case the GPX pin serves as a second interrupt pin (along with INT), with the same configuration (level or edge, edge polarity) as the INT pin. See page for more information about the SEPIRQ bit. MAX3421E Programming Guide...
Page 35 HOST bit set to 0. In this mode the MAX3421E operates as a MAX3420E peripheral-only controller. The CPU sets HOST = 1 to operate the MAX3421E as a host. It uses the register set shown in Table 1. Programming information for operating when HOST = 0 is found in the MAX3420E Programming Guide.
Page 36 Doing this allows the CPU to restore the toggle value the next time the CPU transfers data to the same endpoint. The CPU initializes the endpoint toggle value using the SNDTOG0/1 and RCVTOG0/1 bits in the HCTL register (page 59). MAX3421E Programming Guide...
Page 37 HUBPRE Meaning: Send the PRE PID to a LS device operating through a USB hub. Mode: Host only The CPU sets and clears this bit. Programming Notes If the host firmware detects (during enumeration) that it is talking to a low-speed peripheral through a USB hub, it sets HUBPRE = 1.
Page 38 These two transfer types are identical, differing only by when the host firmware schedules them. The ‘-ep’ field in the ‘hex’ column indicates the value of EP[3:0]. For details about each of these transfer types, see “Programming Host Transfers” on page 10. MAX3421E Programming Guide...
Page 39 HXFRDNIRQ, HXFRDNIE Meaning: HXFRDNIRQ: Host Transfer Done Interrupt Request HXFRDNIE: Host Transfer Done Interrupt Enable Mode: Host only The SIE sets the HXFRDNIRQ bit when it has completed a host transfer. The CPU clears the HXFRDNIRQ by writing a 1 to it. The CPU sets and clears the HXFRDNIE bit.
Page 40 When IE = 0, the state of the INT pin is inactive (open for level mode, high for negative edge, low for positive edge). The internal IRQ bits operate independent of the state of the IE bit. The IE bit only controls activation of the INT output pin. MAX3421E Programming Guide...
Page 41 INTLEVEL POSINT PULSEWID1, PULSEWID0 Meaning: INTLEVEL: Sets the INT output pin to level-active (1) or edge-active (0). POSINT: Edge polarity of the edge-active INT pin. PULSEWID: These two bits set the IRQ inactive time in edge mode (see below). Mode: Peripheral and Host INTLEVEL The CPU sets the INTLEVEL bit to make the INT output pin level-active.
Page 42 = 1, the MAX3421E removes the eight interrupts associated with the eight GPIN pins from the INT pin. The MAX3421E then routes them to the GPX pin, which serves as a second interrupt output pin when GPX[B:A] = 10. When the GPX pin operates in this manner its characteristics as an INT output pin are set by the INTLEVEL, POSINT, and PULSEWID[1:0] bits.
Page 43 LOWSPEED Meaning: Sets the host for low-speed operation Mode: Host only The CPU sets and clears this bit. Programming Notes The CPU sets this bit to enable operation as a low-speed USB host. The CPU will normally set this bit when it discovers that a peripheral has plugged in (activating CONDETIRQ) and that the quiescent bus state is D+ = 0, D- = 1.
Page 44 INT pin. Programming Notes Whenever the CPU stops the MAX3421E oscillator by resetting the chip (setting CHIPRES = 1 then CHIPRES = 0), it should wait for the OSCOKIRQ to assert before continuing operation. MAX3421E Programming Guide...
Page 45 PERADDR Register Meaning: Peripheral Address to which packets are to be sent. Mode: Host only The CPU writes this register; the SIE reads it. Programming Notes When the SIE sends a token packet after the CPU loads the HXFR register, it takes the peripheral address from this register.
Page 46 PWRDOWN Meaning: Power Down the MAX3421E. Mode: Peripheral and Host The CPU sets the PWRDOWN bit to put the chip into a low-power state, and clears the PWRDOWN bit to resume operation. Programming Notes This bit is designed only for peripheral mode usage, although it is accessible in host mode. The CPU should never set POWERDOWN = 1 when operating as a host.
Page 47 RCVBC Register Meaning: Receive FIFO Byte Count Register Mode: Host only Programming Notes After loading a data packet from the bus into the RCVFIFO, the SIE updates this register with the received byte count and asserts the INDAVIRQ bit. After the CPU has read the number of bytes indicated in the RCVBC register, it clears the RCVDAVIRQ bit by writing a 1 to it.
Page 48 INT pin. Programming Notes The CPU must clear this IRQ bit (by writing a 1 to it) before reading the RCVFIFO data. If any error occurs, the HXVRDNIRQ asserts, while the RCVDAVIRQ does not. MAX3421E Programming Guide...
Page 49 RCVFIFO Register Meaning: Receive FIFO. Mode: Host only As a peripheral sends data over the bus in response to a host IN request, the SIE fills an internal FIFO with data. The CPU reads bytes from the FIFO by repeatedly reading the RCVFIFO register.
Page 50: Revision Register
REVISION Register Meaning: MAX3421E Revision Number Mode: Peripheral and Host This read-only register indicates the chip revision code. Consult the Maxim website for current revision information. Writing this register has no effect. MAX3421E Programming Guide...
Page 51 RWUIRQ, RWUIE Meaning: RWUIRQ: Remote Wakeup Interrupt Request RWUIE: Remote Wakeup Interrupt Enable Mode: Host only The SIE sets the RWUIRQ bit when it receives a remote wakeup signal from a peripheral device. The CPU clears the RWUIRQ bit by writing a 1 to it. The CPU sets and clears the RWUIE bit.
Page 52 Note: The meaning of the J and K states depends on the setting of the LOWSPEED bit. When LOWSPEED = 0, then J means D+ high and D- low; when LOWSPEED = 1, J means D+ low and D- high. MAX3421E Programming Guide...
Page 53 When the CPU sets SEPIRQ = 1, the eight GPIN IRQ signals are removed as an interrupt source to the INT pin, and routed to the GPX pin to serve as a second MAX3421E interrupt pin (bottom figure). The GPX[B:A] setting of 2 normally connects the BUSACT signal to the GPX pin.
Page 54 Setting SEPIRQ = 1 replaces this signal with a signal indicating any of the eight GPIN interrupts. The dotted line in the bottom figure indicates that when the GPX pin functions as this second interrupt pin, its characteristics (as determined by INTLEVEL and POSINT) are the same as for the INT pin. MAX3421E Programming Guide...
Page 55 SIGRSM = 0. Then the CPU restarts the millisecond frame markers by setting SOFKAENAB = 1. The CPU can also check for the end of MAX3421E resume signaling by using the BUSEVENT interrupt request bit BUSEVENTIRQ (page 19). The SIE sets this bit when the SIGRSM bit...
Page 56 SIE FIFO pointer is reset, the host can repeatedly send the same SNDFIFO data in this manner without reloading the FIFO data every time. The CPU clears the SNDBAVIRQ by writing the SNDBC register. The CPU should never directly clear the SNDBAVIRQ bit. MAX3421E Programming Guide...
Page 57 SNDBC Register Meaning: Send FIFO Byte Count Register. Mode: Host only The CPU loads this register to indicate the number of bytes it loaded into the SNDFIFO, and to commit the FIFO to sending OUT data over the bus. Programming Notes When the CPU loads the SNDBC register, the SIE clears the SNDBAVIRQ bit.
Page 58 USB. If the CPU writes the SNDBC register and the other buffer is available, the SIE negates the SNDBAVIRQ bit and then immediately re-asserts it to indicate availability of the second buffer. The CPU should load the SNDFIFO only when a SEND buffer is available, indicated by SNDBAVIRQ = 1. MAX3421E Programming Guide...
Page 59 Writing a 0 to these bits has no effect. Writing 1s to both bits of either bit pair has no effect. Programming Notes The MAX3421E contains two data toggle flip-flops, which it uses to implement USB signaling protocol during SNDFIFO and RCVFIFO data transfers. Before transferring data to an endpoint, the CPU initialized the data toggle value for the endpoint by using these bits.
Page 60 FRMRST = 1 (page 31). Keep-Alive Pulses When operating as a low-speed host and when SOFKAENAB = 1, the SIE generates a keep-alive pulse that consists of one low-speed EOP every millisecond MAX3421E Programming Guide...
Page 61 SUDFIFO Register Meaning: Set Up Data FIFO Register. Mode: Host only The CPU writes the SUDFIFO register eight times to load an internal 8-byte FIFO with data to be included in a SETUP packet. Programming Notes The SUDFIFO has no associated byte-count register because the payload is always eight bytes. If the CPU reads this register after writing eight bytes, the FIFO bytes are read back.
Page 62 3 milliseconds after the SPU sets SOFKAENAB = 0. The CPU clears the SISDNIRQ bit by writing a 1 to it. The CPU sets and clears the SUSDNIE bit. When SUSDNIE = 1, the SUSDNIRQ is enabled as a source to activate the INT pin. MAX3421E Programming Guide...
Page 63 5V supply, and the D+ and D- MAX3421E pulldown resistors can be switched on to detect a peripheral device plugging into the A connector. Host designs should use a current limiter/detector/switch such as the MAX4793 on the A connector V pin.

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Summary of Contents for Maxim MAX3421E

Page 2: About This Programming Guide

Page 50: Revision Register