1. Manuals
  2. Brands
  3. Embedian Manuals
  4. Carrier boards
  5. SMARC T335 Series
  6. Hardware design manual

Embedian SMARC T335 Series Hardware Design Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
SMARC T335x Carrier Board
Hardware Design Guide
SMARC T335x Carrier Board Hardware Design Guide, Document Revision 1.2

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the SMARC T335 Series and is the answer not in the manual?

Questions and answers

Subscribe to Our Youtube Channel

Summary of Contents for Embedian SMARC T335 Series

  • Page 1 SMARC T335x Carrier Board Hardware Design Guide SMARC T335x Carrier Board Hardware Design Guide, Document Revision 1.2...
  • Page 2 SMARC T335x Carrier Board Hardware Design Guide, Document Revision 1.2...
  • Page 3 Revision History Revision Date Changes from Previous Revision 2013/7/26 Initial Release 2014/04/19 Update to Hardware rev. 00B0 1. Remove the 10k pull-ups on USB_EN_OC# 2. Add SDIO_PWREN Schematics 3. Rename Evaluation Carrier Board from Smartbase T3 to SMART-BEE SMARC T335x Carrier Board Hardware Design Guide, Document Revision 1.2...
  • Page 4 This EMBEDIAN product is warranted against defects in material and workmanship for the warranty period from the date of shipment. During the warranty period, EMBEDIAN will at its discretion, decide to repair or replace defective products. Within the warranty period, the repair of products is free of charge as long as warranty conditions are observed.
  • Page 5 EMBEDIAN will not be responsible for any defects or damages to other products not supplied by EMBEDIAN that are caused by a faulty EMBEDIAN product. Technical Support Technicians and engineers from EMBEDIAN and/or its subsidiaries and official distributors are available for technical support. We are committed to making our product easy to use and will help you use our products in your systems.

  • Page 6: Table Of Contents

    Table of Contents   CHAPTER 1 INTRODUCTION ......................10   1.1 ACRONYMS AND ABBREVIATIONS USED ................11   1.2 SIGNAL TABLE TERMINOLOGY ..................... 14   1.3 DOCUMENT AND STANDARD REFERENCES ............... 17   1.4 INTENDED AUDIENCE ....................... 19   CHAPTER 2 INTERFACES ......................... 21  ...
  • Page 7 Embedian Information Document Updates Please always check the product specific section on the Embedian support website at www.embedian.com/ for the most current revision of this document. Contact Information For more information about your Embedian products, or for customer service and technical support, contact Embedian directly.
  • Page 8 Additional Resources Please also refer to the most recent Embedian SMARC T335X user’s manual or TI AM335x processor reference manual and related documentation for additional information. SMARC T335x Carrier Board Hardware Design Guide, Document Revision 1.2...
  • Page 9 Introduction This Chapter gives background information on this document. Section includes：  Acronyms and Abbreviations Used  Signal Table Terminology Document and Standard References   Intended Audience SMARC T335x Carrier Board Hardware Design Guide, Document Revision 1.2...

  • Page 10: Chapter 1 Introduction

    All examples of this document are based on SMART-BEE carrier board that is available from Embedian. This document also provides a collection of useful documentation, application reports, and design recommendations.

  • Page 11: Acronyms And Abbreviations Used

    1.1 Acronyms and Abbreviations Used Table below shows the acronyms and abbreviations used in this section. Abbreviation Explanation ADC  Analogue to Digital Converter Auto‐MDIX  Automatically Medium Dependent Interface Crossing, a PHY with Auto-MDIX f is able to detect whether RX and TX need to be crossed (MDI or MDIX) CAN ...
  • Page 12 Abbreviation Explanation I2C  Inter-Integrated Circuit, two wire interface for connecting low speed peripherals I2S  Integrated Interchip Sound, serial bus for connecting PCM audio data between two devices JTAG  Joint Test Action Group, widely used debug interface LCD  Liquid Crystal Display LSB ...
  • Page 13 Abbreviation Explanation PHY  Physical Layer of the OSI model Power Management IC, integrated circuit that manages PMIC  amongst others the power sequence of a system PU  Pull Up Resistor PWM  Pulse-Width Modulation RGB  Red Green Blue, colour channels in common display interfaces RJ45 ...

  • Page 14: Signal Table Terminology

    1.2 Signal Table Terminology Table below describes the terminology used in this section for the Signal Description tables. The “#” symbol at the end of the signal name indicates that the active or asserted state occurs when the signal is at a low voltage level. When “#” is not present, the signal is asserted when at a high voltage level.
  • Page 15 Direction Type / Tolerance Notes LVDS LCD LVDS signaling used for LVDS LCD displays DC coupled differential signaling used for traditional (non- Super-Speed) USB signals USB SS LVDS signaling used for Super Speed USB 3.0 USB VBUS 5V 5V tolerant input for USB VBUS detection 10/100Base-TX Differential signaling, using MLT-3 (tri level) format for 100 MBit / Sec full duplex Ethernet...
  • Page 16 Power nets are labeled per the table below. The power rail behavior under the various system power states is shown in the table. Term Suspend Suspend Soft Off Mechanical to RAM to Disk VDD_IN  3.35V~5.25 3.35V~5.25 3.35V~5.25 3.35V~5.25 VDD_50  VDD_33  3.3V AUD_33 ...

  • Page 17: Document And Standard References

    1.3.3. Embedian Documents The following documents are listed for reference. The Module schematic is not usually available outside of Embedian, without special permission. The other schematics may be available, under NDA or otherwise. Contact your Embedian representative for more information. The SMARC T335X Evaluation Carrier schematic is particularly useful as an example of the implementation of various interfaces on a Carrier board.
  • Page 18 1.3.6. TI Software Documents  LINUXEZSDK-AM335x  ANDROIDDEVKIT-JB-AM335x 1.3.7. Embedian Software Documents  Embedian Linux BSP for SMARC T335X Module  Embedian Android BSP for SMARC T335X Module  Embedian Linux BSP User’s Guide  Embedian Android BSP User’s Guide 1.3.8.

  • Page 19: Intended Audience

    1.4 Intended Audience This design guide is intended for electronics engineers and PCB layout engineers designing Carrier Boards for SMARC T335X Modules. SMARC T335x Carrier Board Hardware Design Guide, Document Revision 1.2...
  • Page 20 Interfaces This chapter describes the signals and implementation guideline found on SMARC T335X connectors. Section includes：  SMARC T335X Connector Pin Mapping Ethernet Interface   USB Interface  Parallel RGB LCD Interface  SD/SDIO Interface  I2C Audio Interface ...

  • Page 21: Chapter 2 Interfaces

    Chapter 2 Interfaces There are 314 edge fingers of the SMARC module that mate with a low profile 314 pin 0.5mm pitch right angle connector (the connector is sometimes identified as a 321 pin connector, but 7 pins are lost to the key). The following table lists the module pin assignments for all 314 edge fingers.
  • Page 22 P-Pin Primary (Top) Side S-Pin Secondary (Bottom) Side GBE_MDI3+ AFB4_IN GBE_LINK100# AFB5_IN GBE_LINK1000# AFB6_PTIO GBE_MDI2- AFB7_PTIO GBE_MDI2+ GBE_LINK_ACT# SDMMC_D0 GBE_MDI1- SDMMC_D1 GBE_MDI1+ SDMMC_D2 GBE_CTREF SDMMC_D3 GBE_MDI0- SDMMC_D4 GBE_MDI0+ SDMMC_D5 SPI0_CS1# SDMMC_D6 SDMMC_D7 SDIO_WP SDIO_CMD SDMMC_CK SDIO_CD# SDMMC_CMD SDIO_CK SDMMC_RST# SDIO_PWR_EN AUDIO_MCK I2S0_LRCK SDIO_D0...
  • Page 23 P-Pin Primary (Top) Side S-Pin Secondary (Bottom) Side SPI0_DIN I2S1_CK SPI0_DO I2C_GP_CK SATA_TX+ I2C_GP_DAT SATA_TX- I2S2_LRCK I2S2_SDOUT SATA_RX+ I2S2_SDIN SATA_RX- I2S2_CK SATA_ACT# SPI1_CS0# AFB8_PTIO SPI1_CS1# AFB9_PTIO SPI1_CK PCAM_ON_CSI0# SPI1_DIN PCAM_ON_CSI1# SPI1_DO SPDIF_OUT SPDIF_IN USB0+ USB0- AFB_DIFF0+ USB0_EN_OC# AFB_DIFF0- USB0_VBUS_DET USB0_OTG_ID AFB_DIFF1+ USB1+ AFB_DIFF1-...
  • Page 24 P-Pin Primary (Top) Side S-Pin Secondary (Bottom) Side USB2- AFB_DIFF3+ USB2_EN_OC# AFB_DIFF3- PCIE_C_PRSNT# PCIE_B_PRSNT# AFB_DIFF4+ PCIE_A_PRSNT# AFB_DIFF4- <Key> <Key> PCIE_A_RST# PCIE_B_RST# PCIE_C_CKREQ# PCIE_C_RST# PCIE_B_CKREQ# PCIE_C_RX+ PCIE_A_CKREQ# PCIE_C_RX- PCIE_C_REFCK+ PCIE_C_TX+ PCIE_C_REFCK- PCIE_C_TX- PCIE_A_REFCK+ PCIE_B_REFCK+ PCIE_A_REFCK- PCIE_B_REFCK- PCIE_A_RX+ PCIE_B_RX+ PCIE_A_RX- PCIE_B_RX- PCIE_A_TX+ PCIE_B_TX+ PCIE_A_TX- PCIE_B_TX-...
  • Page 25 P-Pin Primary (Top) Side S-Pin Secondary (Bottom) Side LCD_D2 HDMI_D1+ LCD_D3 HDMI_D1- LCD_D4 LCD_D5 HDMI_D0+ LCD_D6 HDMI_D0- S100 LCD_D7 P100 S101 P101 HDMI_CK+ S102 LCD_D8 P102 HDMI_CK- S103 LCD_D9 P103 S104 LCD_D10 P104 HDMI_HPD S105 LCD_D11 P105 HDMI_CTRL_CK S106 LCD_D12 P106 HDMI_CTRL_DAT S107...
  • Page 26 P-Pin Primary (Top) Side S-Pin Secondary (Bottom) Side P119 GPIO11 S120 LCD_DE P120 S121 LCD_VS P121 I2C_PM_CK S122 LCD_HS P122 I2C_PM_DAT S123 LCD_PCK P123 BOOT_SEL0# S124 P124 BOOT_SEL1# S125 LVDS0+ P125 BOOT_SEL2# S126 LVDS0- P126 RESET_OUT# S127 LCD_BKLT_EN P127 RESET_IN# S128 LVDS1+ P128...
  • Page 27 P-Pin Primary (Top) Side S-Pin Secondary (Bottom) Side P144 CAN0_RX S145 WDT_TIME_OUT# P145 CAN1_TX S146 PCIE_WAKE# P146 CAN1_RX S147 VDD_RTC P147 VDD_IN S148 LID# P148 VDD_IN S149 SLEEP# P149 VDD_IN S150 VIN_PWR_BAD# P150 VDD_IN S151 CHARGING# P151 VDD_IN S152 CHARGER_PRSNT# P152 VDD_IN S153...
  • Page 28 Figure 2: SMARC T335X Connector Schematics I SMARC T335x Carrier Board Hardware Design Guide, Document Revision 1.2...
  • Page 29 Figure 3: SMARC T335X Connector Schematics II SMARC T335x Carrier Board Hardware Design Guide, Document Revision 1.2...

  • Page 30: Smarc T335X Connector Pin Mapping

    2.1 SMARC T335X Connector Pin Mapping The diagrams in the figures below show the pin numbering schema on both sides of the module and land pattern. The schema deviates from the unrelated MXM3 standard pin numbering schema and is compliant to SMARC specification version 1.0. Pins on the primary (top) side of the module have a label “P”...
  • Page 31 Figure 5: SMARC T335X edge finger secondary pins Figure 6: Pin numbering schema on the module connector land pattern The rest of the sections in this chapter describe the signals on SMARC MXM3 connector that is provided over the edge-fingers of the SMARC module. Refer to the SMARC Specification for information about this.

  • Page 32: Ethernet Interface

    2.2 Ethernet Interface SMARC hardware specification defines one 10/100/1000BaseT Gigabit Ethernet LAN port compliant with the IEEE 802.3ab standard and the other optional one in the Alternate Function Block (AFB). The interface is backward compatible with the 10/100Mbit Ethernet (10/100Base-TX) standard. The LAN interface of the SMARC module consists of 4 pairs of low voltage differential pair signals designated from 'GBE_MDI0' (+ and -) to 'GBE_MDI3' (+ and -) plus additional control signals for link activity indicators.
  • Page 33 2.2.1. Ethernet Signal The following table shows the Ethernet signals of LAN1. SMARC Edge Finger Type Power Description Rail Pin Name  Pin# GBE_MDI0+  Analogue 1000Base-T: DA+ 10/100Base-TX: Transmit + GBE_MDI0‐  Analogue 1000Base-T: DA- 10/100Base -TX: Transmit - GBE_MDI1+  Analogue 1000Base-T: DB+ 10/100Base -TX: Receive + GBE_MDI1‐ ...
  • Page 34 The following table shows the Ethernet signals of LAN2. SMARC Edge Finger Type Power Description Rail Pin Name  Pin# AFB_DIFF0+  Analogue 1000Base-T: DA+ (GBE1_MDI0+)  10/100Base-TX: Transmit + AFB_DIFF0‐  Analogue 1000Base-T: DA- (GBE1_MDI0‐)  10/100Base -TX: Transmit - AFB_DIFF1+  Analogue 1000Base-T: DB+ (GBE1_MDI1+)  10/100Base -TX: Receive + AFB_DIFF1‐ ...
  • Page 35 2.2.2. LAN Implementation Guidelines The most critical component in the LAN interface is the isolation magnetics connected directly to the MDI differential pair signals of the SMARC module. It should be carefully qualified for Return Loss, Insertion Loss, Open Circuit Inductance, Common Mode Rejection and Crosstalk Isolation to pass the IEEE conformance tests and EMI tests.
  • Page 36 2.2.2.1. Gigabit Ethernet LAN Magnetics Modules 1000Base-T Ethernet magnetics modules are similar to those designed solely for 10/100Base-Tx Ethernet, except that there are four MDI differential signal pairs instead of two. 1000Base-T magnetics modules have a center tap pin that is connected to the reference voltage output 'GBE_CTREF' of the SMARC module, which biases the controller's output buffers.
  • Page 37 2.2.2.2. Fast Ethernet (10/100Mbps) LAN Magnetics Modules SMARC T335X uses SMSC LAN8720A as LAN PHY layer chip. The following table is the magnetic sources that are qualified or suggested by SMSC. The manufacturer, part number, package, number of cores, operating temperature range and configuration are included for each suggested magnetic.
  • Page 38 Above are magnetics for normal temperature. For industrial temperature magnetics are listed below. SMARC T335X-I (LAN8720i) Qualified Magnetics Vendor Part Number Package Core Temp Configuration Pulse HX1188 16-pin HP Auto-MDIX SOIC Halo TG110-RPE5N5 16-pin HP Auto-MDIX SOIC Halo HFJ11-RPE26E-L12RL Integrated HP Auto-MDIX RJ45 TLA-6T717W...
  • Page 39 2.2.2.4. LAN Ground Plane Separation Isolated separation between the analog ground plane and digital ground plane is recommended. If this is not implemented properly then bad ground plane partitioning could cause serious EMI emissions and degrade analog performance due to ground bounce noise. The plane area underneath the magnetic module should be left empty.
  • Page 40 2.2.2.5. LAN Link Activity and Speed LED The SMARC module has three 3.3V open drain outputs to speed indication and link status LEDs. The 3.3V standby voltage should be used as LED supply voltage so that the link activity can be viewed during system standby state.
  • Page 41 2.2.3. LAN Reference Schematic 2.2.3.1. Gigabit Ethernet Schematic Example (Integrated Magnetics) The need for centre tap voltage depends on the Ethernet PHY used on the SMARC module. In order to keep the carrier board compatible with all SMARC modules, the centre tap pins of the magnetics should all be connected to the centre tap voltage source pin of the module connector (GBE_CTREF).
  • Page 42 2.2.3.2. Gigabit Ethernet Schematic Example (Discrete Magnetics) If discrete magnetics are used instead of a RJ-45 Ethernet jack with integrated magnetics, special care has to be taken to route the signals between the magnetics and the jack. These signals are required to be high voltage isolated from the other signals.
  • Page 43 Figure 10: Gigabit Ethernet with Discrete Magnetics Reference Schematic 2.2.3.3. 10/100Mbit Ethernet Schematic Example (Integrated Magnetics) The Fast Ethernet interface uses the MDI0 as transmitting lanes and the MDI1 as receiving lane. As most Ethernet PHYs feature Auto-MDIX, the signal direction RX and TX could be swapped. It is strongly recommend that RX and TX lanes are not swapped in order to ensure compatibility between all SMARC modules.
  • Page 44 Figure 11: Fast Ethernet with Integrated Magnetics Reference Schematic 2.2.4. Unused Ethernet Signals Termination All unused Ethernet signals can be left unconnected. SMARC T335x Carrier Board Hardware Design Guide, Document Revision 1.2...

  • Page 45: Usb Interface

    2.3 USB Interface The Universal Serial Bus interface of the SMARC module is compliant to USB 2.0 and backward compatible to USB 1.1 specification. SMARC specifies a minimum configuration of 1 USB client port that can be configured as host port or OTG port, and a minimum configuration of 1 USB host port up to a maximum of 2 ports.
  • Page 46 The table below shows the USB signals of USB1. SMARC Edge Finger Type Power Description Rail Pin Name  Pin# USB1+  3.3V Positive differential USB signal, OTG capable USB1‐  3.3V Negative differential USB signal, OTG capable USB1_EN_OC#  3.3V Enable signal for the bus voltage output in host mode and Over current input signal for the USB0 interface...
  • Page 47 2.3.2. USB Implementation Guidelines 2.3.2.1. USB Over-Current Protection and Power Enable Signal (USB_EN_OC#) The USB Specification describes power distribution over the USB port, which supplies power for USB devices that are directly connected to the carrier board. Therefore, the host must implement over-current protection on the ports for safety reasons.
  • Page 48 Carrier USB power switches have active-high power enables and active low open drain OC# outputs (as the TI and Micrel devices referenced do). The USB power switch Enable and OC# pins for a given USB channel are tied together on the Carrier. The USB power switch enable pin must function with a low input current.
  • Page 49 DP/DM lines. 3) If there is a USB over-current condition, the Carrier board USB power switch drives the USBx_EN_OC# line low. This removes the over-current condition (by disabling the USB switch enable input), and allows Module software to detect the over-current condition. 4) The Module software will look for a falling edge interrupt on USBx_EN_OC# to detect the OC# condition.
  • Page 50 2.3.2.2. EMI/ESD Protection To improve the EMI behavior of the USB interface, a design should include common mode chokes, which have to be placed as close as possible to the USB connector signal pins. Common mode chokes can provide required noise attenuation but they also distort the signal quality of full-speed and high-speed signaling.
  • Page 51 2.3.2.3. USB Client Considerations Precautions at the carrier board level must be taken to protect against voltage spikes and ESD to ensure robust operation of the host detection circuitry after multiple connect/disconnect events. A clamping diode may be used to minimize ESD, and a bulk capacitor should be placed on +5V USB client rail to avoid excessive voltage spikes.
  • Page 52 2.3.2.4 Routing Considerations for USB See SMARC T335X layout guide for trace routing guidelines and the SMARC specification for more information about this subject. 2.3.3. USB Reference Schematic 2.3.3.1. USB Host Reference Schematic The power distribution for the four USB host port in the example below is handled by an 'AIC1526' dual channel power distribution switch from Analog Integrations (http://www.analog.com.tw).
  • Page 53 Signal Description VCC  +5V Power Supply DATA‐  I/O USB Universal Serial Bus Data, negative differential signal. DATA+  I/O USB Universal Serial Bus Data, positive differential signal. GND  Ground GNDSHLD  Shield Ground GNDSHLD  Shield Ground 2.3.3.2. USB Client Reference Schematic The USB0_OTG_ID signal is used to detect which type of USB connector is plugged into the OTG jack (Mini-AB jack).
  • Page 54 require pull-ups. Figure 16: USB Client Reference Schematic 2.3.4. Unused USB Signals Termination All unused USB signals can be left unconnected. SMARC T335x Carrier Board Hardware Design Guide, Document Revision 1.2...

  • Page 55: Parallel Rgb Lcd Interface

    2.4 Parallel RGB LCD Interface 2.4.1. Parallel RGB LCD Signal The following table shows the 24-bit parallel RGB signal. SMARC Edge Finger Type Power Description Rail Pin# Pin Name  S111 LCD_D16  CMOS 3.3V LCD_D17  S112 CMOS 3.3V LCD_D18  Red LCD data signals (LSB: D16, S113 CMOS 3.3V...
  • Page 56 SMARC Edge Finger Type Power Description Rail Pin# Pin Name  LCD_D0  CMOS 3.3V LCD_D1  CMOS 3.3V LCD_D2  CMOS 3.3V LCD_D3  CMOS 3.3V Blue LCD data signals (LSB: D0, MSB: D7) LCD_D4  CMOS 3.3V LCD_D5  CMOS 3.3V LCD_D6  CMOS 3.3V S100 LCD_D7  CMOS 3.3V S120...
  • Page 57 2.4.2. Parallel RGB LCD Implementation Guide 2.4.2.1. LCD Data Line The parallel RGB interface can cause problems with EMC compliance when used with a high pixel clock frequency. This can be made worse if a display is connected over flat flex cables. Therefore, the flat flex cables should be kept as short as possible.
  • Page 58 2.4.2.2. LCD Color Mapping The 24bit color mapping is guaranteed to be compatible with other SMARC modules. LCD_D23, LCD_D15 and LCD_D7 are the most significant bits (MSBs) and LCD_D16, LCD_D8 and LCD_D0 are the least significant bits (LSBs) for the respective colors. To use displays which require fewer bits (e.g.
  • Page 59 SMARC Edge Finger 24-bit 18-bit 16-bit Pin# Pin Name  S111 LCD_D16  LCD_D17  S112 LCD_D18  S113 LCD_D19  S114 LCD_D20  S115 LCD_D21  S116 LCD_D22  S117 LCD_D23  S118 LCD_D8  S102 LCD_D9  S103 LCD_D10  S104 LCD_D11  S105 LCD_D12  S106 LCD_D13  S107 LCD_D14  S108 S109 LCD_D15  LCD_D0 ...
  • Page 60 2.4.2.3. I2C_LCD Some displays feature an I2C interface for reading out the EDID PROM or additional controls such as contrast and hue. If the carrier board provides no other display interface with DDC, it is recommended that the I2C_LCD on the SMARC module be used for the DDC. The I2C interfaces on the SMARC module are 3.3V logic level.
  • Page 61 2.4.3. Parallel RGB Reference Schematic 2.4.3.1. 18bit Parallel RGB Display Reference Schematic As described in previous section, for 18-bit LCD configuration, LCD_D16, LCD_D17, LCD_D8, LCD_D9, LCD_D0 and LCD_D1 will remain unused and LCD_D18, LCD_D10 and LCD_D2 become the LSBs for this configuration.
  • Page 62 2.4.3.2. LCD WLED Backlight Reference Schematic WLED driver IC utilizes the inductor/Schottky diode pumping method, incorporating a feedback system to monitor output current. Driver output frequency can be from 0.5 - 3 MHz and efficiencies are up to 92%, depending on usage. The driver IC handles the DC to DC conversion, and these ICs typically include an input for a PWM dimming signal.
  • Page 63 2.4.5. Carrier Based 18 bit Color Depth LVDS LVDS LCD operation is not native to the TI Sitara AM335x. In most cases, 18bit and 24 bit color mappings are not compatible. For 24 bit color mapping, the more common one, sometimes referred to as “24 bit standard color mapping”...
  • Page 64 Figure 20: Carrier Based 18-bit LVDS Connection The following table details exactly how the SMARC T335X parallel LCD pins are mapped to the on-carrier Texas Instruments SN75LVDS83B LVDS transmitter. For 18 bit displays, LVDS channels 0, 1, 2 are used. SMARC T335x Carrier Board Hardware Design Guide, Document Revision 1.2...
  • Page 65 SMARC Module LVDS Transmitter (TI Net Names 18-bit Edge Golden Finger SN75LVDS83B) standard color map Pin# Pin Name Pin# Pin Name LCD_D10  D7  LCD_D10  G0  S104 LCD_D23  D6  LCD_D23  R5  S118 LCD_D22  D4  LCD_D22  R4  S117 LCD_D21  D3  LCD_D21  R3  S116 LCD_D20 ...
  • Page 66 SMARC Module LVDS Transmitter (TI Net Names 18-bit Edge Golden Finger SN75LVDS83B) standard color map Pin# Pin Name Pin# Pin Name Not Used  D23  Not Used  Not Used  Not Used LCD_D1  D17  LCD_D1  Not Used  LCD_D0  D16  LCD_D0  Not Used  LCD_D9  D11  LCD_D9  Not Used  S103 LCD_D8 ...
  • Page 67 Figure 21: Carrier Based 24-bit LVDS Connection The following table details exactly how the SMARC T335X parallel LCD pins are mapped to the on-carrier Texas Instruments SN75LVDS83B LVDS transmitter. For 24 bit displays, channels 0, 1, 2 and 3 are used. SMARC T335x Carrier Board Hardware Design Guide, Document Revision 1.2...
  • Page 68 SMARC Module LVDS Transmitter (TI Net Names 24-bit Edge Golden Finger SN75LVDS83B) standard color map Pin Name Pin# Pin Name Pin# S102 LCD_D8  D7  LCD_D8  G0  S116 LCD_D21  D6  LCD_D21  R5  S115 LCD_D20  D4  LCD_D20  R4  S114 LCD_D19  D3  LCD_D19  R3 ...
  • Page 69 SMARC Module LVDS Transmitter (TI Net Names 24-bit Edge Golden Finger SN75LVDS83B) standard color map Pin Name Pin# Pin Name Pin# NC  D23  Not Used  Not Used  S100 LCD_D7  D17  LCD_D7  B7  LCD_D6  D16  LCD_D6  B6  S109 LCD_D15  D11  LCD_D15  G7  LCD_D14  D10 ...
  • Page 70 2.4.6.1. 24bit LVDS Display Reference Schematic To improve the EMI behavior of the LVDS interface, a design should include common mode chokes, which have to be placed as close as possible to the LVDS connector signal pins. Common mode chokes can provide required noise attenuation but they also distort the signal quality of full-speed and high-speed signaling.

  • Page 71: Sd/Sdio Interface

    application skew budget. A variety of shielding options are available. Ribbon cables are a cost effective and easy solution. Even though they are not well suited for high-speed differential signaling they do work fine for very short runs. Most cables will work effectively for cable distances of <0.5m. The cables and connectors that are to be utilized should have a differential impedance of 100Ω...
  • Page 72 2.5.1. SD/SDIO Signal The following table shows the SDIO signals. SMARC Edge Finger Type Power Description Rail Pin Name  Pin# SDIO_D0  CMOS 3.3V Data signals [3:0], used for SD, MMC and SDIO interfaces, add SDIO_D1  external49.9k ohm pull-up CMOS 3.3V resistors on carrier SDIO_D2 ...
  • Page 73 2.5.2. SD/SDIO Implementation Guidelines 2.5.2.1. ESD Protection To protect the SD interface of the module from over-voltage caused by electrostatic discharge (ESD) and electrical fast transients (EFT), it is highly recommended to use low capacitance steering diodes and transient voltage suppression diodes that must be implemented on the carrier board (for example...
  • Page 74 2.5.2.3. Routing Considerations for SD/SDHC interface See SMARC T335X layout guide for trace routing guidelines and the SMARC specification for more information about this subject. 2.5.3. SD/SDHC Reference Schematic The example shown below is implemented on the SMARC T335X evaluation carrier board.
  • Page 75 2.5.4. Unused SD/SDHC Signals Termination All unused SD interface signals can be left unconnected. SMARC T335x Carrier Board Hardware Design Guide, Document Revision 1.2...

  • Page 76: I2S Audio Interface

    2.6 I2S Audio Interface The SMARC specification defines minimum configuration of one (1) I2S interface up to a maximum of three (3) ports and one of them (I2S2) may alternatively be used to implement a HDA (High Definition Audio) channel. I2S interfaces are typically used for connection to I2S audio CODEC.
  • Page 77 I2S1 interface is not used in SMARC T335X. SMARC Edge Finger Type Power Description Rail Pin Name  Pin# I2S1_LRCK  Not Used I2S1_SDOUT  Not Used I2S1_SDIN  Not Used I2S1_CK  Not Used I2S2 interface is not used in SMARC T335X. SMARC Edge Finger Type Power Description...
  • Page 78 Figure 25: AIC3106 I2S Audio CODEC Reference Schematic 2.6.3. I2S Placement and Routing Guide The implementation of proper component placement and routing techniques will help to ensure that the maximum performance available from the codec is achieved. Routing techniques that should be observed include properly isolating the codec, associated audio circuitry, analog power supplies, and analog ground planes from the rest of the carrier board.
  • Page 79 the analog input and voltage reference pins.  Provide separate analog and digital ground planes with the digital components over the digital ground plane, and the analog components, including the analog power regulators, over the analog ground plane. The split between planes must be a minimum of 0.05 inch wide.

  • Page 80: Can Bus Interface

    2.7 CAN BUS Interface Controller Area Network (CAN or CAN-bus) is a message based protocol designed specifically for automotive applications but now is also used in other areas such as industrial automation and medical equipment. The SMARC specification defines two optionally CAN bus controller interfaces and T335X features one.
  • Page 81 2.7.2. CAN Interface Implementation Guidelines 2.7.2.1. CAN System Architecture A typical architecture of the CAN system is shown in following figure. A CAN interface controller is connected to the transceiver via a serial data output line (TX) and a serial data input line (RX). The transceiver is attached to the bus line via its two bus terminals CANH and CANL, which provide differential receive and transmit capability.
  • Page 82 The input Rs is used for mode control purpose. Both transceiver products are powered with a nominal supply voltage of +5 V. The CAN bus controller outputs a serial transmit data stream to the TxD input of the transceiver. An internal pull-up function sets the TxD input to logic HIGH i.e.
  • Page 83 2.7.2.2. EMI Protection Common-mode chokes or LC filter are frequently used in automotive CAN networks to increase system reliability with respect to EMC. EMI emitted from an end device through the CAN transceiver can be filtered, thus limiting unwanted high-frequency noise on the communication bus. Another reason for using a common-mode choke or LC filter is attempting improve susceptibility...
  • Page 84 2.7.3. CAN Interface Reference Schematic The example shown below is implemented on the SMARC T335X evaluation carrier board. The CAN transceiver used is from TI SN65HVD251D that has built-in 14kV ESD protection and a wide common-mode voltage range. Figure 28: CAN Interface Reference Schematic 2.7.4.

  • Page 85: Serial Com Port Interface

    2.8 Serial COM Port Interface The SMARC specification defines up to four asynchronous serial ports interface in CMOS logic level. The ports are designated SER0 ~ SER3. Ports SER0 and SER2 are 4 wire ports (2 data lines and 2 handshake lines). Ports SER1 and SER3 are 2 wire ports (data only).
  • Page 86 2.8.1. Serial COM Port Signals The following table shows the SER0 controller interface signals. SMARC Edge Finger Type Power Description Rail Pin Name  Pin# SER0_TX  P129 CMOS 3.3V Asynchronous serial port data out SER0_RX  P130 CMOS 3.3V Asynchronous serial port data in SER0_RTS# ...
  • Page 87 SER3 (Debug Port) interface is defined as follows. SMARC Edge Finger Type Power Description Rail Pin Name  Pin# SER3_TX  P140 CMOS 3.3V Asynchronous serial port data out SER3_RX  P141 CMOS 3.3V Asynchronous serial port data in 2.8.2. Asynchronous Interface Implementation Guidelines 2.8.2.1.
  • Page 88 2.8.2.2. EMI Protection An LC filter is frequently used in serial networks to increase system reliability with respect to EMC. EMI emitted from an end serial device through the RS232/RS422/RS485 transceivers can be filtered, thus limiting unwanted high-frequency noise on the communication bus. 2.8.2.3.
  • Page 89 Figure 30: RS232, RS422 and RS485 Reference Schematic 2.8.4. Unused Asynchronous Serial Signals Termination All unused asynchronous serial interface signals can be left unconnected. SMARC T335x Carrier Board Hardware Design Guide, Document Revision 1.2...

  • Page 90: Spi Interface

    2.9 SPI Interface The Serial Peripheral Interface (SPI) is a 4-pin interface that provides a potentially lower-cost alternative for system devices such as EEPROM and flash components. SMARC standard features two optional SPI ports. Each port defines two chip select signals that can connect up to two SPI devices. SMARC T335X features two SPI interfaces.
  • Page 91 SPI1 interface signal is defined as follows. SMARC Edge Finger Type Power Description Rail Pin Name  Pin# SPI1_CS0#  CMOS 3.3V SPI1 Master Chip Select 0 output SPI1_CS1#  CMOS 3.3V SPI1 Master Chip Select 1 output SPI1_CK  CMOS 3.3V SPI1 Master Clock output SPI1_DIN ...
  • Page 92 If multiple slave devices exist, the master generates a separate slave select signal for each slave. These relationships are illustrated in Figure 32. The master generates slave select signals using general-purpose discrete input/output pins or other logic. This consists of old-fashioned bit banging and can be pretty sensitive.
  • Page 93 2.9.2.1. Routing Considerations for SPI interface The SPI signal length on the SMARC carrier board should be no longer than 4.5 inches. It is recommended that you shorten your trace length as much as possible to attain the best signal quality. To reduce the length of the SPI trace, place the SPI device close to the MXM 3.0 board­to­board interconnectors.
  • Page 94 2.9.3. SPI Implementation Reference Schematic The example shown below is implemented on the SMARC T335X evaluation carrier board. SPI signals are presented in a 2.0mm header. A varistor is applied on each signal line and able to withstand ESD test of IEC-61000-4-2 and surge protection.

  • Page 95: I2C Bus Interface

    2.10 I2C BUS Interface Due to the simple two-wire serial bus protocol and the high availability of devices, the I2C Bus is a frequently used low speed bus interface for connecting embedded devices such as sensors, converters or data storage. The SMARC specification defines up to five I2C interfaces dedicated for power management (I2C_PM), camera (I2C_CAM), general purposes (I2C_GP), LCD display (I2C_LCD) and HDMI (HDMI_CTRL) support.
  • Page 96 I2C_GP interface signal is defined as follows. SMARC Edge Finger Type Power Description Rail Pin Name  Pin# I2C_GP_CK  CMOS 3.3V General purpose use I2C_GP_DAT  CMOS 3.3V General purpose use Both I2C_GP_CK and I2C_GP_DAT have a 2.2k pull-up resistor to 3.3V. I2C_LCD interface signal is defined as follows. SMARC Edge Finger Type Power...
  • Page 97 2.10.2. I2C Interface Implementation Guidelines 2.10.2.1. Terminations I2C_PM bus has a 2.2k pull-up to 1.8V on module. I2C_GP and I2C_LCD buses have a 2.2k pull-up to 3.3V on module. There is no need to pull up on carrier. 2.10.2.2. Routing Considerations for I2C Interface The I2C does not need to be routed as differential pair, but it is recommended not to separate the data and clock lines too much.
  • Page 98 Figure 34: I2C EEPROM Reference Schematic 2.10.4. Unused I2C Signals Termination All unused I2C signals can be left unconnected. SMARC T335x Carrier Board Hardware Design Guide, Document Revision 1.2...

  • Page 99: Selecting The Boot Mode

    2.11 Selecting the Boot Mode SMARC hardware specification defines three pins (BOOT_SEL[0:2]) that allow the Carrier board user to select from eight possible boot devices. SMARC Edge Finger Type Power Description Rail Pin Name  Pin# BOOT_SEL[0:2]#  I CMOS 3.3V Input straps determine the Module boot device.
  • Page 100 The boot mode selection of SMARC T335X is listed in the following table. Carrier Connection Boot Source BOOT_SEL2# BOOT_SEL1# BOOT_SEL0# Float Carrier SD Card Float Float Module eMMC Flash Float Float Carrier SPI The BOOT_SELx# configuration will be decoded to SYSBOOT on Note: module and recognized by AM335X.

  • Page 101: Watchdog Control Signals

    2.12 Watchdog Control Signals The simplest way to implement the watchdog timer is to utilize the AM335X internal WDT function. This function is available to users through the standard Linux Watchdog API. The Watchdog can be initialized and controlled by the API (Application Program Interface) called Embedded Application Software Interface (EASI).
  • Page 102 Figure 36: External WDT Control Circuitry Reference Schematic SMARC T335x Carrier Board Hardware Design Guide, Document Revision 1.2...
  • Page 103 Power Design Guideline This Chapter details the general power requirements and control signals. Section include： Power Signals   RTC Battery  Power Flow and Control Signals Block Diagram  Power States  Power Sequences  Layout Requirements Reference Schematics ...

  • Page 104: Chapter 3 Power Design Guideline

    Chapter 3 Power Design Guideline SMARC modules are designed to be driven with a single +3V to +5.25V input power rail. A +5V is recommended for non-battery operated system. Unlike Q7 module, there is no separate voltage rail for standby power, other than the very low current RTC voltage rail.
  • Page 105 3.1.2. Power Control Signals The input pins listed in the following table are all active low and are meant to be driven by OD (open drain) devices on the Carrier. The Carrier either floats the line or drives it to GND. No Carrier pull-ups are needed. The pull-up functions are performed on the Module.
  • Page 106 2 LAN signals. They will be used in a battery-operated system. The default configuration of T335X is LAN. If users would like to use these pins, contact Embedian representatives for more details. SMARC Edge Finger Type...
  • Page 107 SMARC Edge Finger Type Power Description Rail Pin# Pin Name  SLEEP# /  S149 CMOS 3.3V Sleep indicator from Carrier board. May be sourced from user RMII2_TXD0  Sleep button or Carrier logic. Carrier to float the line in in-active state. Active low, level sensitive. Should be de-bounced on the Module.

  • Page 108: Rtc Battery

    3.2 RTC Battery The Real Time Clock (RTC) is responsible for maintaining the time and date even when the SMARC module is not connected to a main power supply. RTC backup power is brought in on the VDD_RTC rail. The RTC consumption is typically 15 mA or less.

  • Page 109: Power Flow And Control Signals Block Diagram

    3.2.2. RTC Battery Lifetime The RTC battery lifetime determines the time interval between system battery replacement cycles. Current leakage from the RTC battery circuitry on the carrier board is a serious issue and must be considered during the system design phase. The current leakage will influence the RTC battery lifetime and must be factored in when a specific life expectancy of the system battery is being defined.
  • Page 110 When main power is supplied from the carrier, a voltage detector will assert VIN_PWR_BAD# signal to tell the module and carrier that the power is good. VDD_IO_SEL# will be pulled high on carrier that represents a 3.3V VDD_IO carrier. These two signals will turn on the PMIC on module to power on the module.

  • Page 111: Power States

    3.4 Power States The SMARC T335X module supports different power states. The table below describes the behavior in the different states and which power rails and peripherals are active. Additional power states can be implemented if required using available GPIOs to control additional power domains and peripherals. Abbr.

  • Page 112: Power Sequences

    running mode in two ways. The module main voltage rail (VDD_IN) can be removed and applied again. If needed, this could also be done with a button and a small circuit. SMARC T335X module supports being power cycled by asserting the RESET_IN# signal (e.g. by pressing the reset button or shunt and relief the reset jumper), please consult the associated module datasheet for more information about the support power cycle methods.
  • Page 113 VDD_IO_SEL# as soon as the main voltage supply is applied to the module and all module supplies necessary for module booting are up. This is to ensure that the module is powered before the main body of carrier circuits (those outside the power and power control path on the carrier) and the VDD_IO of module and carrier is matching.
  • Page 114 If the operating system supports it, a shutdown sequence can be initiated. Some systems may benefit from shutting down instead of just removing the main power supply as this allows the operating system to take care of any housekeeping (e.g. bringing mass storage devices to a controlled halt). Some operating system may not provide the shutdown function.
  • Page 115 When the RESET_IN# is asserted, a reset cycle is initiated. The module internal reset and the external reset output RESET_OUT# are asserted as long as RESET_IN# is asserted. If the reset input RESET_IN# is de-asserted, the internal reset and the RESET_OUT# will remain low for at least 1ms until they are also de-asserted and the module starts booting again.

  • Page 116: Layout Requirements

    3.6 Layout Requirements A proper power supply layout is essential for ensuring EMC compliance. If buck or boost converters are used on the carrier board, ensure any layout requirements as defined by the manufacturer of the devices are followed. Generally, application notes and reference designs carefully document and explain any such requirements.

  • Page 117: Reference Schematics

    Copper foils on the outer layers of a PCB (top and bottom layer) often are thicker due to the via plating process. A common value is one ounce of copper per square foot. This equals to a thickness of 35μm. The traces of on such layers have half the electrical resistance, which is 0.5m...
  • Page 118 Figure 44: Power Supply Reference Schematic SMARC T335x Carrier Board Hardware Design Guide, Document Revision 1.2...
  • Page 119 Floor Planning the PCB This Chapter gives mechanical information needed when designing the SMARC carrier board. Section include： Carrier Connector   Module and Carrier Connector Pin Numbering Convention  Module Outline – 82mm x 50mm Module  Module “Z” Height Consideration ...

  • Page 120: Chapter 4 Floor Planning The Pcb

    Chapter 4 Floor Planning the PCB 4.1 Carrier Connector Figure 45: MXM3 Carrier Connector SMARC T335x Carrier Board Hardware Design Guide, Document Revision 1.2...
  • Page 121 The Carrier board connector is a 314 pin 0.5mm pitch right angle part designed for use with 1.2mm thick mating PCBs with the appropriate edge finger pattern. The connector is commonly used for MXM3 graphics cards. The SMARC Module uses the connector in a way quite different from the MXM3 usage. Vender Vendor P/N Stack...
  • Page 122 Vender Vendor P/N Stack Body Contact Body Height Height Plating Style Color Foxconn AS0B821-S55B - *H 2.7mm 5.5mm Flash Black Foxconn AS0B821-S55N - *H 2.7mm 5.5mm Flash Ivory Foxconn AS0B826-S55B - *H 2.7mm 5.5mm 10 u-in Black Foxconn AS0B826-S55N - *H 2.7mm 5.5mm 10 u-in...

  • Page 123: Module And Carrier Connector Pin Numbering Convention

    MXM3 standard gangs large groups of pins together to provide ~80W capable power paths needed for X86 graphics cards. The SMARC module “ungangs” these pins to allow more signal pins. Footprint and pin numbering information for application of this 314 pin connector to SMARC is given in the sections below.
  • Page 124 Figure 46: SMARC T335X Module Mechanical Outline SMARC T335x Carrier Board Hardware Design Guide, Document Revision 1.2...

  • Page 125: Module "Z" Height Consideration

    4.4 Module “Z” Height Consideration Note from Figure 46 Module Mechanical Outline above that the component height on the Module is restricted to a maximum component height of 2.9mm on the Module Primary (Top) side and to 0.9mm on the Module Secondary (Bottom) side.

  • Page 126: Carrier Board Connector Pcb Footprint

    4.5 Carrier Board Connector PCB Footprint Figure 48: Carrier Board Connector PCB Footprint Note: The hole diameter for the 4 holes (82mm x 50mm Module) or 7 holes (82mm x 80mm Module) depends on the spacer hardware selection. See the section below for more information on this. SMARC T335x Carrier Board Hardware Design Guide, Document Revision 1.2...

  • Page 127: Module And Carrier Board Mounting Holes - Gnd Connection

    4.6 Module and Carrier Board Mounting Holes – GND Connection It shall be possible to tie all Module and Carrier board mounting holes to GND. The holes should be tied directly to the GND planes, although Module and Carrier designers may optionally make the mounting hole GND connections through passive parts, allowing the mounting holes to be isolated from GND if they feel it necessary.
  • Page 128 SMTSO (“surface mount technology stand offs”). The shortest standard length offered is 2mm. A custom part with 1.5mm standoff length, M2.5 internal thread, and 5.56mm standoff OD is available from PEM. The Carrier PCB requires a 4.22mm hole and 6.2mm pad to accept these parts. Other vendors such as RAF Electronic Hardware (www.rafhdwe.com) offer M2.5 compatible swaged standoffs.
  • Page 129 DISCLAIMER: Copyright © Embedian, Inc. All rights reserved. All data is for information purposes only and not guaranteed for legal purposes. Information has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. Brand and product names are trademarks or registered trademarks of their respective owners.

Table of Contents