LSI DMN-8600 Technical Manual

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TECHNICAL

MANUAL

DMN-8600

DVD Recorder

System Processor

J u l y 2 0 0 2

Preliminary-3

LSI Logic Conﬁdential

Table of Contents

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Summary of Contents for LSI DMN-8600

Page 1 TECHNICAL MANUAL DMN-8600 DVD Recorder System Processor J u l y 2 0 0 2 Preliminary-3 LSI Logic Conﬁdential ®...
Page 2 LSI Logic; nor does the purchase or use of a product from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or third parties.
Page 3 Overview, deﬁnes DMN-8600 features and introduces its main applications. • Chapter 2, Application Example, describes the common user interface shared by all DMN-8600 applications and provides a listing of components needed to complete the design. • Chapter 3, Internal Architecture, gives an overview of the main modules and their external interfaces.
Page 4 AC timing; includes pin list alphabetized according to both pin name and pin bondout location. • Chapter A, Register Listing, is an index of the DMN-8600 registers. Preface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 5 LOW are marked with an overbar symbol. Hexadecimal numbers are indicated by the preﬁx “0x” —for example, 0x32CF. Binary numbers are indicated by the preﬁx “0b” —for example, 0b0011.0010.1100.1111. Preface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 6 Special Edition - 2nd Edition October 2, 2001 DB14-000198-00 Preliminary Edition January 31, 2002 DB14-000198-01 Preliminary-2 Edition. Chapter 15 expanded, etc. July 31, 2002 DB14-000198-02 Preliminary-3 Edition. Assorted changes made. Preface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 7: Table Of Contents
IEEE 1394 Interface 4.4.4 Video Interface 4.4.5 Audio Interface 4.4.6 SDRAM Interface 4.4.7 Serial I/O Interface 4.4.8 JTAG Interface (Test Access Port) Graphics Accelerator DMN-8600 DVD Recorder System Processor Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 8 Outgoing Transfers from DMN-8600 Device 8-10 Power Management 8-10 Host Interface Registers 8-11 8.6.1 Host Interface Control Register 8-12 8.6.2 Version Register 8-16 8.6.3 Host DMA Data Register 8-17 viii Contents Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 9 Incoming FRAME Transfers FIFO and Buffer Operation Secondary Bitstream Interface Registers 9.5.1 Secondary Bitstream Conﬁguration Register 9.5.2 Secondary NextAddress Register (CBus Addr: 0x080824) 9-11 9.5.3 Secondary Stop Address Register Contents Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 10 Video Control Register 11-6 Chapter 12 Audio Interface 12.1 Data, Serial Clocks and FSYNC 12-2 12.1.1 MCLK 12-2 12.1.2 IEC-958 Encoder 12-2 12.2 Audio Input Control Register 12-3 Contents Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 11 SDRAM Timing 13-17 Chapter 14 Bitstream I/O (Storage) Port 14.1 ATAPI Interface 14-2 14.1.1 Read Cycle 14-2 14.1.2 Write Cycle 14-3 14.1.3 DMA Operation 14-3 14.2 SD Interface 14-7 Contents Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 12 15.5.7 Reserved Registers (SIO UART2) 15-104 Chapter 16 Clock Control and Power Management 16.1 Clock and Power Registers 16-3 16.2 Main PLL Power Down and Wake-Up Sequence 16-12 Contents Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 13 18.2.16 SBP Interface Timing 18-47 18.3 Pin Description 18-50 18.4 Package Mechanical Speciﬁcations 18-70 18.4.1 Package Dimensions 18-70 18.4.2 Recommended Manufacturing Conditions 18-72 Chapter A Register Listing Customer Feedback Contents xiii Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 15 11.2 Video Output Channel Data Flow 11-3 11.3 Output Field/Frame Format 11-5 11.4 Single Video Stream 11-6 11.5 ITU-R BT.656 Timing 11-6 12.1 Location of FRFORM 1 Status 12-22 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 16 Device-Paced Async Master Write Cycle in 68K Mode 18-9 18.9 Device-Paced Async Master Read Cycle in SRAM Mode 18-10 18.10 Device-Paced Async Master Write Cycle in SRAM Mode 18-11 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 17 18-48 18.43 SBP Outgoing Transfer (POL = 0, WRREQ = 0) 18-49 18.44 308-Pad BGA Pinout (Sheet 1 of 2) 18-66 18.45 308-Pin BGA Package Mechanical Dimensions 18-71 xvii Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 19 Absolute Maximum Ratings 18-1 18.2 Operating Conditions 18-2 18.3 DC Characteristics 18-3 18.4 Miscellaneous Timing Values 18-5 18.5 Async Host Master Timing Parameters - Master Mode Only (Master replaces Slave) 18-12 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 20 18.32 1394 AC Timing Parameters at the Link 18-46 18.33 SBP Timing Parameters 18-49 18.34 DMN-8600 Pin List 18-51 18.35 308 BGA Alphabetical Pin List 18-68 18.36 Recommended Hot Air or IR Solder Reﬂow Conditions 18-72 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 21 MPEG-1, MPEG-2 and DV compressed images. The DMN-8600 can also be used as a powerful audio processor that encodes audio into M1L2 and MP3 formats, and decodes AC3, M2L2, DTS, DVD-Audio, and MP3 formats.
Page 22 NTSC, PAL, ITU-R BT.656/601 Input One 8-bit video stream at 27 MHz Output One 8/16-bit video stream at 27 MHz, with progressive scan output support at 54 (480P) MHz. Overview Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 23 IEEE 1149.1 compliance for boundary scan testing and board JTAG assembly testing Finally, the DMN-8600 achieves a high level of performance through system-on-chip (SOC) levels of integration. In addition to the audio and video codec, the DMN-8600 also integrates host, graphics and I/O processor subsystems.
Page 24 LSI Logic Conﬁdential Through such high integration, the DMN-8600 is capable of a high degree of concurrency. Examples of this are simultaneous encoding and decoding in MPEG-2 MP@ML format, simultaneous decoding to MPEG-2 MP@ML and transcoding to DV25, multi-angle view decoding, DV25 to MPEG-2 with zero delay preview, CD-DA to MP3 transcoding, as well as IEEE1394 transport stream muxing and demuxing.
Page 25: System Block Diagram For A Dmn-8600-Based Advanced
The only major components needed to complete the design are: • 8 to 64 Mbytes SDRAM • TV tuner • Analog video encoder and decoder DMN-8600 DVD Recorder System Processor Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 26 DVD-RAM or other read/writeable DVD drives in dual loader conﬁguration mode, or in combination with a hard disk drive. The DMN-8600 is able to record a single input, either from a TV tuner, the IEEE1394 link, or the ATAPI interface, in MPEG-1 or MPEG-2 format.
Page 27 Storage device interface controller for IDE/ATAPI devices or non-ATAPI devices (low-cost optical loaders) • IEEE1394 link layer interface (with 5C encryption) to a required external Physical Layer chip DMN-8600 DVD Recorder System Processor Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 28: Dmn-8600 Internal Architecture Diagram
Motion Video DSP Video Memory Estimator Interface Controller 8/16 Memory Memory CBus 1394 Audio Host Storage 2 Port Link Interface Interface Interface Interface 4 Port S/PDIF 16/32 Internal Architecture Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 29: Functional Description
DMA transfers. Each SPARC processor delivers 150 MIPS of processing power. Video Processing As a highly integrated network media processor engine, the DMN-8600 is designed to implement motion-compensated, block-DCT-based video compression algorithms. To this end, the DMN-8600 includes a Video DMN-8600 DVD Recorder System Processor Copyright ©...
Page 30: Motion Estimation Coprocessor
63-bit MAC units with 32-bit precision, and a DSP instruction set to support efﬁcient encoding and decoding of a wide variety of audio algorithms. These include MPEG-1 Layer 2, DTS, MP3, AC-3, AAC, etc., Functional Description Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 31: Interfaces And I/O
(DSP instruction) and a regular SPARC processor instruction; e.g., there can be an overlap between the load-and-store operations and the multiply-and- accumulate operations. Interfaces and I/O The DMN-8600’s connections to the outside world are summarized in Figure 4.1. The following subsections brieﬂy describe each corresponding interface.
Page 32: Host Interface
The host communication functions include initializing the DMN-8600, downloading microcode to the local SDRAM, sending commands, monitoring status, and downloading graphics data such as OSD bitmaps. Functional Description Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 33: Bitstream/Storage Interface
WR) to indicate whether a transfer is a read or a write. In M mode, the decoder requires one direction signal (RD or WR) and a data strobe. This selection allows the DMN-8600 to operate with most popular microcontrollers.
Page 34: Ieee 1394 Interface
4.4.4 Video Interface The video interface is a programmable high-speed I/O port that supports the transfer of uncompressed digital video into and out of the DMN-8600 processor. It captures one stream of 8-bit digital video data from an Functional Description...
Page 35: Audio Interface
4.4.5 Audio Interface The DMN-8600 has a dual serial audio input port capable of two channels of audio input for stereo recording, and four serial audio output ports capable of eight channels of audio output for up to eight channel surround sound reproduction.
Page 36: Serial I/O Interface
4 M x 32 SDR or DDR SDRAMs or two to four 8 M x 16 SDR or DDR SDRAMs. The DMN-8600 uses its external SDRAM to store both code and data, allowing memory allocation to be under complete software control. For example, when encoding MPEG video, the SDRAM contains: •...
Page 37: Jtag Interface (Test Access Port)
IEEE standard 1149.1. The JTAG interface provides for boundary scan testing utilizing a multiplexor and latches on every pin of the DMN-8600 device that can be forced to a known state. The actual data that is latched depends on multiplexor functions controlled by the TAP (test access port) controller.
Page 39 Chapter 5 Programmability (C-Ware) The DMN-8600 is a programmable device. It is compatible with the LSI Logic unique C-Ware environment. C-Ware is an object oriented software architecture that abstracts the underlying hardware. This promotes portability and application reusability within and across LSI Logic product families.
Page 40 Support for an external, generic host (16- or 32-bit) is provided through a set of generic host APIs. All components and ﬂow controllers provided by LSI Logic are fully optimized for performance and code compactness. Note: The DMN-8600 shares its API with LSI Logic ZiVA®-5 family of products, enabling the development and porting of Playback navigation from either platform to the other.
Page 41 This chapter describes the signals that comprise the external physical interface to the DMN-8600. Figure 6.1 shows a diagram of the DMN-8600 with all external interface signals grouped together. Table 6.1 provides the pin name, pin number, type, and description of each signal.
Page 42: Dmn-8600 System Interfaces
SIO_SPI_MOSI ATAPI_DMAACK SIO_SPI_MISO (Serial I/O) SIO_IRTX1 SIO_SPI_CS[3:0] SIO_IRTX2 (Serial I/O) SIO_IRRX SIO_SDA (Serial I/O) SIO_SCL SIO_UART1_TX SIO_UART1_RX TRST UART1 SIO_UART1_RTS Boundary SIO_UART1_CTS Scan (JTAG) SIO_UART2_TX UART2 SIO_UART2_RX Signal Descriptions Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 43 RREF Analog reference resistor. Connecting to pin VSS_RREF through a 1.18 K ± 1% resistor is recommended. C6, B5, B4, C5, No connect. D6, A4, B1, A3, A6, D2 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 44 Analog ground for internal clock DLL. VSS_RREF Analog ground for the internal Bandgap block. VSS_A C8, A8, C9, A9 Analog ground for isolated analog supplies. VSS_X Ground for crystal oscillator supply. Signal Descriptions Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 45 MCONFIG[1:0] = 00 = Async slave only. MCONFIG[1:0] = 01 = Async slave + Async master (no UART1, SPI, IRTX). MCONFIG[1:0] = 10 = Async master only. Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 46 32 MBytes x 1 [15] [13:0] 16 MBytes x 2 [15:14] [13:0] 16 MBytes x 1 [15] [13:0] 8 MBytes x 2 [15:14] [12:0] 8 MBytes x 1 [15] [12:0] Signal Descriptions Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 47 VI_D[9:2] pins. The data order is either (Cb, Y, Cr, Y) or (Y, Cb, Y, Cr) as selected by the Yﬁrst bit in the video control register. Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 48 54 MHz for 8-bit data and 27 MHz for 16-bit data. VO_CLK is asynchronous to all other chip clocks, 0 to 74.25 MHz. Signal Descriptions Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 49 AI_FSYNC determines the start or end of the next input sample or frame as speciﬁed by frForm in the audio input control register. AI_FSYNC can be internally or externally generated. Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 50 M_UWE/UDS. H_RD Host I-mode read strobe. This pin (slave) is shared with M_GPIO[4]. H_RD/WR Host I-mode write strobe/M-mode direction signal. H_RD/WR (slave) is shared with M_RD/WR. 6-10 Signal Descriptions Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 51 Master muxed address [21:6] and data [15:0]. These M_D[15:0] V10, Y12, V12, pins are shared with H_DATA[15:0] (slave) pins. W11, U11, V13, W12, U12, Y14, V14, W13, W14, W15 6-11 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 52 M_ALE Master address latch enable. M_WAIT Master ready. This pin is shared with H_WAIT. M_DTACK Master data transfer acknowledge. This pin is shared with H_DTACK. 6-12 Signal Descriptions Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 53 Multiplexed with ATAPI_INTRQ. SD_ERROR The DSP asserts this signal to indicate that an error has occurred. If DSP does not provide an error signal, ground this pin. Multiplexed with ATAPI_DMARQ. 6-13 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 54 ATAPI I/O read request. This pin is shared with SD_RDREQ. ATAPI_INTRQ Device interrupt request. This pin is shared with SD_ACK. ATAPI_IORDY Device I/O ready. This pin is shared with SD_CLK. 6-14 Signal Descriptions Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 55 SPI master out slave in. Multiplexed with M_A[25]. SIO_SPI_MISO SPI master in slave out. Multiplexed with M_A[1]. SIO_SPI_CS[3:0] W18, V16, V18, SPI chip selects. Multiplexed with M_A[24:22], M_A[5]. 6-15 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 56 TRST Test reset. BST reset - resets the TAP controller. This signal must be pulled high during normal mode. Test data Out. BST serial data output. 6-16 Signal Descriptions Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 57 (TAP) controller. Test clock. Boundary scan test (BST) serial data clock. 1. I - input, O - output, OD - open drain, PU - requires external pull-up resistor. 6-17 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 59: Memory Mapping
Section 7.3, “Control Bus Address Mapping” Host Interface Address Mapping A 32-bit address is used to access either the SDRAM or the CBus registers, as shown in Figure 7.1. DMN-8600 DVD Recorder System Processor Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 60: Sparc Processor Address Mapping
7.2.1 In System with an External Master Processor DMN-8600 SPARC processors boot from SDRAM — the external master must load SPARC boot code into SDRAM via the DMN-8600 device’s Host Interface. Figure 7.2 shows the resulting memory map. Memory Mapping...
Page 61: In System With No External Master Processor
256 Mbyte SDRAM Space 0000_0000 7.2.2 In System with No External Master Processor DMN-8600 SPARC processors boot from an external ROM. Figure 7.3 shows the resulting memory map. SPARC Processor Address Mapping Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 62: Control Bus Address Mapping
24-bit address offset is used to index into the CBus space shown in Figures through 7.3. Table 7.1 shows the assignments of these blocks to the various modules within the DMN-8600 device. Memory Mapping Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 63 0xC3_0000–0xC3_FFFF DSP DMem 0xC4_0000–0xC4_FFFF Video I/O 0xC5_0000–0xF8_FFFF Reserved 0xF9_0000 –0xF9_FFFF Reserved 0xFA_0000–0xFA_FFFF Reserved 0xFB_0000–0xFB_FFFF Bitstream I/O 0xFC_0000–0xFC_FFFF Audio DSP 0xFD_0000–0xFD_FFFF Video SPARC Processor 0xFE_0000–0xFF_FFFF reserved Control Bus Address Mapping Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 65: Host Slave Interface
8.1) that provides local DRAM and control register access to an external microcontroller (Host) which may perform various control functions at the system level. DMN-8600 DVD Recorder System Processor Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 66 In this conﬁguration, master accesses can be performed in parallel with host accesses to allow code download from an external PROM without interfering with host processing. Host Slave Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 67 50 Mbytes/s. The microcode must ensure that the internal DMA channel is programmed to match the transfers being performed by the host. Each interface is described in the following sections Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 68: Async Slave Interface With Host Dma
LSI Logic Conﬁdential Async Slave Interface with Host DMA The ﬂexible DMN-8600 Host bus interface offers many options for conﬁguring the following host interface controls: • Conﬁgurable 16/32-bit demultiplexed address/data bus • Separate WR or RD strobes (I-mode) or single CS strobe with a single WR signal (M-mode) •...
Page 69: Transfer Mode B
The Host drives the address and CS (1), and asserts WR (2) after the address and chip select are stable. • The DMN-8600 processor asserts both WAIT and DTACK from a 3-state level to a high level (shaded area is 3-state) (3) in response to the assertion of WR.
Page 70: I-Mode Outgoing Transfers
The Host deasserts WR (5) in response to either the WAIT deassertion or DTACK assertion. • The DMN-8600 processor uses the LOW-to-HIGH edge of WR (6) to latch in data and to stop driving WAIT. • The DMN-8600 processor deasserts DTACK, then stops driving DTACK on the LOW-to-HIGH edge of WR.
Page 71: M-Mode Write And Read Operations
The processor then deasserts WAIT (4) and asserts DTACK when it is ready to take data in. • The Host deasserts CS (5) in response to either the WAIT deassertion or DTACK assertion. Async Slave WRITE and READ Protocols Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 72: M-Mode Outgoing Transfers
LSI Logic Conﬁdential • The DMN-8600 processor uses the LOW-to-HIGH edge of CS to latch in data and to stop driving WAIT (6). • The DMN-8600 processor deasserts DTACK, then stops driving DTACK on the LOW-to-HIGH (7) edge of CS.
Page 73: Host Dma Read/Write Protocol
SDRAM and the Host register. The BSRD bit in the Host Conﬁguration register controls the direction of the bitstream transfers for the primary bitstream interface. The Host DMA Read/Write Protocol Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 74: Incoming Transfers To Dmn-8600 Device
Any DMA read that occurs when H_DMAREQ is deasserted will result in undetermined data (that is, spurious data). Power Management When DMN-8600 is in standby mode, asserting the CS pin causes a chip reset, which clears standby mode and reactivates the internal PLL. 8-10 Host Slave Interface Copyright ©...
Page 75: Host Interface Registers
Host Data Register [31:0] 0x4/0x5 Host Address Register [31:0] Host Address Register [31:0] Host DMA Data Register [31:0] Host DMA Data Register [7:0, 15:8, 23:16, 31:24] Reserved Reserved Host Interface Registers 8-11 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 76: Host Interface Control Register
If LE is set, then host DMA transfers between SDRAM and the host DMA data register are byte swapped, other- wise they are not swapped. 8-12 Host Slave Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 77 0. VDSP VDSP Reset A self clearing writable bit that resets the DMN-8600 Video DSP including the instruction and result queues. Host Interface Registers 8-13 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 78 (when the host resets this bit) since pend- ing RISC core transactions are left in an undeﬁned state. 1 = Drive H_INT pin LOW. 0 = H_INT pin is ﬂoating. 8-14 Host Slave Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 79 It is not possible to predict when a write to CPURst and/or ChipRST takes effect relative to other events in the DMN- 8600 processor due to the unpredictable latency of the DMN-8600 internal bus arbitration. Host Interface Registers 8-15 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 80: Version Register
It is accessible as a Host space register using H_ADDR[2:0], or as a CBus register. The initial value is 0x0900. Version Register Address: 0x1 (Host space) 0x60044 (CBus) Version Stepping Information 8-16 Host Slave Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 81: Host Dma Data Register
The Host DMA Data Register is used when the Host conﬁgures the DMN-8600 processor as a DMA target to transfer bitstream data to and from the DMN-8600 device. It is accessible only as a Host space register at address 0x6 via H_ADDR[2:0].
Page 82: Host Data Registers
ﬁrst followed by a read to 0x3. When performing a write to a new address, write to the 0x2 data register then write to 0x3. 8-18 Host Slave Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 83 32-bit write by combining the data with the 0x2 data register. Writing the 0x2 Host data register triggers a write in 32-bit host mode; however, in 16-bit host mode only the host register is updated. Host Interface Registers 8-19 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 84: Host Address Register
4 after each read or write of the data register that triggered the SDRAM access. Table 8.4 shows the auto-increment support of the Host Address Register. 8-20 Host Slave Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 85: Auto-Increment Support Of Host Address Registers
Read ADR = 0x2 Autoincrement Autoincrement Read ADR = 0x3 No autoincrement Autoincrement Write ADR = 0x2 No autoincrement Autoincrement Write ADR = 0x3 Autoincrement Autoincrement Host Interface Registers 8-21 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 86: Host Dma Registers
1 = Host completion interrupt enabled 0 = Host completion interrupt disabled GO is set by microcode or by the host processor to begin host DMA transfers. 8-22 Host Slave Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 87 If BSRD is clear, the Host DMA transfers are written by the system. BSRD should not be changed while the GO bit is set. 1 = DMN-8600 processor outputs the DMA data Host DMA Registers 8-23 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 88: Host Dma Nextaddress Register
Reloads of the stop address must be synchronized with DMA completion detection so that the DMA operation is not restarted after the GO bit is cleared or a completion interrupt is generated. 8-24 Host Slave Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 89: Host Dma Baseaddress And Limitaddress Registers (Cbus Address: 0X6006C And 0X60070)
Bits [15:8] of MData are swapped with [7:0]. 1 = Transfers byte swapped 0 = Transfer not byte swapped Master DMA Registers 8-25 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 90 GO bit was cleared by software. Note: The GO bit should be cleared, only if necessary, and read as zero before software changes the value of BSRD or any 8-26 Host Slave Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 91: Master Dma External Address Register
DMA data will be stored or read. As data is transferred, this register is updated if Ainc is set in the master DMA conﬁguration register. The two Master DMA Registers 8-27 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 92: Master Dma Nextaddress Register
(Cbus Address: 0x6F00C and 0x6F010) The master DMA base address register at control bus address 0x6F00C speciﬁes the SDRAM address for the beginning of the master DMA 8-28 Host Slave Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 93 DMA limit address register, it is reloaded with the master DMA base address register value before transferring additional data. The two least signiﬁcant and the upper four bits of these registers must be zero. Master DMA Registers 8-29 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 95: Secondary Bitstream Interface
Transfers are clocked from the rising edge of SBP_CLK. The direction of the port is controlled by the BSRD bit in the Secondary Bitstream Conﬁguration register. (See Figure 9.1). DMN-8600 DVD Recorder System Processor Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 96: Secondary Bitstream Port (Sbp)
HIGH active LOW SBP_RD WRREQ = 1 SBP_ACK active HIGH active LOW active HIGH active LOW SBP_REQ active HIGH active LOW SBP_RD active HIGH active LOW Secondary Bitstream Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 97: Wrreq = 0
Figure 9.2 shows outgoing transfers from the bitstream port with WRREQ = 0, POL = 1 and BSRD = 1. In the ﬁgure, note that SBP_ACK and SBP_REQ are shown as active LOW. The DMN-8600 processor drives SBP_DATA. Figure 9.2...
Page 98: Bitstream Input - Incoming Transfers (Bsrd = 0)
FIFO at the end of the clock. As long as the DMA operation is enabled and SBP_CLK is running at 27 MHz or slower while the DMN-8600 internal clock is running at 148.5 MHz, SBP_REQ will be asserted continuously. This allows a non-ﬂow-controlled transfer to be used, if necessary.
Page 99: Wrreq
For outgoing FRAME transfers, the following occurs: • SBP_FRAME is asserted on the ﬁrst clock of all outgoing packets (outgoing transfers are assumed to start on a packet boundary). WRREQ = 1 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 100: Incoming Frame Transfers
If zero stufﬁng occurs and the contents of the Next Address register equals the contents of the Stop Address register: – The GO bit in the bitstream conﬁguration is cleared. Secondary Bitstream Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 101: Fifo And Buffer Operation
SDRAM in the form of a circular buffer (see Figure 9.6). Figure 9.6 Circular Buffer Limit Limit Stop Next Next Stop Base Base Next < Stop Next > Stop FIFO and Buffer Operation Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 102 If WRREQ is set, the SBP_REQ pin is redeﬁned as a DMA write request, which is only asserted on outgoing transfers when the bitstream FIFO is not empty. Secondary Bitstream Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 103: Secondary Bitstream Interface Registers
The number of bytes to capture can be pre- computed at the beginning of the transfer. 1 = Host completion interrupt enabled 0 = Host completion interrupt disabled Secondary Bitstream Interface Registers Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 104 If POL and WRREQ are set, the SBP_RD, SBP_REQ and SBP_ACK pins are active LOW; otherwise, they are active HIGH. 1 = SBP_RD/SBP_REQ/SBP_ACK are active HIGH 0 = SBP_REQ/SBP_ACK are active LOW 9-10 Secondary Bitstream Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 105: Secondary Bitstream Configuration Register
Limit Address register. The two least signiﬁcant and the upper four bits of this register must be zero. Secondary Bitstream Interface Registers 9-11 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 107: Host Async Master Interface
SDRAM to zero. The SCPU rst bit will remain set after reset to allow the host processor to download microcode before booting. DMN-8600 DVD Recorder System Processor 10-1 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 108: Host (Slave) Plus Limited Master
SCPU rst bit is cleared after reset, causing the system SPARC to begin fetching instructions from a PROM at address zero. 10-2 Host Async Master Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 109: Cycle Types
HIGH during a write. D[7:0], is used in the transfer. Figure 10.1 shows the basic operation of these two cycle types. Cycle Types 10-3 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 110 68K Mode Write 68K Mode Burst Read BH CSO BH CSO M_CS M_UWE/LWE M_OE M_DTACK SRAM Mode Write SRAM Mode Burst Read SRAM Mode Read 10-4 Host Async Master Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 111: Transfer Acknowledge Mode
For device-paced accesses, the master waits a programmed amount of time before sampling M_DTACK or M_WAIT, as described in Section 10.4.5, “Device-Paced Transfers,” page 10-8. Cycle Types 10-5 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 112 68K Mode Write 68K Mode Burst Read BH CSO BH CSO M_CS M_UWE/LWE M_OE M_WAIT SRAM Mode Write SRAM Mode Burst Read SRAM Mode Read 10-6 Host Async Master Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 113: Timing Parameters
Multiplexed address set up time from address and M_ALE asserted to fall of M_ALE. 0–1 Multiplexed address hold time from fall of M_ALE to Addr/Data change. Cycle Types 10-7 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 114: Burst Transactions
These devices drive the M_DTACK or M_WAIT signal themselves, instead of relying on the host to self-time the transfer. Figure 10.3 shows an example of this kind of cycle. 10-8 Host Async Master Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 115 When using device-paced transfers, the DT timing parameter controls the delay before the master begins sampling M_DTACK or M_WAIT. This is most useful when the data acknowledge strobe is a M_WAIT signal, Cycle Types 10-9 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 116: Multiplexed Address Cycles
M_DTACK. 10.4.6 Multiplexed Address Cycles The DMN-8600 multiplexes the middle address bits 21 to 6 on the Addr/Data lines. For these cycles, the address bits are captured with an external latch. An address latch enable pin (M_ALE) is provided to control the latch.
Page 117: Chip Select Configuration Registers
10.5 Chip Select Conﬁguration Registers The DMN-8600 has six chip select pins, M_CS[5:0]. Each of these chip selects are controlled by a pair of 32-bit chip-select conﬁguration registers: (0x6F020, 0x6F024), (0x6F028, 0x6F02C), (0x6F030, 0x6F034), (0x6F038, 0x6F03C), (0x6F040, 0x6F044), (0x6F048, 0x6F04C).
Page 118 • 1001 - Region is 16M • 1010 - Region is 32M • 1011 - Region is 64M • 1100 - Region is 64M 10-12 Host Async Master Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 119 When a master address with no M_CS pin selected occurs on an async master DMA cycle, the entire transfer is aborted and the GO bit is cleared. The personality-dependent register is shown below: Chip Select Conﬁguration Registers 10-13 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 120 Figure 10.4. Reset to one. [25:24] Address setup time, corresponding to AS in Table 10.2. Reset to three. 10-14 Host Async Master Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 121: Interrupt/Gpio Configuration And Value Registers
ﬁeld for GPIO[5] is stored in the most signiﬁcant four bits of the register, as shown below. Interrupt/GPIO Conﬁguration and Value Registers 10-15 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 122: Gpio Pin Operating Modes
Interrupt/GPIO conﬁguration register will only update ﬁelds which have the write-enable bit set to one. Any ﬁelds that have a 0 write enable bit during register writes remain unchanged. 10-16 Host Async Master Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 123: Async Master Status/Time-Out Register
M_CS pin selected occurs on a SPARC read, the cycle is aborted and a data access exception trap is induced in the respective SPARC. When a time-out, SD/Secondary bitstream conﬂict or master Async Master Status/Time-Out Register 10-17 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 124 Reﬂects the last master mode access error caused by video SPARC. SysSparc Status [13:11] Reﬂects the last master mode access error caused by the system SPARC. 10-18 Host Async Master Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 125: Async Master Sparc Error Address Register
This register at control bus address contains the address of the last SPARC write to generates a host error. The upper six bits are always zero. Async Master SPARC Error Address Register 10-19 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 127: Video Interface
• Section 11.2, “Video Operation” • Section 11.3, “Video Control Register” The DMN-8600 processor provides a video input port and a video output port. Figure 11.1 shows the data ﬂow for the video input port. The input port captures 8-bit digital video from ITU-R 656 (parallel D1) or low-cost video decoder chips such as the Philips SAA7111.
Page 128 Additional windows can be captured by loading a new capture window in to the input channel at the completion of each window. In a multiple DMN-8600 system, each chip will capture the video region it requires. 8-bit values are passed through an 8-tap, 8-phase horizontal ﬁlter for resampling and noise reduction.
Page 129: Video Output Channel Data Flow
For DoMiNo, the maximum output rate is 74.25 MHz (smpte 260m). The maximum OSD pixel rate with ﬂicker ﬁltering and 32-bit pixels is 37.125 MHz. The DMN-8600 output values are optionally passed through an interpolating 4-tap, 8-phase horizontal ﬁlter. The video output channel can convert from 4:2:0 to 4:2:2 on the ﬂy using a 2-tap ﬁeld or frame ﬁlter with software speciﬁed coefﬁcients.
Page 130: Video Output Format
The normal data window and the blanking window may overlap the boundary of the active window. Restriction : Pels cannot be captured within and including the EAV and SAV regions (138 pels wide). 11-4 Video Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 131: Video Operation
This section explains the general operation of the video interface. 11.2.1 Video Streams The DMN-8600 processor takes as its input a single video stream synchronized with a 27 MHz Video Clock (VI_CLK[0]). The DMN-8600 processor supports both interlaced and progressive video streams.
Page 132: Itu-R 656 Operation
The Video Control Register is used to control a variety of features, as described in the description below. A read-modify-write cycle must be used when accessing this register. 11-6 Video Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 133: Video Control Register
Vertical chroma last. If set and VCP and VCD are set (and FRC is not set) when GoI is set by software, then the last chroma input line will be duplicated for the last Video Control Register 11-7 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 134 ﬁeld/frame or the previous window in the current ﬁeld/frame had VCD clear. VCL must be set when VCD is set and this is the last window in the current 11-8 Video Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 135 1 command queue. A transfer is loaded into the queue each time the GoI or echo bit is set by software. A command is removed from the queue each Video Control Register 11-9 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 136 In DoMiNo, there are separate interrupts for input and output transfer completion, so VidInInt and VidOutInt can be set at the same time. This bit should not 11-10 Video Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 137 When VideoRGB is set, RLEalpha blending, PIP and echo windows are not allowed. The video RGB layer is affected by the Video Control Register 11-11 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 138 YCbYCr format otherwise the output window will read output data in CbYCr format. Important: Packed video is not implemented in the ﬁrst version of DoMiNo, and this bit is ignored. 11-12 Video Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 139 Note that Echo and GoI can both be set time, to echo and capture input data to SDRAM at the same. Echo windows can not be Video Control Register 11-13 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 140 The GoO bit must be set before the start of the output window. Typically it will be set from the video ﬁeld or video transfer 11-14 Video Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 141 At reset, this bit is set to avoid contention on the output pins. The reset sequence can clear this bit if DMN-8600 is the only driver. This bit should not be changed while an output transfer is active or pending.
Page 142 This bit must be programmed to 0. Oclkr If set, video data output pins are clocked on the rising edge of the video output clock; otherwise, they are 11-16 Video Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 143 ﬁeld of the video output. This bit should not be changed while an output transfer is active or pending. This bit must be programmed to 0. Video Control Register 11-17 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 144 LSI Logic Conﬁdential Out16 If set and RGB is not set, DMN-8600 video output is 16 bits wide (SMPTE 260M). If Out16 and RGB are clear, video output is 8 bits wide (656). This bit should not be changed while an input or output transfer is active or pending.
Page 145 This bit is set when the input/output rate is out of range or when an extremely large DSP load or store instruction is executed (more than 1 Kbyte transferred). Video Control Register 11-19 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 146 OSD pixels in the window. Alpha Mode Value Alpha Mode Normal Alpha Inverted Alpha Constant Alpha Transparent Color 11-20 Video Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 147 The GoRLE bit remains set while the RLE transfer is outstanding to allow software polling for completion. Clearing this bit is ignored (use the Stop bit instead). Video Control Register 11-21 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 148 SqPixel bit. Square pixel scaling is limited to pixel output rates less than or equal to one ﬁfth of the DMN-8600 internal clock (480P at 148.5 MHz). OSD data is scaled by duplicating pels horizontally by the scale factor amount.
Page 149 Polling is typically used for short transfers (<10 microseconds), and interrupts are used for longer transfers. Video Control Register 11-23 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 150 GoOSD bit remains set while there is at least one video output transfer outstanding to allow software polling for completion. Clearing this bit is ignored (use the Stop bit instead). 11-24 Video Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 151: Audio Interface
AI_MCLKO – Internal audio input master clock • AO_MCLKO – Internal audio output master clock The 8600 also has an IEC958 data output signal. DMN-8600 DVD Recorder System Processor 12-1 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 152: Data, Serial Clocks And Fsync
(AC3 or MPEG). The sample rate of audio samples carried by this interface can be 32, 44.1, 48 or 96 kHz. The width of audio samples can be up to 24 bits. 12-2 Audio Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 153: Audio Input Control Register
(AI_FSYNC as an output) is clocked on the falling edge of the AI_SCLK input; otherwise, it is clocked on the rising edge. Programming note: This ﬁeld should be Audio Input Control Register 12-3 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 154 GoI bit. Stop Setting this bit halts audio input and output processing for diagnostic purposes. All queue entries from both input and both output streams are ﬂushed. 12-4 Audio Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 155 AI_SCLK and AI_FSYNC are outputs and frame timing is derived from the input master clock using the divisor speciﬁed by IBclock. Internally generated input Audio Input Control Register 12-5 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 156 (MSB at lowest address). ChCnt [6:5] The number of stream audio channels to capture or ChCnt playback is 2 . Audio data is stored as sets of 12-6 Audio Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 157 GOI bit remains set while there is at least one audio input 1 DMA transfer outstanding. When all audio input outstanding transfers are done, the DMA will clear the bit, Audio Input Control Register 12-7 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 158 This allows the I958 output to run at a subsampled rate (typically 44.1 kHz or 48 kHz) of the main audio output as required in DVD-Audio. Programming note: This ﬁeld 12-8 Audio Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 159 24 bits of the sample are transmitted in each output subframe. If 16 bit samples are selected, then they occupy the upper 16 bits of each Audio Output Control Register 12-9 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 160 Disabled: IEC958 will not respond to GoO; Stream audio output doesn’t sync with IEC958 block 0. Enabled: IEC958 responds to stream 1 GoO; Stream audio output syncs with IEC958 block 0. 12-10 Audio Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 161: Audio Output Control Register
16-bits of the status out register. Left High/Right Low sync is high from during left (lowest number) channel sample bits and low during right Audio Output Control Register 12-11 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 162 (upper memdata bits used) OTim If set and Frform is not one or two, the timing of each stream output sample is 64 bit clocks (as recommended 12-12 Audio Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 163 When outputting less than 8 audio channels, zero data is transmitted on the unused output channels. Audio Output Control Register 12-13 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 164 ﬁrst frame of output on the audio pins will be synchronized to the start of an IEC958 block boundary to allow consistent IEC958 user status and audio data. Programming note: When changing IEC958 user status, 12-14 Audio Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 165: Audio Status Registers
Usually the status input/output provides status information to an audio codec connected to the processor or delivers status words from an audio codec to the processor. For the DMN-8600, three registers are used for status input and three for status output, as shown below.
Page 166 AudioStatusOut[1] to the AO_D [3:0] pins during each audio frame. Data is clocked even when the output DMA is not active. This register is typically used to control codec status. 12-16 Audio Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 167 1 output DMA queue to drain, change the IEC958 status registers then queue up the next output transfer. Audio DMA In Status Register Memory Space Address: 0x050024 Audio PTS Audio Status Registers 12-17 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 168: Audio Address And Length Registers
The contents are undeﬁned after the transfer begins. This register is part of a two-level command queue that is advanced each time the GoI bit is set by software. Reading or writing the Audio Input DRAM Address 12-18 Audio Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 169: Audio Input Length Register
GoI bit is set by software. Reading or writing the IEC958 Output DRAM Address register returns or updates the most recent queue entry. The lowest three bits are always zero. Audio Address and Length Registers 12-19 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 170: Audio Output Length Register
FRFORM 7 Right The number of samples per frame speciﬁes the number of audio samples transmitted per frame sync cycle on each audio input and output pin. 12-20 Audio Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 171 The data has the same format as an input sample speciﬁed in the Audio Conﬁguration command deﬁned in the DMN-8600Programming Reference Manual. Audio Frame Formats 12-21 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 172 0x05000C AI_D2 Pin AI_D3 Pin Figure 12.2 FRFORM 0 Audio Frame Deﬁnition SCLK FSYNC 1 Frame Audio 32/64 Bits 32/64 Bits 32/64 Bits 32/64 Bits Data] 12-22 Audio Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 173: Audio Frame Formats
FSYNC is LOW. The FSYNC transition occurs at the ﬁrst bit of each sample. The transition of FSYNC from LOW-to-HIGH and HIGH-to-LOW deﬁnes the beginning or end of each sample. Audio Frame Formats 12-23 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 174: Frform
FRFORM 5 audio frame format. In this format, two 16-bit audio samples are transmitted per frame sync (FSYNC) cycle. FRFORM 5 uses a Left HIGH/Right LOW frame sync–that is, the Left 12-24 Audio Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 175: Frform
Right Sample Figure 12.8 FRFORM 6 Audio Frame Deﬁnition (Right Justiﬁed) SCLK FSYNC 1 Frame Audio 18 Bits 18 Bits Data Left Sample Right Sample Audio Frame Formats 12-25 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 176: Frform
LOW-to-HIGH and HIGH-to-LOW deﬁnes the beginning or end of each sample. Figure 12.9 FRFORM 7 Audio Frame Deﬁnition (Right Justiﬁed) SCLK FSYNC 1 Frame Audio 20 Bits 20 Bits Data Left Sample Right Sample 12-26 Audio Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 177: Sdram Interface
• Section 13.9, “SDRAM Timing” The DMN-8600 processor uses a 32-bit memory interface that supports up to 64 Mbytes of DRAM. The DRAM memory uses two to four 16-bit wide SDR/DDR DRAMs, or one to two 32-bit wide SDR/DDR DRAMs, capable of running at 150 MHz, 2.5 V–3.3 V.
Page 178 32–64 Mbytes pairs 1. HDTV requires 8 banks (two 4 bank or one 8 bank part) and 150 MHz. Example conﬁgurations are shown in Figure 13.1–Figure 13.4. 13-2 SDRAM Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 179 UDQS VDD2.5 UDQS VREF SDRAM_CLK1 BA[1:0] VDD2.5 MADDR[15] VREF MADDR[13:12] BA[1:0] DQM2 LDQM LDQM DQM3 UDQM UDQM Processor 8M x 16 (4 banks) 8M x 16 (4 banks) 13-3 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 180 DQ[15:0] A[11:0] SDRAM_CLK[1] BA[1:0] BA[1:0] MADDR[15] DQM2 DQM2 MADDR[13:12] LDQM LDQM DQM3 DQM3 UDQM UDQM Processor 8M x 16 (4 banks) 8M x 16 (4 banks) 13-4 SDRAM Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 181 2M x 32 SDRAM (4 banks) 2M x 32 SDRAM (4 banks) SDRAM_CKE SDRAM_RAS SDRAM_CAS SDRAM_WE DM[3:0] DM[3:0] SDRAM_CLK[0] BA[1:0] BA[1:0] DQ[31:16] A[10:0] DQ[15:0] A[10:0] SDRAM_A[10:0] SDRAM_DQM[3:0] SDRAM_DQ[31:0] SDRAM_A[12:11] SDRAM_CLK[1] SDRAM_A[15] 13-5 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 182: Dram Address Map
The bits above the column address bits are used to select banks (2 bits for 4 banks, and 3 bits for 8 banks). The bits above 13-6 SDRAM Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 183: Supported Number Of Simultaneous Banks
Within a transaction, up to four active DRAM banks are used. A misaligned 9 V x 64 H transaction will touch at most 4 pages in separate banks (with the DMN-8600 tiled image format). The bank precharge and Supported Number of Simultaneous Banks 13-7 Copyright ©...
Page 184: Sdram Initialization
4 banks of the previous access. 13.4 SDRAM Initialization DRAMs require an initialization sequence to be performed when the DMN-8600 is reset through the reset pin or the host control register. Note: Proper initialization assumes that the SDRAM Clock Control and External SDRAM Conﬁguration register have...
Page 185: Sdram Refresh
(refer to speciﬁc DRAM timing specs for more details). The 12 bits of data are written via the Address bus. Values for the DRAM Mode register used by the DMN-8600 processor will be as follows:...
Page 186: External Sdram Configuration Register
10 = Page size is 32x512. Tile height is 32. DRAM Size [28:27] DRAM size. For 16 bit wide parts, refers to the size of a pair of parts. 13-10 SDRAM Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 187 Reads from different slots and read to write require dead clocks. Write to read will have at least 1.5 dead clocks because of CAS latency. External SDRAM Conﬁguration Register 13-11 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 188 Active command to Active Command duration (tRC) is not programmed since it is (tRAS + tRP). The actual value is (programmed_value + 1). 13-12 SDRAM Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 189: Sdram Control And Clock Control Registers
The SDRAM Clock Control Register controls the timing of the SDRAM input and output clocks. This register must be written at least 1 SDRAM Control and Clock Control Registers 13-13 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 190: Sdram Arbitration And Throttle Registers
13.6) so the DRAM clocks are stable for the required period (per DRAM data sheet specs) prior to initialization of the DRAMs. This register should only be written once after the DMN-8600 is reset (via the Chip Reset bit in the Host Control register).
Page 191 23. DSP Alpha channel 24. DSP VLC channel 25. ME Wmem/Tmem load 26. ME result write 27. ME command read 28. Video Subpicture RLE Data input SDRAM Arbitration and Throttle Registers 13-15 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 192 DMA throttle counter reaches zero. This allows software to spread host DMA DRAM loading uniformly over a ﬁeld, when the full host DMA bandwidth is not needed. 13-16 SDRAM Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 193: Sdram Timing
Read data on SDRAM_DQ is latched internally with a read clock whose lead time relative to the other processor outputs to the SDRAMs is speciﬁed in microcode. The read clock tracks the other outputs SDRAM Timing 13-17 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 194 LSI Logic Conﬁdential (speciﬁcally SDRAM_CLK) so that read data can be captured independent of actual output delay. 13-18 SDRAM Interface Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 195: Bitstream I/O (Storage) Port
Two more ring buffers are supported to manage input data for SDRAM-to-SDRAM operations. DMN-8600 DVD Recorder System Processor 14-1 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 196 ATAPI_DIOR signal t1 time later. The 16-bit data (AtapiIOCS16 signal is always low) from the ATAPI device is latched by the ATAPI Interface during the rising edge of the ATAPI_DIOR signal. 14-2 Bitstream I/O (Storage) Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 197: Atapi Interface
ATAPI device. The host must do several ATAPI register read/writes to the ATAPI device using the ATAPI_RD and ATAPI_WR commands before it can initiate the ATAPI DMA transfer from the host. ATAPI Interface 14-3 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 198 ATAPI device deasserts the ATAPI_DMARQ signal. Figure 14.2 ATAPI DMA Read/Write Cycle ATAPI_DMARQ (I) ATAPI_DMAACK (O) ATAPI_DIOW/DIOR (O) ATAPI_DATA[15:0] Data0 Data1 (Read) (I/O) ATAPI_DATA[15:0] Data0 Data1 (Read) (I/O) 14-4 Bitstream I/O (Storage) Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 199 ATAPI Interrupt Request. Software can monitor the status of DoMiNo’s ATAPI_INTRQ input pin by reading this read-only bit. External devices will set this bit to indicate the completion of ATAPI operations. ATAPI Interface 14-5 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 201: Sd Interface
For the read operation, the SD Interface asserts the read request signal SD_RDREQ when it receives the SD_DECS_BS or SD_DESC_NO command from the host. The SD device must respond to the read SD Interface 14-7 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 202 The CD Interface continues to search for the sector sync bytes, once it is enabled and the SrchCnt (sector sync search count) in the SD/CD 14-8 Bitstream I/O (Storage) Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 203: Cd Interface
SD/CD Conﬁguration Register Cbus Address: 0xFB0050 Atapi TKDe SDWr EnS- Srch- Reserved SdInt Mode eSrt C2po SrchCnt SDreq SDack SDclk CDG Mode BCK LRclk DatOrd Wdlen Sync C2po CD Interface 14-9 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 204 The interface protocol in which the BIO will be working: 0 = ATAPI, 1 = SD, 2 = CD. Software must set this bit 14-10 Bitstream I/O (Storage) Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 205 NoC2po Only used to differentiate the 2 cases where WeLen = 2, DatOrd = 0, Lrck = 1, Bck = 0. (For other cases, this bit CD Interface 14-11 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 206: Valid Signal Formats
1 = Left channel active when CD_LRCK pin is high. C2poOrd C2PO error ﬂag ordering: 0 = MSByte ﬁrst, 1 = LSByte ﬁrst. Since DMN-8600 uses one bit in the appendix to report errors in each 128-byte block of data, this bit doesn’t affect the appendix.
Page 207 CD-LRCK CD-DATA Invalid Invalid CD-C2PO MSB Valid MSB Valid LSB Valid 24-bit BCK, MSB First, Left Channel Low, C2PO MSB First, DAta Latch Timing High (IDS) CD Interface 14-13 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 208: 1394 Controller
1394 descrambling on the scrambled data. In both cases, the BIO sends the raw packets to SDRAM and appends extra information such as an all-zero packet ﬂag, transmitting speed, receive status, and acknowledge code. 14-14 Bitstream I/O (Storage) Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 209 LSI Logic Conﬁdential For asynchronous packets (APs) received on the 1394 interface, if the packet is directed to the current DMN-8600 node, the BIO sends the packet to the AP’s SDRAM buffer and signals an interrupt at the end of an isochronous cycle.
Page 211: Serial I/O Port
IR module generates waveforms with the programmed pulse length and period characteristics, while for receive, it simply measures the period and duty cycle of incoming pulses. DMN-8600 DVD Recorder System Processor 15-1 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 212: Ir Interface Protocol
IRTX Modulated Signal Pulse Low: 0x0 + 1 0xff + 1 User can program duty cycle of IRTX carrier carrier waveform, in units of carrier wave cycles cycles cycles 15-2 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 213: Ir Transmit Functionality
Transmit Period register (IR_MSPR) is the Transmit Enable bit. When programmed to one, this bit indicates that the pulse shape values should be loaded immediately after the completion of the current pulse SIO IR (Infrared) Interface 15-3 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 214: Ir Receive Functionality
SIO_IRRX signal. Again, this provides a minimum of 1.125 ms between interrupts for the NCR protocol (shown in Figure 15.2) and 1.778 ms for the RC-5 protocol (shown in Figure 15.3). 15-4 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 215: Ncr Ir Protocol
(as if zooming in to reveal more detail). SIO_IRTX and SIO_IRRX are asynchronous. The timing parameter values are under program control, e.g., application-speciﬁc. SIO IR (Infrared) Interface 15-5 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 216: Ir Programming Guidelines
MSPL and MSPR. However, the DMA Engine writes these two registers simultaneously by writing a single 32-bit word with the upper bits of MSPR and MSPL concatenated. The TX data to 15-6 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 217: Sio Spi (Serial Peripheral Interface)
SPI (for example, Sony and Motorola). A typical SPI interface application is shown in Figure 15.4, where the SPI controller is the bus master. SIO SPI (Serial Peripheral Interface) 15-7 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 218 SPI clock frequency range from 4.58 kHz to 37.5 MHz (150 MHz system clock) • Four SIO_SPI_CS[n] signals (16 when used with an external decoder) 15-8 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 219: Spi Interface Signals
(output) port for the SPI interface. SIO_SPI_MISO: SPI Master In Slave Out (Serial Data In). This is the read data (input) port for the interface. SIO SPI (Serial Peripheral Interface) 15-9 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 220: Spi Interface: Protocol Description
2. First Bit of Data Transfer: Data simultaneously gets shifted out the SIO_SPI_MOSI pin and shifted in the SIO_SPI_MISO pin. Depending on the LSBF setting in the SPI_CONFIG register, this 15-10 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 221: Spi Clocking
The programmable value for SIO_SPI_CLK is given by the following equation: sysclk --------------------------------------------- - × spiclk progdiv where progdiv is the value written to the programmable divider (HDIV,SPED). SIO SPI (Serial Peripheral Interface) 15-11 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 222: Spi Transfer: Host-Polled Mode
(polarity, SPI_CS[n] setup/hold, inter-byte blanking, and so forth) and clear bits [15:14] of the SPI_CONFIG register. b. Set the desired SPI_CLK speed by programming the divider (HDIV, SPED). 15-12 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 224 Software must mask the value read from SPI_TEMP to get the real data bytes that are valid, since reading this register (either explicitly, or having the 15-14 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 225: Other Applications
SIO_SPI_CLK is at a static level determined by the CPOL bit. During a SPI cycle, data is transferred only when SPI_CS[n] is asserted and SIO_SPI_CLK is active. SIO SPI (Serial Peripheral Interface) 15-15 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 226: Idc Interface
RX buffers (72 bytes TX, 64 bytes RX). 15.3 IDC Interface The SIO_SDA (IDC Data Bus) and SIO_SCL (IDC Clock) signals are used to interface the DMN-8600 to other devices. The IDC has DMA 15-16 Serial I/O Port...
Page 227 6. Acknowledge Bit: Receiver pulls SIO_SDA LOW while SIO_SCL is HIGH to acknowledge receipt of data. 7. STOP Condition: Master terminates transaction by making a LOW-to-HIGH transition on SIO_SDA while SIO_SCL is HIGH. IDC Interface 15-17 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 228: Sio Uart Interface
(nbdout) from the baud rate generator that is 16 times the desired baud rate. This block implements a 16-bit counter to generate the nbdout from the input clock. The Divisor value can be calculated as follows 15-18 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 229: Sio Register Descriptions
(32-bit) boundaries. They must be accessed through 32-bit CBus loads and stores only. Note: Reserved (Rsvd) bits must always be written as 0 and are undeﬁned when read. SIO Register Descriptions 15-19 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 230: Interrupt Hierarchy
Module Interrupt Status register and the DMA Interrupt Status register are OR’d together to signal to the SPARC processor that the SIO has an interrupt pending. 15-20 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 231: Sio Top Level & Dma Engine Registers
SIO DMA Engine Interrupt Sta- tus register does not change (that is, if the DMA operation is complete, no interrupt is generated). SIO Register Descriptions 15-21 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 232 Each DMA channel has two interrupt bits associated with Bit 1 indicates completion of the entire DMA operation— that is, no DMA buffers are pending. 1 = Completed 15-22 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 233 Action Bit This bit is an action bit. The value of this bit is written to any selected bits during register writes. Bits to be written SIO Register Descriptions 15-23 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 234 The programming of these bits overrides the default behavior. The highest priority is assigned to the target module channel whose ID is programmed in TGT_ID. Rotating Priority 15-24 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 235 This register, depending on the value of the corresponding bit in the SIO Top Level Module Interrupt Enable register, records each of the interrupt signals generated by the various peripheral modules in the SIO. SIO Register Descriptions 15-25 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 236 1 in each desired location as the register is written. Any bit positions that contain a 0 during register writes remain unchanged. This bit always reads back as 0. 15-26 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 237 1 in each desired location as the register is written. Any bit positions that contain a 0 during register writes remain unchanged. This bit always reads back as 0. SIO Register Descriptions 15-27 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 238 SIO Top Level DMA Interrupt Status Register (SIO_DMA_IRQ) Offset = 0xBF014C Read/Write Default = 0x0000 0000 RSVD RSVD R2DT R1DR R1DT U2DR U2DT U1DR U1DT SPDR SPDT ACT 15-28 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 239: Sio_Dma_Irq Registers
Each of the Interrupt Status bits shown below signals that the corresponding DMA channel has an interrupt waiting to be serviced: 1 = Waiting 0 = Done SIO Register Descriptions 15-29 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 240 1 in each desired location as the register is written. Any bit positions that contain a 0 during register writes remain unchanged. This bit always reads back as 0. 15-30 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 241 1 in each desired location as the register is written. Any bit positions that contain a 0 during register writes remain unchanged. This bit always reads back as 0. SIO Register Descriptions 15-31 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 242: Sio Idc Registers
Master Mode 1 = The transaction is a master read from the external device. 0 = The transaction is a master write to the external device. 15-32 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 243 1 = Slave receive mode is enabled. Note: IDC master and slave modes are not mutually exclusive. In master mode, DMN-8600 can initiate transfers. In slave mode, it responds to transfers. SIO Register Descriptions 15-33 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 244 The number of bytes in the Byte2Rd ﬁeld of IDC_Control1 has been read, the LB bit is set, and the STOP condition has been generated. Rx FIFO is full. 15-34 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 245: Status Register Events
Repeat Start was generated. Slave Address 1 = The slave state machine detected a start condition, and the address is the IDC device address. SIO Register Descriptions 15-35 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 246 Offset = 0xBE0088 Read/Write Default = 0x0000 0000 Reserved SAddr Reserved SAddr Slave Address [22:16] The IDC device responds to this address when in slave mode. 15-36 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 247 RxCnt ﬁeld of the IDC FIFO Fullness register. Attempting to read more bytes than are available will corrupt the RxCnt value, requiring a software reset. SIO Register Descriptions 15-37 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 248 ﬁlled with data until the IDC device wins arbitration. Otherwise, if the winning master tries to read from the IDC device, the IDC device sends the data intended for its own 15-38 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 249 The actual number of bytes left to receive in master receive mode. RxCNT Received Byte Count [23:20] Number of bytes in (“fullness” of) the received data FIFO. SIO Register Descriptions 15-39 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 250 SIO_SDA line. The processor is interrupted, and the bus is stalled until the processor writes 1 into this bit. 15-40 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 251 IDCSAMP IDC Samples [19:16] This ﬁeld determines the number of sysclk cycles between successive input samples. The actual value used is IDCSAMP+1. SIO Register Descriptions 15-41 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 252 FIFOs up to the SDRAM (if receive). CHEN DMA Channel Enable This bit enables/disables the DMA channel. If CHEN is cleared during a DMA operation, DMA is paused. Set 15-42 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 253 1 to it. IDC DMA Transmit Address Pointer 1 Register (IDC_TX_ADDR_PTR1_ADDR) Offset = 0xBE00C8 Read/Write Default = 0x0000 0000 Reserved ADDR_PTR1 ADDR_PTR1 SIO Register Descriptions 15-43 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 254 Offset = 0xBE00D0 Read/Write Default = 0x0000 0000 Reserved ADDR_PTR3 ADDR_PTR3 ADDR_PTR3 Address Pointer 3 [27:0] This register is updated by hardware during a DMA oper- ation. 15-44 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 255 MODE FLUS CHEN Load Current Address Buffer Registers This bit is used to control when ADDR_PTR1 and ADDR_PTR2 for a particular DMA channel are loaded SIO Register Descriptions 15-45 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 256 DMA operation has ﬁnished. On reset, CHEN is 0. IDC DMA Receive Status Register (IDC_RX_STATUS_REG_ADDR) Offset = 0xBE00E4 Read/Write Default = 0x0000 0000 Reserved FLSTS FLVLB 15-46 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 257 Address for the next SDRAM buffer about to be trans- ferred. Note: The maximum size for each SDRAM buffer transfer is 511 bytes. Therefore, the difference between ADDR_PTR2 and ADDR_PTR1 should not exceed 511. SIO Register Descriptions 15-47 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 258 In double-buffer mode, this register is loaded with the contents of ADDR_PTR1 if Go is high and if either of the following is true: • The DMA channel is idle. 15-48 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 259: Sio Ir1 / Ir2 Registers
This register encodes the period of the IR carrier wave in units of sysclk cycles. This register allows carrier frequen- cies as low as 4.58 kHz. The actual carrier wave period is CWP[13:0] + 1. SIO Register Descriptions 15-49 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 260 Output Polarity 1 = The SIO_IRTX* output is active high, normally low. 0 = The SIO_IRTX* output is active low, normally high. 15-50 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 261 = (MSPL[7:0]+1)(carrier wave period). This register is sufﬁcient to provide a 4.5 ms pulse, the largest low pulse width required by existing IR standards. SIO Register Descriptions 15-51 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 262 This ﬁeld is read-only. IR1 Receive Tick Period Register (IR1_RTP) Offset = 0xBF0014 Read/Write Default = 0x1B770000 RSVD 15-52 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 263 This value has no effect if the Filter Start Pulse bit in the IR Receive Tick Count register is set to zero. SIO Register Descriptions 15-53 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 264 IR1 DMA Transmit Control Register (IR_TX_CONTROL_REG_ADDR) IR2 DMA Transmit Control Register (IR2_TX_CONTROL_REG_ADDR) Offset = 0xBF0040 / 0xBF00C0 Read/Write Default = 0x0000 0000 RSVD RSVD MODE FLUS CHEN 15-54 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 265 DMA operation continues from where it left off. CHEN is controlled by software. It must be cleared once the DMA operation has ﬁnished. On reset, CHEN is 0. SIO Register Descriptions 15-55 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 266 IR1 DMA Transmit Address Pointer1 Register (IR_TX_ADDR_PTR1_ADDR) IR2 DMA Transmit Address Pointer1 Register (IR2_TX_ADDR_PTR1_ADDR) Offset = 0xBF0048 / 0xBF00C8 Read/Write Default = 0x0000 0000 RSVD ADDR_PTR1 ADDR_PTR1 15-56 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 267 IR1 DMA Transmit Address Pointer3 Register (IR_TX_ADDR_PTR3_ADDR) IR2 DMA Transmit Address Pointer3 Register (IR2_TX_ADDR_PTR3_ADDR) Offset = 0xBF0050 / 0xBF00D0 Read/Write Default = 0x0000 0000 RSVD ADDR_PTR3 ADDR_PTR3 SIO Register Descriptions 15-57 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 268 ADDR_PTR2 if Go is high and if either of the following is true: • The DMA channel is idle. • The previous SDRAM buffer has completed. 15-58 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 269 Setting FLUS does not terminate a transfer; it merely dumps data (if transmit) or sends whatever data remains in the FIFOs up to the SDRAM (if receive). SIO Register Descriptions 15-59 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 270 This ﬁeld shows the number of bytes currently held in FIFO A. CHST DMA Channel Status 1 = The DMA transfer operation has ﬁnished. CHST can be cleared by writing 1 to it. 15-60 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 271 Address for the “next” SDRAM Buffer about to be trans- ferred. Note: The maximum size for each SDRAM buffer transfer is 511 bytes. Therefore, the difference between ADDR_PTR2 and ADDR_PTR1 should not exceed 511. SIO Register Descriptions 15-61 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 272 ADDR_PTR2 if Go is high and if either of the following is true: • The DMA channel is idle. • The previous SDRAM buffer has completed. 15-62 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 273: Sio Spi Registers
Bit-bang Mode Bit to SPI Signal Mapping Byte/Bit Signal In/Out BYTE[n].7 Don’t Care BYTE[n].6 SIO_SPI_CS[3] BYTE[n].5 SIO_SPI_CS[2] BYTE[n].4 SIO_SPI_CS[1] BYTE[n].3 SIO_SPI_CS[0] BYTE[n].2 SIO_SPI_CLK BYTE[n].1 SIO_SPI_MOSI BYTE[n].0 SIO_SPI_MISO SIO Register Descriptions 15-63 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 274 HAEN bit and allows the cycle to continue. If the read data is needed, the host reads the SPI_TEMP register before doing the write. 15-64 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 276: Spi Inter-Byte Blanking
These bits allow adjustment of the setup and hold times of the SIO_SPI_CS[n] about SPI_CLK. CSDL is the num- ber of half SIO_SPI_CLK cycles between the following events: 15-66 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 277: Cssl Bit To Chip Select Mapping
Host Access Enable 1 = Host access of SPI_TEMP is enabled. HAEN is set when the SPI_TEMP register is loaded with the contents of SPI_SHIFT. SIO Register Descriptions 15-67 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 278 With the DMA engine, these write/read updates are taken care of automatically. See Section 15.2.5, “SPI Program- ming Examples,” page 15-12 for more details. 15-68 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 279 SIO_SPI_MISO. The order of the bits is unaffected by the LSBF bit, which causes the swap of the bits when trans- ferring to/from the SPI_TEMP register. When a SPI cycle SIO Register Descriptions 15-69 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 280 BSIZ and BCNT. If (BCNT != 0) NumBits Transferred = (BSIZ)* 8 + BCNT else NumBits Transferred = (BSIZ + 1) * 8 15-70 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 281: Number Of Bits Sent Depending On Programmed Values Of Bsiz And Bcnt
# Bits Sent 40=32+8 37=32+5 120=32+32+32+24 119=32+32+32+23 144=32+32+32+32+16 142=32+32+32+32+14 SPI Clock Divider Register, MSB (SPI_SPED_MSB) Offset = 0xBE0028 Read/Write Default = 0x0000 0000 RSVD RSVD HDIV SIO Register Descriptions 15-71 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 282 It is also cleared on reset. MODE Transfer Mode Select This bit must always be set to ‘1’ so that the channel operates in double-buffer mode. 15-72 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 283 This ﬁeld shows the number of bytes currently held in FIFO B. FLVLA FIFO A Byte Count This ﬁeld shows the number of bytes currently held in FIFO A. SIO Register Descriptions 15-73 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 284 Address for the “next” SDRAM buffer about to be trans- ferred. Note: The maximum size for each SDRAM buffer transfer is 511 bytes. Therefore, the difference between ADDR_PTR2 and ADDR_PTR1 should not exceed 511. 15-74 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 285 ADDR_PTR2 if Go is high and if either of the following is true: • The DMA channel is idle. • The previous SDRAM buffer has completed. SIO Register Descriptions 15-75 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 286 Setting FLUS does not terminate a transfer; it merely dumps data (if transmit) or sends whatever data remains in the FIFOs up to the SDRAM (if receive). 15-76 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 287 This ﬁeld shows the number of bytes currently held in FIFO A. CHST DMA Channel Status 1 = The DMA transfer operation has ﬁnished. CHST can be cleared by writing 1 to it. SIO Register Descriptions 15-77 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 288 Address for the “next” SDRAM buffer about to be trans- ferred. Note: The maximum size for each SDRAM buffer transfer is 511 bytes. Therefore, the difference between ADDR_PTR2 and ADDR_PTR1 should not exceed 511. 15-78 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 289 ADDR_PTR2 if Go is high and if either of the following is true: • The DMA channel is idle. • The previous SDRAM buffer has completed. SIO Register Descriptions 15-79 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 290: Sio Uart1/Uart2 Registers
16-bit data into DLM and DLL (DLM holds the eight most signiﬁcant bits, DMSB, and DLL holds the eight least signiﬁcant bits, DLSB) to obtain an output (nBD- 15-80 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 291 FIFO mode, the THRE bit is reset when the data is loaded into the transmit FIFO; once reset, it will be set only after the transmit FIFO is empty. SIO Register Descriptions 15-81 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 292 Write UART*_DLM when DLAB = 1 • Read/Write UART*_IER when DLAB = 0 In either case, these registers are always accessed via the same software name: UART1_IER0_DLM1 or UART2_IER0_DLM1. 15-82 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 293 DLAB = 1 UARTn_IER when DLAB = 0 In either case, these registers are always accessed via the same software name, UART1_IER0_DLM1 or UART2_IER0_DLM1. SIO Register Descriptions 15-83 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 294 1 = Enable the DR bit in the Line Status Register to acti- vate the interrupt signal of the UART. The RDRE bit also enables the trigger level interrupt and the time-out inter- rupt. 15-84 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 295 UART*_FCR is write-only; that is, writing to this address changes the contents of UART*_FCR. In either case, each of these two registers is always accessed via the same software name, UART1_IIR_FCR or UART2_IIR_FCR. SIO Register Descriptions 15-85 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 296: Interrupt Identification Register Details
Interrupt Type None Highest Receiver Line Status Second Receiver Data Available or Trigger Level Reached Second Character Time-out Indication Third THR Empty Lowest Modem Status 15-86 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 297: Fcr Trigger Levels
FCR[0] Enable FIFOs 1= Enable both the transmit and receive FIFOs. 0 = Clear all bytes in both FIFOs. SIO Register Descriptions 15-87 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 298 1 = Select the divisor latches to be accessed during read/write operations to the DLL-THR-RBR and the DLM- IER registers. Set Break 1= The SOUT pin goes low. 15-88 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 299: Character Length And Stop Bits Of Lcr
8 Bits WLS[1:0] Word Length Select 25:24 These bits, along with STB, set the number of bits to be transmitted/received per character, and the number of SIO Register Descriptions 15-89 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 300 If hardware ﬂow control is disabled, this bit controls the SIO_UART*_RTS (request to send) output signal: 1 = The RTS pin is low. 0 = The RTS pin is high. 15-90 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 301 In FIFO mode, this bit is reset when at least one byte is written to the FIFO, and it is set when the transmit FIFO is empty. SIO Register Descriptions 15-91 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 302 FIFO is full and the next character is received completely in the Receive Shift Register. The character in the Receive Shift Register is not put into the receive FIFO. 15-92 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 303 0 = CTS pin is active high DCTS Delta CTS 1= The CTS has changed state. 0 = Cleared after the Modem Status Register has been read. SIO Register Descriptions 15-93 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 304 This register can alter the frequency of the external input clock, which is fed back into the UART. Note: These registers are known as UART1_EXT_CLOCK and UART2_EXT_CLOCK in global.h 15-94 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 305 UART1 DMA Transmit Control Register (UART1_TX_CONTROL_REG_ADDR) UART2 DMA Transmit Control Register (UART2_TX_CONTROL_REG_ADDR) Offset = 0xBE0140 / 0xBE01C0 Read/Write Default = 0x0000 0000 RSVD RSVD MODE FLUS CHEN SIO Register Descriptions 15-95 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 306 DMA operation continues from where it left off. CHEN is controlled by software. It must be cleared once the DMA operation has ﬁnished. On reset, CHEN is 0. 15-96 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 307 UART1 DMA Transmit Address Pointer1 Register (UART1_TX_ADDR_PTR1_ADDR) UART2 DMA Transmit Address Pointer1 Register (UART2_TX_ADDR_PTR1_ADDR) Offset = 0xBE0148 / 0xBE01C8 Read/Write Default = 0x0000 0000 RSVD ADDR_PTR1 ADDR_PTR1 SIO Register Descriptions 15-97 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 308 UART1 DMA Transmit Address Pointer3 Register (UART1_TX_ADDR_PTR3_ADDR) UART2 DMA Transmit Address Pointer3 Register (UART2_TX_ADDR_PTR3_ADDR) Offset = 0xBE0150 / 0xBE01D0 Read/Write Default = 0x0000 0000 RSVD ADDR_PTR3 ADDR_PTR3 15-98 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 309 ADDR_PTR2 if Go is high and if either of the following is true: • The DMA channel is idle. • The previous SDRAM buffer has completed. SIO Register Descriptions 15-99 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 310 Setting FLUS does not terminate a transfer; it merely dumps data (if transmit) or sends whatever data remains in the FIFOs up to the SDRAM (if receive). 15-100 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 311 This ﬁeld shows the number of bytes currently held in FIFO A. CHST DMA Channel Status 1 = The DMA transfer operation has ﬁnished. CHST can be cleared by writing 1 to it. SIO Register Descriptions 15-101 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 312 Address for the “next” SDRAM Buffer about to be trans- ferred. Note: The maximum size for each SDRAM buffer transfer is 511 bytes. Therefore, the difference between ADDR_PTR2 and ADDR_PTR1 should not exceed 511. 15-102 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 313 UART1 DMA Receive Address Pointer4 (UART1_RX_ADDR_PTR4_ADDR) UART2 DMA Receive Address Pointer4 (UART2_RX_ADDR_PTR4_ADDR) Offset = 0xBE0174 / 0xBE01F4 Read/Write Default = 0x0FFF FFFF RSVD ADDR_PTR4 ADDR_PTR4 SIO Register Descriptions 15-103 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 314: Reserved Registers (Sio Uart2)
UART2 Modem Status Register (UART2_MSR) Offset = 0xBE0198 Read/Write Default = 0x0000 0000 UART2 Hardware Flow Control Register (UART2_HW_FLOW_CTRL) Offset = 0xBE01A4 Read/Write Default = 0x0000 0000 15-104 Serial I/O Port Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 315: Clock Control And Power Management
PLLs. The 13.5 MHz reference frequency is also used as the clock for the PTS time stamp counters in the AV I/O and BIO units. The DMN-8600 has a full power-down mode which shuts down all PLLs and logic operating from the internally generated clocks. Power down mode is exited by hardware reset.
Page 316 Ain_Master VOUTClock (to VIO) Ain_Src AinPLLSrc AinPLLPD AUDIO MIClock (to AIO) AI_MCLKO AIO_CLK AO_MCLKI Aout_Master Aout_Src AoutPLLSrc MOClock (to AIO) AoutPLLPD AUDIO AO_MCLKO 16-2 Clock Control and Power Management Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 317: Clock And Power Registers
DRAM clock control register, followed by the DRAM conﬁguration register 1 msec later (see DRAM interface speciﬁcation). This ﬁeld is reset to one Clock and Power Registers 16-3 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 318 Change Adj[4:0] to 1; Wait at least 100 ms Change Adj[4:0] to 2; Wait at least 100 ms Change Adj[4:0] to 3 Default value equals 0x0F 16-4 Clock Control and Power Management Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 319 DRAM activity including cache misses and DMA transfers should be avoided until the DLLs are reset. The resetDLL bit is a Clock and Power Registers 16-5 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 320 If the source is internal or video input 1 clock, then the video out clock pin becomes an output of the video output clock. This ﬁeld is reset to two. 16-6 Clock Control and Power Management Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 321 After reset, N and P are set to 0. [6:4] See above. This ﬁeld is reset to 0. [3:2] See above. This ﬁeld is reset to 0. Clock and Power Registers 16-7 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 322 After reset, N is set to 4.0176 and P is set to 3. [29:3] See above. This ﬁeld is reset to 0x404816F. [2:0] See above. This ﬁeld is reset to 0x3. 16-8 Clock Control and Power Management Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 323 After reset, N is set to 4.0176 and P is set to 3. [29:3] See above. This ﬁeld is reset to 0x404816F. [2:0] See above. This ﬁeld is reset to 0x3. Clock and Power Registers 16-9 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 324 PLL timing will not be stable for 1 ms. Aout_PLL_Off Power down Audio Out PLL when set. When cleared, audio output PLL timing will not be stable for 1 ms. 16-10 Clock Control and Power Management Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 325 IR WE IR WakeUp Enable. If set, a falling edge on SIO_IRRX will wake up DoMiNo, otherwise it is ignored in power down state. Clock and Power Registers 16-11 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 326: Main Pll Power Down And Wake-Up Sequence
Internal Clock Control register after all DRAM transactions have been suspended. The MAIN PLL should be the last thing to be powered down. When in the power-down state, the only way to wake up the DMN-8600 is through reset, which may be generated in one of the following ways: •...
Page 329: Jtag Boundary Scan
DMN-8600 boundary scan supports only board-level testing (for example, SAMPLE/PRELOAD and EXTEST instructions); component testing (for example, the INTEST instruction) is not supported. DMN-8600 DVD Recorder System Processor 17-1 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 330: Jtag Instruction Set
LSI Logic Conﬁdential 17.1 JTAG Instruction Set The DMN-8600 processor JTAG instructions are three bits in length, encoded as shown in Table 17.1. Table 17.1 JTAG Instruction Set Opcode[2:0] Instruction EXTEST SAMPLE/PRELOAD 010–1110 Private BYPASS The Private instructions are “hazardous” as deﬁned by 1149.1 and should not be used.
Page 331: Boundary Scan Chain Cells
[IN/OUT] – Control [CTRL] ATAPI_DATA[11] [IN/OUT] – Control [CTRL] ATAPI_DATA[3] [IN/OUT] – Control [CTRL] ATAPI_DATA[10] [IN/OUT] – Control [CTRL] ATAPI_DATA[4] [IN/OUT] – Control [CTRL] Boundary Scan Chain Cells 17-3 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 332: Boundary Scan Chain Cells
[N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] 17-4 JTAG Boundary Scan Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 333 [IN/OUT] – Control [CTRL] BIO_PHY_CLK [IN] – Control [CTRL] BIO_PHY_CTL[1] [IN/OUT] – Control [CTRL] BIO_LINK_ON [IN] – Control [CTRL] BIO_PHY_DATA[7] [IN/OUT] – Control [CTRL] Boundary Scan Chain Cells 17-5 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 334 [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] 17-6 JTAG Boundary Scan Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 335 – DUMMY [N/A] – DUMMY [N/A] – Control [CTRL] VO_D[1] [OUT] – Control [CTRL] VO_D[2] [OUT] – Control [CTRL] VO_D[3] [OUT] – Control [CTRL] Boundary Scan Chain Cells 17-7 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 336 Control [CTRL] VO_D[12] [OUT] – Control [CTRL] VO_D[13] [OUT] – Control [CTRL] VO_D[15] [OUT] – DUMMY [N/A] – DUMMY [N/A] – Control [CTRL] VO_D[14] [OUT] 17-8 JTAG Boundary Scan Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 337 – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – Control [CTRL] Boundary Scan Chain Cells 17-9 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 338 VI_D[7] [IN] – Control [CTRL] VI_D[6] [IN] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] 17-10 JTAG Boundary Scan Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 339 – Control [CTRL] PLL_BYPASS [IN] – Control [CTRL] CLKO [OUT] – Control [CTRL] AI_SCLK [IN/OUT] – DUMMY [N/A] – DUMMY [N/A] – Control [CTRL] Boundary Scan Chain Cells 17-11 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 340 [CTRL] AO_IEC958 [OUT] – Control [CTRL] AO_FSYNC [OUT] – DUMMY [N/A] – DUMMY [N/A] – Control [CTRL] AO_SCLK [OUT] – DUMMY [N/A] – DUMMY [N/A] 17-12 JTAG Boundary Scan Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 341 – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] Boundary Scan Chain Cells 17-13 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 342 DUMMY [N/A] – DUMMY [N/A] – Control [CTRL] SDRAM_WE [OUT] – Control [CTRL] SDRAM_CKE [OUT] – Control [CTRL] SDRAM_RAS [OUT] – Control [CTRL] SDRAM_CAS [OUT] 17-14 JTAG Boundary Scan Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 343 [OUT] – Control [CTRL] SDRAM_A[12] [OUT] – Control [CTRL] SDRAM_A[8] [OUT] – Control [CTRL] SDRAM_A[10] [OUT] – Control [CTRL] SDRAM_A[7] [OUT] – Control [CTRL] Boundary Scan Chain Cells 17-15 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 344 – Control [CTRL] SDRAM_DQS[3] [IN/OUT] – Control [CTRL] SDRAM_DQ[30] [IN/OUT] – Control [CTRL] SDRAM_DQ[28] [IN/OUT] – Control [CTRL] SDRAM_DQ[29] [IN/OUT] – Control [CTRL] SDRAM_DQ[31] [IN/OUT] 17-16 JTAG Boundary Scan Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 345 [IN/OUT] – Control [CTRL] SDRAM_DQ[19] [IN/OUT] – Control [CTRL] SDRAM_DQ[18] [IN/OUT] – Control [CTRL] SDRAM_DQ[17] [IN/OUT] – Control [CTRL] SDRAM_DQ[16] [IN/OUT] – Control [CTRL] Boundary Scan Chain Cells 17-17 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 346 – Control [CTRL] SDRAM_DQ[12] [IN/OUT] – Control [CTRL] SDRAM_DQ[9] [IN/OUT] – Control [CTRL] SDRAM_DQ[15] [IN/OUT] – Control [CTRL] SDRAM_DQM[0] [OUT] – Control [CTRL] SDRAM_CLK[0] [OUT] 17-18 JTAG Boundary Scan Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 347 Control [CTRL] SDRAM_DQ[1] [IN/OUT] – Control [CTRL] SDRAM_DQ[0] [IN/OUT] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – Control [CTRL] Boundary Scan Chain Cells 17-19 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 348 – Control [CTRL] SIO_UART2_RX [IN] – Control [CTRL] SIO_SPI_CS[1] [OUT] – Control [CTRL] SIO_UART1_RX [IN/OUT] – Control [CTRL] SIO_IRRX [IN] – Control [CTRL] SIO_SPI_CS[0] [OUT] 17-20 JTAG Boundary Scan Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 349 – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – Control [CTRL] Boundary Scan Chain Cells 17-21 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 350 [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] 17-22 JTAG Boundary Scan Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 351 – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] Boundary Scan Chain Cells 17-23 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 352 [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] 17-24 JTAG Boundary Scan Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 353 – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – DUMMY [N/A] – Control [CTRL] Boundary Scan Chain Cells 17-25 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 354 – Control [CTRL] ATAPI_ADDR[1] [IN/OUT] – Control [CTRL] ATAPI_ADDR[3] [OUT] – Control [CTRL] ATAPI_ADDR[2] [OUT] – Control [CTRL] ATAPI_DATA[14] [IN/OUT] – Control [CTRL] ATAPI_IORDY [IN] 17-26 JTAG Boundary Scan Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 355: Specifications
LSI Logic Conﬁdential Chapter 18 Speciﬁcations This chapter speciﬁes the electrical, mechanical and AC timing characteristics of the DMN-8600. It also provides a table listing each pin in alpha-numeric order, with corresponding voltage levels, in these sections: • Section 18.1, “Electrical Speciﬁcations”...
Page 356: Operating Conditions
Supply Voltage for I/O 3.135 3.465 VDD_1.8 Core supply voltage 1.71 1.89 VDD_A Analog Voltage 3.135 3.465 Junction Temperature ˚C Temperatures θ Thermal resistance 14.0 ˚C (4-layer PCB) 18-2 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 357 – I/O Pin capacitance – – Power dissipation VDD Nominal @ 25 ˚C at 148.5 MHz – – 1. Not 100% tested, guaranteed by design characteristics. Electrical Speciﬁcations 18-3 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 358 LSI Logic Conﬁdential 18.2 AC Timing This section provides the AC timing for the DMN-8600 processor’s various interfaces and is divided into these sections: • Section 18.2.1, “Miscellaneous Timing,” page 18-5 • Section 18.2.2, “Host Master Timing,” page 18-6 •...
Page 359: Ac Timing
CLKI CLKO The DMN-8600 has eight general-purpose I/O pins, four of which can be used to interrupt the SPARC. They can be conﬁgured to be edge or level sensitive and must be asserted for at least two clock cycles, as shown Figure 18.2.
Page 360: Host Master Timing
Figure 18.2 General-Purpose I/O Timing GPIO (in) 18.2.2 Host Master Timing When in Master mode, the DMN-8600 controls an external slave device through use of an async master interface. The DMN-8600 master interface supports 68K and SRAM data strobe modes with either a self-paced or device-paced protocol.
Page 361: Self-Paced Async Master Write Cycle In Sram Mode
M_D (O) Figure 18.5 Self-Paced Async Master Read Cycle in 68K Mode M_A (O) M_CS (O) M_R/W (O) M_LDS/UDS (O) holdCS data_valid_begin2 M_D (I) data_valid_begin1 data_valid_end1 AC Timing 18-7 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 362: Self-Paced Async Master Write Cycle In 68K Mode
M_D (O) Figure 18.7 Device-Paced Async Master Read Cycle in 68K Mode M_A (O) M_R/W (O) M_CS (O) M_LDS/UDS (O) holdCS M_D (O) M_DTACK (I) M_WAIT (I) DTPW 18-8 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 363: Device-Paced Async Master Write Cycle In 68K Mode
Figure 18.8 Device-Paced Async Master Write Cycle in 68K Mode M_A (O) M_WR (O) M_CS (O) M_LDS/UDS (O) write_data_valid write_data_hold M_D (O) M_DTACK (I) M_WAIT (I) DTPW AC Timing 18-9 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 364: Device-Paced Async Master Read Cycle In Sram Mode
LSI Logic Conﬁdential Figure 18.9 Device-Paced Async Master Read Cycle in SRAM Mode M_A (O) M_UWE/LWE (O) M_CS (O) M_OE (O) holdCS M_D (I) M_DTACK (I) M_WAIT (I) DTPW 18-10 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 365: Device-Paced Async Master Write Cycle In Sram Mode
Figure 18.10 Device-Paced Async Master Write Cycle in SRAM Mode M_A (O) M_OE (O) M_CS (O) M_UWE/LWE (O) write_data_valid write_data_hold M_D (O) M_DTACK (I) M_WAIT (I) DTPW AC Timing 18-11 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 366: Multiplexed Address Async Master Read Cycle
This can be treated as hold time by an external + 2 ns device. Delay from M_A and R/W to fall of M_CS. CS clock cycles CS clock cycles − 5 ns + 3 ns 18-12 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 367 BH clock cycles − 3 ns 1. The parameters T and T represent the minimum possible window dur- data_valid_begin(n) data_valid_end(n) ing which the data pins must be stable. AC Timing 18-13 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 368: Host Slave Timing
18.2.3 Host Slave Timing The diagrams shown in Figures 18.12, 18.13, 18.14 18.15 give the slave mode read-from and write-to timing. 18-14 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 369: I-Mode Write Ac Timing Parameters
2 cycles 3 cycles WR hold time with respect to WAIT rising. 3.0 ns – WR hold time with respect to DTACK falling. 3.0 ns – AC Timing 18-15 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 370: I-Mode Read Ac Timing Diagram
1. H_WAIT and H_DTACK are pulled up by an internal pull-up on 3-state. 18.2.3.2 I-Mode Read AC Timing Figure 18.13 I-Mode Read AC Timing Diagram H_CS (I) H_RD (I) H_WAIT (O) H_DTACK (O) H_ADDR[2:0] (I) H_DATA[31:0] (I/O) 18-16 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 371: I-Mode Read Ac Timing Parameters
2.0 ns – RD holdtime with respect to H_DTACK falling. 2.0 ns – 1. H_WAIT and H_DTACK are pulled up by an internal pull-up on 3-state. AC Timing 18-17 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 372: M-Mode Write Ac Timing Parameters
2 cycles 3 cycles Output delay from H_CS rising to H_DTACK 3-state. 2 cycles 3 cycles H_CS hold time with respect to H_WAIT rising. 2.0 ns – 18-18 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 373: M-Mode Read
18.2.3.4 M-Mode Read AC Timing Figure 18.15 M-Mode Read AC Timing Diagram H_CS (I) H_RD/WR (I) H_WAIT (O) H_DTACK (O) H_ADDR[2:0] (I) VALID H_DATA[31:0] (I/O) VALID AC Timing 18-19 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 374: Sdram Interface Ac Timing
18.2.4.1 Clock Signals to SDRAM The clock signal to the SDRAM is driven from the DMN-8600. For SDR SDRAM, only the SDRAM_CLK output is used to connect to the clock input of the DRAM. For DDR SDRAM, the differential clock signal is used, and both SDRAM_CLK and SDRAM_CLK are connected to CLK and CLK of the DRAM, respectively.
Page 375: Sdram Clock Low And High Period Definition
Clock HIGH period in SDR mode HIGH Clock LOW period in SDR mode Clock HIGH period in DDR mode 0.45 0.55 Clock LOW period in DDR mode 0.45 0.55 AC Timing 18-21 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 376: Dmn-8600 Writing To Sdram In Sdr Mode
SDRAM reading, like writing, is also in burst mode. CAS latency for a DRAM read is programmed once during initialization of the memory chip. For SDR mode, it can be 2 or 3. 18-22 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 377: Dmn-8600 Reading From Sdram In Sdr Mode
The internal programmable clock will be able to capture the data up to the speciﬁed delay. 18.2.4.4 DMN-8600 Writing to SDRAM in DDR Mode For DDR mode, when writing into the SDRAM, DMN-8600 drives SDRAM_DQS signals together with the SDRAM_DQ pin. SDRAM_DQS AC Timing 18-23...
Page 378: Dmn-8600 Write To Sdram In Ddr Mode
Control pins include SDRAM_CAS, SDRAM_RAS, SDRAM_WE, and address pins include SDRAM_A[15:0], all of which are outputs of DoMiNo • SDRAM_DQ[31:0] and SDRAM_DQS[3:0] are driven from DMN-8600 for writes to SDRAM. 18-24 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 379: Dmn-8600 Read From Sdram In Ddr Mode
SDRAM_DQS signals together with the SDRAM_DQ pin. DQS pins are generally edge-aligned with the data on SDRAM_DQ. The strobe is delayed within DMN-8600 so that the edge can be used to sample data. Figure 18.20 DMN-8600 Read from SDRAM in DDR Mode...
Page 380: Cd Interface Timing
Table 18.16 CD Input Timing Symbol Description Units Cycle clock period CD_BCK HIGH pulse width HIGH CD_BCK LOW pulse width CD_DATA, CD_LRCK, CD_C2PO setup CD_DATA, CD_LRCK, CD_C2PO hold 18-26 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 381: Idc Interface Timing
IDC Design Values (in sysclk cycles) Param Description High period of SIO_SCL(I) M{(S+1)(R+1), 3} ------ HIGH Low period of SIO_SCL(I) M{(S+1)(F+1), 2} ------ Clock period of SIO_SCL(I) M{(S+1)[(R+1)+(F+1)], 4} ------ AC Timing 18-27 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 382 (IDC_RX_FILTER) register (see Section 15.5.3, “SIO IDC Registers”): S = IDCSAMP[3:0] R = IDCRISE[3:0] F = IDCFALL[3:0] • M{a,b} = Max{a,b} = greater of a and b 18-28 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 383: Idc Interface Ac Master Timing
The C parameter is a programmable (from 2 - 1023) register ﬁeld for output clock frequency located in the IDC Clock (IDC_CLOCK) register (see Section 15.5.3, “SIO IDC Registers”): C = IDCSCL[9:0] AC Timing 18-29 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 384: Audio Timing
Table 18.19 Audio Input/Output AC Timing Parameters Symbol Description Unit MCLK cycle clock period 19.2 MCLK high pulse width HIGH MCLK low pulse width 18-30 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 385: Uart Interface Timing
UART interface. Table 18.20 lists timing values for UART parameters. Figure 18.25 UART Interface AC Timing SIO_UART_TX (O) SIO_UART_RX (I) SIO_UART_RTS (O) SIO_UART_CTS (I) AC Timing 18-31 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 386: Video Interface Timing
AC timing for the DMN-8600 device Video interface. Figure 18.26 AC Timing for Video Input Stream at VI_CLK[0] HIGH VI_CLK[0] (I) VI_D[9:2] (I) Valid VI_VSYNC[0] (I) 18-32 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 387: Video Out Clock Source
Video Out OSync PLL Source VO_CLK Video out clock is internally generated; DMN-8600 drives out VO_CLK pin Don’t care VI_CLK[0]; DMN-8600 drived out VO_CLK pin VI_CLK[0]; DMN-8600 drived out VO_CLK pin Externally generated video output clock; VO_CLK pin in input...
Page 388 5.0 (27 MHz) (74.25 MHz) Output data valid time VO_D[15:0] after the rising edge of VO_CLK Output data hold time for VO_D[15:0] after the rising edge of VO_CLK 18-34 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 389: Ir Interface Timing
LSI Logic Conﬁdential 18.2.10 IR Interface Timing DMN-8600 has two IR modules: one with full-duplex operation (TX and RX), and one with TX-only functionality. The DMN-8600 IR modules ofﬂoad most of the formatting and protocol issues to software; for transmit, the IR module generates waveforms with the programmed pulse length and period characteristics, while for receive, it simply measures the period and duty cycle of incoming pulses.
Page 390: Jtag Interface Signal Timing
IR ticks that IRRX is high. IR ticks IR ticks 18.2.11 JTAG Interface Signal Timing The timing parameters for the JTAG interface are shown in Figure 18.29 and described in Table 18.25. 18-36 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 391: Jtag Interface Timing Diagram
TDI, TMS, RST setup time to TCK – 10.0 TDI, TMS, RST hold time from TCK – TDO delay time from TCK – TDO hold time from CLK – AC Timing 18-37 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 392: Atapi Ac Timing
ATAPI_DIOR/ATAPI_DIOW 16-bit (min) RWTime * C ATAPI_DIOR data access (max) ATAPI_DIOR data hold (min) ATAPI_DIOR data setup (min) ATAPI_DIOW data setup (min) ATAPI_DIOW data hold (min) RWHold * C 18-38 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 393 ATAPI_DIOW to ATAPI_DMARQ delay (max) ATAPI_DMAACK to 3-state (max) 1. This timing only applies to a single DMA transfer. “C” is the system clock cycle time. AC Timing 18-39 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 394: Atapi Pio Read And Write Timing
(RWTime * (min) * C) * C) * C) ATAPI_DIOR/ ATAPI_DIOW recovery (RWRcv * (RWRcv * (RWRcv * (RWRcv * (RWRcv * time (min) ATAPI_DIOW data setup (min) 18-40 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 395: Sd Interface Timing
The SD interface is used to read or write the data from or to the DVD drives. The SD synchronous read and write timing diagram is shown in Figure 18.32. AC Timing 18-41 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 396: Sd Interface Timing
Description Input Transition Time 2.0 ns 5.0 ns Ouput Load 10 pF 60 pF SD_CLK period 20 ns 37 ns SD_CLK high 9 ns 16 ns HIGH 18-42 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 397: Spi Interface Timing
4 ns 18 ns SD_DATA and SD_SECSTART output delay 1. Note: Light loading (50 MHz) is for point-to-point connections in a multi-DMN-8600 conﬁguration. 18.2.14 SPI Interface Timing Figure 18.33 shows typical AC timing parameters for DMN-8600 SPI transfers. The parameter values are listed in Table 18.29.
Page 398: 1394 Timing
Unit 49.152 ± 100 ppm 49.152 ± 100 ppm BIO_PHY_CLK frequency BIO_PHY_CLK High time HIGH BIO_PHY_CLK Low time BIO_PHY_CLK duty cycle BIO_PHY_CLK Rise time BIO_PHY_CLK Fall time 18-44 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 399 BIO_PHY_CLK input high to BIO_PHY_DATA[0:7] and BIO_PHY_CTL[0:1] invalid (high-impedance) Setup time: BIO_PHY_DATA[0:7], BIO_PHY_CTL[0:1], and BIO_LREQ inputs before BIO_PHY_CLK Hold time: BIO_PHY_DATA[0:7], BIO_PHY_CTL[0:1], and BIO_LREQ inputs after BIO_PHY_CLK AC Timing 18-45 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 400 BIO_PHY_CLK input high to BIO_PHY_DATA[0:7] and BIO_PHY_CTL[0:1] invalid (high-impedance) Setup time BIO_PHY_DATA[0:7] , BIO_PHY_CTL[0:1] , and BIO_LREQ inputs before BIO_PHY_CLK Hold time BIO_PHY_DATA[0:7] , BIO_PHY_CTL[0:1] , and BIO_LREQ inputs after BIO_PHY_CLK 18-46 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 401: Sbp Interface Timing
Figure 18.39 SBP Clock Timing HIGH Figure 18.40 SBP Incoming Transfer (POL = 1, WRREQ = 0) SBP_CLK (I) SBP_REQ (O) SBP_RD (O) SBP_ACK (I) SBP_FRAME (I/O) SBP_DATA[7:0] (I/O) AC Timing 18-47 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 402: Sbp Outgoing Transfer (Pol = 1, Wrreq = 0)
SBP_ACK (I) SBP_FRAME (I/O) SBP_DATA[7:0] (I/O) Figure 18.42 SBP Incoming Transfer (POL = 0,WRREQ = 0) SBP_CLK (I) SBP_REQ (O) SBP_RD (O) SBP_ACK (I) SBP_FRAME (I/O) SBP_DATA[7:0] (I/O) 18-48 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 403: Sbp Outgoing Transfer (Pol = 0, Wrreq = 0)
SBP_RD output delay time 12.0 18.0 SBP_DATA input setup time SBP_DATA input hold time 1.25 1.25 SBP_ACK input setup time SBP_ACK input hold time 1.25 1.25 AC Timing 18-49 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 404: Pin Description
Light loading (50 MHz) is for point-to-point connections only (in a multi-DMN-8600 conﬁguration). 18.3 Pin Description The DMN-8600 is packaged in a 308-pin Ball Grid Array (BGA) package and is drop-in pin compatible, presenting OEMs with unprecedented ﬂexibility and cost reduction in their product lines.
Page 405: Dmn-8600 Pin List
CLKI XVDD CLKO AI_MCLKO AO_SCLK AO_D[3] SDRAM_WE 2.5/3.3 SDRAM_A[2] 2.5/3.3 SDRAM_A[15] 2.5/3.3 SDRAM_A[0] 2.5/3.3 SDRAM_A[5] 2.5/3.3 NO CONNECT VI_D[2] 3.3/5 VI_D[7] 3.3/5 NO CONNECT NO CONNECT Pin Description 18-51 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 406 SDRAM_A[4] 2.5/3.3 SDRAM_A[1] 2.5/3.3 SDRAM_A[7] 2.5/3.3 VI_VSYNC[0] 3.3/5 VI_D[4] 3.3/5 VI_D[3] 3.3/5 VI_D[6] 3.3/5 NO CONNECT NO CONNECT VSS_A GROUND – VSS_A GROUND – VSS_X GROUND – 18-52 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 407 SDRAM_A[14] 2.5/3.3 VO_D[13] NO CONNECT VI_D[5] 3.3/5 VDD_1.8 – VDD_3.3 – NO CONNECT TRST VDD_A – VDD_A – VDD_RREF – AI_D[1] AO_FSYNC AO_D[0] VDD_2.5 2.5/3.3 – Pin Description 18-53 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 408 – VDD_3.3 – VDD_1.8 – SDRAM_A[12] 2.5/3.3 SDRAM_A[13] 2.5/3.3 SDRAM_DQ[25] 2.5/3.3 SDRAM_DQS[3] 2.5/3.3 (For DDR parts only) VO_D[7] VO_D[8] VO_D[11] VO_D[15] SDRAM_A[11] 2.5/3.3 SDRAM_DQ[26] 2.5/3.3 SDRAM_DQ[30] 2.5/3.3 18-54 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 409 SDRAM_CLK[1] 2.5/3.3 VO_CLK VO_D[1] VO_D[2] VO_D[3] – – – – – – SDRAM_DQ[29] 2.5/3.3 SDRAM_DQ[22] 2.5/3.3 SDRAM_DQ[23] 2.5/3.3 SDRAM_CLK[1] 2.5/3.3 (For DDR parts only) BIO_PHY_DATA[4] BIO_PHY_DATA[0] Pin Description 18-55 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 410 2.5/3.3 SDRAM_DQS[2] 2.5/3.3 (For DDR parts only) SDRAM_DQ[19] 2.5/3.3 BIO_PHY_DATA[5] BIO_PHY_DATA[6] BIO_PHY_DATA[7] BIO_LINK_ON VDD_3.3 – GROUND – GROUND – GROUND – GROUND – GROUND – GROUND – 18-56 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 411 – GROUND – GROUND – GROUND – GROUND – VDD_2.5 2.5/3.3 – SDRAM_DQM[1] 2.5/3.3 SDRAM_DQ[8] 2.5/3.3 SDRAM_DQ[11] 2.5/3.3 SDRAM_DQ[13] 2.5/3.3 BIO_LREQ BIO_PHY_DATA[3] BIO_PHY_DATA[2] ATAPI_DATA[8] 3.3/5 SBP_DATA[0] Pin Description 18-57 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 412 2.5/3.3 ATAPI_DATA[7] 3.3/5 SD_DATA[7] ATAPI_DATA[6] 3.3/5 SD_DATA[6] ATAPI_DATA[9] 3.3/5 SBP_DATA[1] ATAPI_DATA[5] 3.3/5 SD_DATA[5] GROUND – GROUND – GROUND – GROUND – GROUND – GROUND – SDRAM_DQM[0] 2.5/3.3 18-58 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 413 SDRAM_CLK[0] 2.5/3.3 ATAPI_DATA[11] 3.3/5 SBP_DATA[3] ATAPI_DATA[12] 3.3/5 SBP_DATA[4] ATAPI_DATA[1] 3.3/5 SD_DATA[1] CD_LRCK ATAPI_DATA[0] 3.3/5 SD_DATA[0] CD_DATA SDRAM_DQ[0] 2.5/3.3 SDRAM_DQ[2] 2.5/3.3 SDRAM_DQS[0] 2.5/3.3 (For DDR parts only) Pin Description 18-59 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 414 2.5/3.3 SDRAM_DQ[3] 2.5/3.3 ATAPI_DMAACK SD_SECSTART 3.3/5 ATAPI_DATA[14] 3.3/5 SBP_DATA[6] ATAPI_ADDR[3] SBP_REQ VDD_1.8 – VDD_5 – H_DATA[23] 3.3/5 M_A[24] H_INT op dr O M_GPIO[0] 3.3/5 H_RD/WR 3.3/5 M_RD/WR 18-60 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 415 VDD_DLL – VSS_DLL GROUND – SIO_SPI_MOSI M_A[25] SIO_UART2_TX SIO_UART1_TX M_A[4] ATAPI_ADDR[2] SBP_RD ATAPI_ADDR[1] SBP_ACK 3.3/5 ATAPI_DIOR SD_RDREQ ATAPI_ADDR[4] SBP_CLK 3.3/5 H_DATA[29] 3.3/5 M_CS[3] H_DATA[26] 3.3/5 M_CS[0] Pin Description 18-61 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 416 H_DATA[7] 3.3/5 M_A[13]/M_D[7] H_DATA[3] 3.3/5 M_A[9]/M_D[3] H_DMAREQ M_UWE/UDS SIO_SPI_CS[2] M_A[22] SIO_UART1_CTS M_RD/WR SIO_SPI_CS[1] M_A[23] SIO_SCL 3.3/5 SIO_UART1_RTS M_A[3] ATAPI_DMARQ 3.3/5 SD_ERROR ATAPI_INTRQ 3.3/5 SD_ACK ATAPI_ADDR[0] SBP_FRAME 3.3/5 18-62 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 417 H_DATA[9] 3.3/5 M_A[15]/M_D[9] H_DATA[6] 3.3/5 M_A[12]/M_D[6] H_DATA[2] 3.3/5 M_A[8]/M_D[2] H_DATA[1] 3.3/5 M_A[7]/M_D[1] H_DATA[0] 3.3/5 M_A[6]/M_D[0] H_RST 3.3/5 M_RST SIO_IRTX2 M_OE SIO_SPI_CS[3] M_A[5] SIO_UART1_RX M_CS[0] SIO_UART2_RX 3.3/5 Pin Description 18-63 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 418 M_A[4] H_CS 3.3/5 M_GPIO[5] 3.3/5 H_RD 3.3/5 M_GPIO[4] 3.3/5 H_DATA[15] 3.3/5 M_A[21]/M_D[15] H_DATA[11] 3.3/5 M_A[17/M_D[11] H_ADDR[0] 3.3/5 M_GPIO[1] 3.3/5 H_DATA[4] 3.3/5 M_A[10]/M_D[4] M_OE MCONFIG[1] 3.3/5 SIO_SPI_CLK M_A[26] 18-64 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 419 SDRAMs and are used for high-performance, non-power critical applications. Note: The DMN-8600 core operates at 1.8 V 5%. Some I/O interface pins can be interfaced with 3.3 V or 5 V devices depending on the voltage applied to the VDD pins associated with them.
Page 420 1. For DDR parts only. DDR refers to Double Data Rate SDRAMs, which have double the bandwidth of standard SDRAMs and are used for high-performance, nonpower critical applications. 18-66 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 421 SIO_SPI_CS[0] DQ[11] DQS[1] SDRAM_DQ[9] SDRAM_DQ[7] DQS[0] SDRAM_DQ[1] SIO_SCL M_CS[0] M_A[24] SIO_UART1_ SIO_UART1_ SDRAM_ SDRAM_ SDRAM_ SDRAM_ SIO_UART2_ DQ[13] DQ[10] CLK[0] CLK[0] SDRAM_DQ[5] SDRAM_DQ[3] M_A[4] M_A[3] SIO_IRRX Pin Description 18-67 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 422: Bga Alphabetical Pin List
1. For DDR parts only. DDR refers to Double Data Rate SDRAMs, which have double the bandwidth of standard SDRAMs and are used for high-performance, nonpower critical applications. 18-68 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 423 VDD_3.3 VO_CLK VSS_DLL VO_D[2] VDD_5 VO_D[0] VSS_RREF VO_D[3] VDD_A VO_D[10] VSS_X VO_D[4] VDD_A VO_D[11] XVDD VO_D[5] VDD_A VO_D[12] VO_D[6] VDD_A VO_D[13] NC pins are not connected. Pin Description 18-69 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 424: Package Mechanical Specifications
LSI Logic Conﬁdential 18.4 Package Mechanical Speciﬁcations This section provides the dimensions and recommended manufacturing conditions for the DMN-8600 processor. 18.4.1 Package Dimensions The DMN-8600 processor is available in a 308-pin ball grid array (BGA) package illustrated in Figure 18.45. 18-70 Speciﬁcations...
Page 425 3. Minimum clearance of 0.25 mm between the edge of the solder ball and the body edge. Important: This drawing may not be the latest version. Package Mechanical Speciﬁcations 18-71 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 426: Recommended Manufacturing Conditions
Package Case Temperature 220˚C Peak Temperature Hold Time 10 s maximum High Temperature Region Hold Time 60 s maximum @ 183 ˚C Cooling Rate 5 ˚C/s maximum 18-72 Speciﬁcations Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 427: Chapter A Register Listing
IDC DMA Receive Address Pointer 3 Register (IDC_RX_ADDR_PTR3_ADDR) 15-48 IDC DMA Receive Address Pointer 4 Register (IDC_RX_ADDR_PTR4_ADDR) 15-49 IDC DMA Receive Control Register (IDC_RX_CONTROL_REG_ADDR) 15-45 DMN-8600 DVD Recorder System Processor Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 428 IR1 Receive Tick Count Register (IR1_RTC) 15-52 IR1 Receive Tick Period Register (IR1_RTP) 15-52 IR1 Transmit Carrier Wave Period Register (IR1_CWP) 15-49 IR1 Transmit Carrier Wave Pulse High Register (IR1_CWPH) 15-50 Register Listing Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 429 15-79 SPI DMA Receive Control Register (SPI_RX_CONTROL_REG_ADDR) 15-76 SPI DMA Receive Status Register (SPI_RX_STATUS_REG_ADDR) 15-77 SPI DMA Size Register (SPI_DMASIZE) 15-68 SPI DMA Transmit Address Pointer1 Register (SPI_TX_ADDR_PTR1_ADDR) 15-74 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 430 15-95 UART1 Interrupt Enable Register / Divisor Latch MSB Register (UART1_IER0_DLM1) 15-82 UART1 Interrupt Identification / FIFO Control Register (UART1_IIR_FCR) 15-85 UART1 Interrupt Identification Register (IIR) 15-86 Register Listing Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 431 UART2 Modem Status Register (UART2_MSR) 15-93 UART2 Receive Buffer / Transmit Holding / Divisor Latch LSB Register (UART2_RBR0_THR0_DLL1) 15-80 UART2 Scratch Pad Register (UART2_SPR) 15-94 Version Register 8-16 Video Control Register 11-7 Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 432 LSI Logic Conﬁdential Video Output Clock Control Register 16-6 Video Overlay Control Register 11-20 Video Status Register 11-15 Wake Up Source Register 16-11 Register Listing Copyright © 2001, 2002 by LSI Logic Corporation. All rights reserved.
Page 434 Fax your comments to: LSI Logic Corporation Technical Publications M/S E-198 Fax: 408.433.4333 Please tell us how you rate this document: DMN-8600 DVD Recorder System Processor. Place a check mark in the appropriate blank for each category. Excellent Good Average Fair...

LSI DMN-8600 Technical Manual

Chapter 1 Overview Chapter 2 Application Example

Chapter 2 Application Example Chapter 3 Internal Architecture

Chapter 3 Internal Architecture Chapter 4

Chapter 4 Functional Description

Chapter 5 Programmability (C-Ware) Chapter 6

Chapter 6 Signal Descriptions Chapter 7

Chapter 7 Memory Mapping

Chapter 8 Host Slave Interface

Chapter 9 Secondary Bitstream Interface

Chapter 10 Host Async Master Interface

Chapter 11 Video Interface

Chapter 12 Audio Interface

Chapter 13 SDRAM Interface

Chapter 14 Bitstream I/O (Storage) Port

Chapter 15 Serial I/O Port

Chapter 16 Clock Control and Power Management

Chapter 17 JTAG Boundary Scan

Chapter 18 Specifications

Chapter a Register Listing

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Summary of Contents for LSI DMN-8600