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Terasic Altera Dual-XAUI User Manual

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Summary of Contents for Terasic Altera Dual-XAUI

  • Page 2: Table Of Contents

    CONTENTS CHAPTER 1 INTRODUCTION ..........................3 1.1 Features ..................................3 1.2 Getting Help................................4 CHAPTER 2 ARCHITECTURE..........................5 2.1 Block Diagram ................................6 CHAPTER 3 PIN DESCRIPTION ..........................8 3.1 HSMC Expansion Connector ............................ 8 CHAPTER 4 COMPONENTS ..........................17 4.1 Featured Device: BCM8727 (U6) ...........................

  • Page 3: Chapter 1 Introduction

    Chapter 1 Introduction This board is intended to be used by customers to implement and design 10G Ethernet systems based on transceiver host boards that support XAUI interfaces. This mezzanine card is intended to be part of an openly sold Development Kit and can be bundled with packages of Software and IP Cores.

  • Page 4: Getting Help

    Figure 1-1 Picture of the Dual XAUI to SFP+ HSMC board Getting Help Getting Help Here are some places to get help if you encounter any problem: • Email to support@terasic.com • Taiwan & China: +886-3-550-8800 • Korea : +82-2-512-7661 • Japan: +81-428-77-7000...

  • Page 5: Chapter 2 Architecture

    Chapter 2 Architecture This chapter describes the architecture of the Dual XAUI to SFP+ HSMC board including block diagram and components. Figure 2-1 The Dual XAUI to SFP+ HSMC PCB and component diagram A photograph of the Dual XAUI to SFP+ HSMC board is shown in 2-1.

  • Page 6: Block Diagram

    Block Diagram Block Diagram shows the block diagram of the Dual XAUI to SFP+ HSMC board. Figure 2-2 Figure 2-2 Block diagram of the Dual XAUI to SFP+ HSMC board The XAUI interfaces will be attached to the HSMC side of the card and the SFI side of the interface will be attached to the SFP+ optical modules on the opposite side of the board.
  • Page 7 Two SFP+ connectors and cages combined with a SFP+ optical module (not provided with the board) form the 10GE optical interface. The SFP+ modules communicate with the BCM8727 via the serial SFI protocol. The SFP interface connector is 20 pins. Most SFP+ optical modules will contain status and configuration registers accessible through an I2C port.

  • Page 8: Chapter 3 Pin Description

    Chapter 3 Pin Description This chapter describes the detailed information of the connector interfaces, and the pin description on the Dual XAUI to SFP+ HSMC board. HSMC Expansion Connector HSMC Expansion Connector The Dual XAUI to SFP+ HSMC board contains a HSMC connector. Figure 3-1, Figure 3-2 and Figure 3-3 show the pin-outs of the HSMC connector on the Dual XAUI to SFP+ HSMC board.
  • Page 9 Figure 3-1 Pin-outs of Bank 1 on the HSMC connector...
  • Page 10 Figure 3-2 Pin-outs of Bank 2 on the HSMC connector...
  • Page 11 Figure 3-3 Pin-outs of Bank 3 on the HSMC connector...
  • Page 12 Table 3-1 shows the pin description of the HSMC connector. Table 3-1 The pin mappings of the HSMC connector HSMC Schematic Net Connections Board Reference Signal Name IO Standard Function Pin (J6) CONFIG0_1 CMOS Configuration mode channel 1, bit 0. Internally pulled down.
  • Page 13 PCMULK1 LVTTL PMD CMU Lock Detect Channel 1. PCMULK2 LVTTL PMD CMU Lock Detect Channel 2. PHYRESET LVTTL PHY Reset, Active low. PLOSB1 LVTTL PMD Loss of Signal Channel 1. PLOSB2 LVTTL PMD Loss of Signal Channel 2. PRTAD01 CMOS Channel 1 PHY Address LSB.
  • Page 14 XAUI_RX_2N0 Differential XAUI Parallel Receive Data Output Channel 2, lane D, negative leg. XAUI_RX_2N1 Differential XAUI Parallel Receive Data Output Channel 2, lane C, negative leg. XAUI_RX_2N2 Differential XAUI Parallel Receive Data Output Channel 2, lane B, negative leg. XAUI_RX_2N3 Differential XAUI Parallel Receive Data Output Channel 2, lane A, negative leg.
  • Page 15 XAUI_TX_2P1 Differential XAUI Parallel Transmit Data Input Channel 2, lane C, positive leg. XAUI_TX_2P2 Differential XAUI Parallel Transmit Data Input Channel 2, lane B, positive leg. XAUI_TX_2P3 Differential XAUI Parallel Transmit Data Input Channel 2, lane A, positive leg. CLK_OE Clock Output Enable, active low.
  • Page 16 USER_LED_G6 CMOS User LED Green 6 USER_LED_G7 CMOS User LED Green 7 USER_LED_R0 CMOS User LED Red 0 USER_LED_R1 CMOS User LED Red 1 USER_LED_R2 CMOS User LED Red 2 USER_LED_R3 CMOS User LED Red 3 USER_LED_R4 CMOS User LED Red 4 USER_LED_R5 CMOS User LED Red 5...

  • Page 17: Chapter 4 Components

    Chapter 4 Components This section introduces all of the important components on the XAUI to SFP+ HSMC board. Featured Device: BCM8727 (U6) Featured Device: BCM8727 (U6) The BCM8727 is a dual-channel 10-GbE SFI-to-XAUI™ transceiver that incorporates an Electronic Dispersion Compensation (EDC) equalizer supporting SFP+ line-card applications. The BCM8727 is a multi-rate PHY targeted for SMF, MMF, or copper twin-ax applications interfacing to both limiting-based and linear-based SFP+ and SFP modules.
  • Page 18 LASI1 CMOS Link Alarm Status Interrupt Channel 1. LASI2 CMOS Link Alarm Status Interrupt Channel 2. MDC2 CMOS Management Data Clock single device (default), Management Data Clock channel 2 for dual MDIO device. MDIO2 CMOS Management Data I/O for single MDIO device (default), Management Data I/O channel 2 for dual MDIO device.
  • Page 19 differential clock.. PHYRESET LVTTL PHY Reset, Active low. PLOSB1 LVTTL PMD Loss of Signal Channel 1. PLOSB2 LVTTL PMD Loss of Signal Channel 2. PRTAD01 CMOS Channel 1 PHY Address LSB. PRTAD02 CMOS Channel 2 PHY Address LSB PRTAD1 CMOS PHY Address bit 1.
  • Page 20 SFP_TXDIS1 LVTTL, Optical Transmitter Enable channel 1. Open drain SFP_TXDIS2 LVTTL, Optical Transmitter Enable channel 2. Open drain SMBSCL1 LVTTL, Serial Clock channel 1. Open drain SMBSCL2 LVTTL, Serial Clock channel 2. Open drain SMBSDA1 LVTTL, Serial Data channel 1. Open drain SMBSDA2...
  • Page 21 1, lane A, positive leg. XAUI_RX_2N0 Differential XAUI Parallel Receive Data Output Channel 2, lane D, negative leg. XAUI_RX_2N1 Differential XAUI Parallel Receive Data Output Channel 2, lane C, negative leg. XAUI_RX_2N2 Differential XAUI Parallel Receive Data Output Channel 2, lane B, negative leg. XAUI_RX_2N3 Differential XAUI Parallel Receive Data Output Channel...

  • Page 22: General User Input/Output

    2, lane D, positive leg. XAUI_TX_2P1 Differential XAUI Parallel Transmit Data Input Channel 2, lane C, positive leg. XAUI_TX_2P2 Differential XAUI Parallel Transmit Data Input Channel 2, lane B, positive leg. XAUI_TX_2P3 Differential XAUI Parallel Transmit Data Input Channel 2, lane A, positive leg. General User Input/Output General User Input/Output This board has eight dual color (Green/Red) surface mount LEDs are provided for general purpose...

  • Page 23: Clocks

    Clocks Clocks Figure 4-1 shows the XAUI to SFP+ HSMC board clock diagram. Figure 4-1 XAUI to SFP+ HSMC Clocking Diagram...

  • Page 24: Memory Devices

    All signal names and clock pin positions are located in Table 4-3. Table 4-3 XAUI to SFP+ HSMC Board Clock Distribution Signal Frequency Signal Name Originates Signal Propagates To From 156.25 HSM_CLK_P U16.13 J16.156 HSM_CLK_N U16.14 J16.158 U6.T10 U6.R10 156.25 PEXTCLK156_P U16.17 PEXTCLK156_N...
  • Page 25 Table 4-5 256 Kbit Serial SPI EEPROM (25LC256IST) Pinout Board Signal Name IO Standard Function Reference U14.1, SS_N1 3.3V Chip Select (Active low) U15.1 SS_N2 U14.2, MISO1 3.3V Serial Data Output U15.2 MISO2 U14.3, Pull-up resistor to 3.3V Write Protect (Active low) U15.3 3.3V U14.4,...

  • Page 26: Power

    Power Power Power is supplied to the board from the 12V supply of the host board. Figure 4-2 shows the power distribution. Figure 4-2 Power Tree of Dual XAUI to SFP+ HSMC Board...

  • Page 27: Board Setup And Test Designs

    Chapter 5 Board Setup and Test Designs Two host platforms that this board has successfully been tested on are the Stratix IV GX production device development kit and the Arria II GX development kit. The Arria II GX development kit only utilizes the HSMC port A, so this kit can only use SFP+ port 1.

  • Page 28: Test Designs Using Stratix Iv Gx Fpga Development Kit Platform

    Test Designs Using Stratix IV GX FPGA Development Test Designs Using Stratix IV GX FPGA Development Kit Platform Kit Platform XAUI to SFP+ Module 10G Channel Optical Loopback This design tests the dual XAUI to SFI interface using the Stratix IV GX FPGA Dev Kit platform. The Stratix IV GX transmits and receives 3.125G XAUI signals on four transceivers for each of the two channels utilized.
  • Page 29 5) Power on the Stratix IV GX FPGA development kit board 6) Program the Stratix IV GX FPGA development kit with the "hsmc_loopback.sof" On the Stratix IV GX FPGA development kit: 7) Press and release cpu_resetn (S2). 8) Press and release user_pb[0] -- the rx is now ready to search for a prbs seed pattern 9) Press and release both cpu_resetn, user_pb[1] and user_pb[2] simultaneously - Resets the BCM8727C device and the + SFP module(s) 10) Reset Module (It should be OK to skip this one, but include these steps if your board is failing)
  • Page 30 XAUI to SFP+ Module 10G Channel-to-Channel Optical Loopback This design tests the dual XAUI to SFI interface using the Stratix IV GX FPGA Dev Kit platform. The Stratix IV GX transmits 3.125G XAUI signals on the four lanes of channel 1 and the return signal is received on channel 2.
  • Page 31 7) Press and release cpu_resetn (S2). 8) Press and release user_pb[0] -- the rx is now ready to search for a prbs seed pattern 9) Press and release both cpu_resetn, user_pb[1] and user_pb[2] simultaneously - Resets the BCM8727C device and the + SFP module(s) 10) Reset Module (It should be OK to skip this one, but include these steps if your board is failing) A) Set USER_DIPSW[7:0] = [00000000] (Program MDIO to reset module) B) Press and release user_pb[1]...
  • Page 32 channel 2 input. The SFP+ module receives the 10G electrical and sends it to the BCM8727 PHY. The PHY then converts the 10G signal into four 3.125G XAUI output signals and transmits them on channel 2 to the Stratix IV GX device through the HSMC connector. The same process is followed for the channel 2 transmitter to channel 1 receiver.
  • Page 33 C) Press and release user_pb[2] 11) To Flip XAUI Lanes A) Set USER_DIPSW[7:0] = [00000100] (Program MDIO to flip XAUI lanes) B) Press and release user_pb[1] C) Press and release user_pb[2] 12) Set pre-emphasis (for example, if using an SFP+ 12 meter cable) A) USER_DIPSW[7:0] = [11100110] B) Press and release user_pb[1] C) Press and release user_pb[2]...
  • Page 34 Figure 5-4 Signal Tap Display...

  • Page 35: Chapter 6 Appendix

    Chapter 6 Appendix Revision History Revision History Version Change Log V1.0 Initial Version (Preliminary) Copyright Statement Copyright Statement Copyright © 2010 Terasic Technologies. All rights reserved.
  • Page 36 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Terasic P0092...

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