Infineon Cypress S29GL01GS Manual
  1. Manuals
  2. Brands
  3. Infineon Manuals
  4. Storage
  5. Cypress S29GL01GS
  6. Manual
Infineon Cypress S29GL01GS Manual

Infineon Cypress S29GL01GS Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as "Cypress" document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the Cypress S29GL01GS and is the answer not in the manual?

Questions and answers

Summary of Contents for Infineon Cypress S29GL01GS

  • Page 1 The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio.

  • Page 2: Distinctive Characteristics

    S29GL01GS/S29GL512S S29GL256S/S29GL128S 1-Gbit (128 Mbyte)/512-Mbit (64 Mbyte)/ 256-Mbit (32 Mbyte)/128-Mbit (16 Mbyte), 3.0 V, GL-S Flash Memory General Description ® ® The Cypress S29GL01G/512/256/128S are MirrorBit Eclipse flash products fabricated on 65 nm process technology. These devices offer a fast page access time as fast as 15 ns with a corresponding random access time as fast as 90 ns. They feature a Write Buffer that allows a maximum of 256 words/512 bytes to be programmed in one operation, resulting in faster effective programming time than standard programming algorithms.

  • Page 3: General Description

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Performance Summary Maximum Read Access Times Random Access Page Access Time CE# Access Time OE# Access Time Density Voltage Range Time (t PACC Full V 128 Mb VersatileIO V Full V 256 Mb VersatileIO V Full V 512 Mb VersatileIO V Full V 1 Gb...

  • Page 4: Table Of Contents

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Contents General Description ............. 2 9.4 Read ................67 9.5 Write ................68 Distinctive Characteristics ..........2 10. Electrical Specifications..........69 Performance Summary ............3 10.1 Absolute Maximum Ratings .......... 69 Product Overview ............4 10.2 Latchup Characteristics ..........69 10.3 Thermal Resistance ............

  • Page 5: Product Overview

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Product Overview The GL-S family consists of 128-Mbit to 1Gbit, 3.0 V core, Versatile I/O, non-volatile, flash memory devices. These devices have a 16-bit (word) wide data bus and use only word boundary addresses. All read accesses provide 16 bits of data on each bus transfer cycle.
  • Page 6 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 1.1 S29GL-S Address Map Type Count Addresses Address within Page A3–A0 Address within Write Buffer A7–A0 Page 4096 A15–A4 Write-Buffer-Line A15–A8 1024 (1 Gb) 512 (512 Mb) Sector –A16 256 (256 Mb) 128 (128 Mb) The device control logic is subdivided into two parallel operating sections, the Host Interface Controller (HIC) and the Embedded Algorithm Controller (EAC).

  • Page 7: Address Space Maps

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Software Interface 2. Address Space Maps There are several separate address spaces that may appear within the address range of the flash memory device. One address space is visible (entered) at any given time.  Flash Memory Array: the main non-volatile memory array used for storage of data that may be randomly accessed by asynchronous read operations.

  • Page 8: Flash Memory Array

    S29GL01GS/S29GL512S S29GL256S/S29GL128S While in EA mode, only a Program / Erase suspend command or the Status Register Read command will be accepted. All other commands are ignored. Thus, no other ASO may be entered from the EA mode. When an Embedded Algorithm is suspended, the Data Polling ASO is visible until the device has suspended the EA. When the EA is suspended the Data Polling ASO is exited and Flash Array data is available.

  • Page 9: Device Id And Cfi (Id-Cfi) Aso

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 2.4 S29GL128S Sector and Memory Address Map Address Range Sector Size (kbyte) Sector Count Sector Range Notes (16-Bit) SA00 0000000h–000FFFFh Sector Starting Address – SA127 07F0000h–07FFFFFh Sector Ending Address Note: These tables have been condensed to show sector related information for an entire device on a single page Sectors and their address ranges that are not explicitly listed (such as SA001-SA510) have sectors starting and ending addresses that form the same pattern as all other sectors of that size.

  • Page 10: Device Id And Common Flash Interface (Id-Cfi) Aso Map - Automotive Only

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Device ID and Common Flash Interface (ID-CFI) ASO Map — Automotive Only Example of Hex Read Out of Example Word Address Data Field # of bytes Data Format Actual Data Data Size of Electronic (SA) + 0080h 0013h Marking Revision of Electronic (SA) + 0081h...

  • Page 11: Status Register Aso

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Status Register ASO The Status Register ASO contains a single word of registered volatile status for Embedded Algorithms. When the Status Register read command is issued, the current status is captured (by the rising edge of WE#) into the register and the ASO is entered. The Status Register content appears on all word locations.

  • Page 12: Sector Protection Control

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Sector Protection Control 2.7.1 Lock Register ASO The Lock register ASO contains a single word of OTP memory. When the ASO is entered the Lock Register appears at all word locations in the device address space. See Figure 11.16 on page 87 for ASO Entry timing requirements.
  • Page 13 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 2.7 ECC Status Word – Upper Byte Name Value Table 2.8 ECC Status Word – Lower Byte Single Bit Error corrected in the 8-bit Single Bit Error corrected in Name error correction code 16 words of data 0 = No Error Corrected 0 = No Error Corrected Value...

  • Page 14: Data Protection

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Data Protection The device offers several features to prevent malicious or accidental modification of any sector via hardware means. Device Protection Methods 3.1.1 Power-Up Write Inhibit RESET#, CE#, WE#, and, OE# are ignored during Power-On Reset (POR). During POR, the device can not be selected, will not accept commands on the rising edge of WE#, and does not drive outputs.

  • Page 15: Sector Protection Methods

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Sector Protection Methods 3.4.1 Write Protect Signal If WP# = V , the lowest or highest address sector is protected from program or erase operations independent of any other ASP configuration. Whether it is the lowest or highest sector depends on the device ordering option (model) selected. If WP# = V , the lowest or highest address sector is not protected by the WP# signal but it may be protected by other aspects of ASP configuration.
  • Page 16 S29GL01GS/S29GL512S S29GL256S/S29GL128S The Persistent Protection method sets the PPB Lock to 1 during POR or Hardware Reset so that the PPB bits are unprotected by a device reset. There is a command to clear the PPB Lock bit to 0 to protect the PPB bits. There is no command in the Persistent Protection method to set the PPB Lock bit therefore the PPB Lock bit will remain at 0 until the next power-off or hardware reset.
  • Page 17 S29GL01GS/S29GL512S S29GL256S/S29GL128S 3.4.6 Sector Protection States Summary Each sector can be in one of the following protection states:  Unlocked – The sector is unprotected and protection can be changed by a simple command. The protection state defaults to unprotected after a power cycle or hardware reset. Dynamically Locked –...
  • Page 18 S29GL01GS/S29GL512S S29GL256S/S29GL128S As shipped from the factory, all devices default to the Persistent Protection method, with all sectors unprotected, when power is applied. The device programmer or host system can then choose which sector protection method to use. Programming either of the following two, one-time programmable, non-volatile bits, locks the part permanently in that mode: ...
  • Page 19 S29GL01GS/S29GL512S S29GL256S/S29GL128S  The Sector Addresses and Word Line Addresses are compared while the password address/data are loaded. If the Sector Address don't match than the error will be reported at the end of that write cycle. The status register will return to the ready state with the Program Status Bit set to 1, Program Status Register Bit set to 1, and Write Buffer Abort Status Bit set to 1 indicating a failed programming operation.

  • Page 20: Read Operations

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Read Operations Asynchronous Read Each read access may be made to any location in the memory (random access). Each random access is self-timed with the same latency from CE# or address to valid data (t or t Page Mode Read Each random read accesses an entire 32-byte Page in parallel.

  • Page 21: Embedded Operations

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Embedded Operations Embedded Algorithm Controller (EAC) The EAC takes commands from the host system for programming and erasing the flash memory array and performs all the complex operations needed to change the non-volatile memory state. This frees the host system from any need to manage the program and erase processes.

  • Page 22: Program And Erase Summary

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Program and Erase Summary Flash data bits are erased in parallel in a large group called a sector. The Erase operation places each data bit in the sector in the logical 1 state (High). Flash data bits may be individually programmed from the erased 1 state to the programmed logical 0 (low) state.

  • Page 23: Automatic Ecc

    S29GL01GS/S29GL512S S29GL256S/S29GL128S 5.2.2 Incremental Programming The same word location may be programmed more than once, by either the Word or Write Buffer Programming methods, to incrementally change 1’s to 0’s. Note that if additional programming is performed on a page its ECC coverage is disabled. Automatic ECC 5.3.1 ECC Overview...

  • Page 24: Command Set

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Command Set 5.4.1 Program Methods 5.4.1.1 Word Programming Word programming is used to program a single word anywhere in the main Flash Memory Array. The Word Programming command is a four-write-cycle sequence. The program command sequence is initiated by writing two unlock write cycles, followed by the program set up command.
  • Page 25 S29GL01GS/S29GL512S S29GL256S/S29GL128S 5.4.1.2 Write Buffer Programming A write buffer is used to program data within a 512-byte address range aligned on a 512-byte boundary (Line). Thus, a full Write Buffer Programming operation must be aligned on a Line boundary. Programming operations of less than a full 512 bytes may start on any word boundary but may not cross a Line boundary.
  • Page 26 S29GL01GS/S29GL512S S29GL256S/S29GL128S Figure 5.2 Write Buffer Programming Operation with Data Polling Status Write “Write to Buffer” command Sector Address Write “Word Count” to program - 1 (WC) Sector Address Write Starting Address/Data WC = 0? Write to a different Sector Address ABORT Write to Write to Buffer ABORTED.
  • Page 27 S29GL01GS/S29GL512S S29GL256S/S29GL128S Figure 5.3 Write Buffer Programming Operation with Status Register Write “Write to Buffer” command Sector Address Write “Word Count” to program - 1 (WC) Sector Address Write Starting Address/Data WC = 0? Write to a different Sector Address ABORT Write to Write to Buffer ABORTED.
  • Page 28 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 5.1 Write Buffer Programming Command Sequence Sequence Address Data Comment Issue Unlock Command 1 555/AAA Issue Unlock Command 2 2AA/555 Issue Write to Buffer Command at Sector 0025h Address Issue Number of Locations at Sector Address WC = number of words to program - 1 Example: WC of 0 = 1 words to pgm WC of 1 = 2 words to pgm Starting...
  • Page 29 S29GL01GS/S29GL512S S29GL256S/S29GL128S The system must write the Program Resume command to exit the Program Suspend mode and continue the programming operation. Further writes of the Program Resume command are ignored. Another Program Suspend command can be written after the device has resumed programming. Program operations can be interrupted as often as necessary but in order for a program operation to progress to completion there must be some periods of time between resume and the next suspend command greater than or equal to t Embedded...
  • Page 30 S29GL01GS/S29GL512S S29GL256S/S29GL128S 5.4.4.2 Sector Erase The sector erase function erases one sector in the memory array. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire sector for an all 0 data pattern prior to electrical erase.
  • Page 31 S29GL01GS/S29GL512S S29GL256S/S29GL128S 5.4.5 Erase Suspend / Erase Resume The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, the main flash array. This command is valid only during sector erase or program operation. The Erase Suspend command is ignored if written during the chip erase operation.
  • Page 32 S29GL01GS/S29GL512S S29GL256S/S29GL128S 5.4.6 ASO Entry and Exit 5.4.6.1 ID-CFI ASO The system can access the ID-CFI ASO by issuing the ID-CFI Entry command sequence during Read Mode. This entry command uses the Sector Address (SA) in the command to determine which sector will be overlaid and which sector's protection state is reported in word location 2h.
  • Page 33 S29GL01GS/S29GL512S S29GL256S/S29GL128S 5.4.6.4 Lock Register ASO The system can access the Lock Register by issuing the Lock Register entry command sequence during Read Mode. This entry command does not use a sector address from the entry command. The Lock Register appears at word location 0 in the device address space.
  • Page 34 S29GL01GS/S29GL512S S29GL256S/S29GL128S 5.4.6.8 DYB ASO The system can access the DYB ASO by issuing the DYB entry command sequence during Read Mode. This entry command does not use a sector address from the entry command. The DYB bit for a sector appears in bit 0 of all word locations in the sector. The DYB ASO allows the following activities: ...

  • Page 35: Status Monitoring

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Status Monitoring There are three methods for monitoring EA status. Previous generations of the S29GL flash family used the methods called Data Polling and Ready/Busy# (RY/BY#) Signal. These methods are still supported by the S29GL-S family. One additional method is reading the Status Register.
  • Page 36 S29GL01GS/S29GL512S S29GL256S/S29GL128S 5. Bits 5, 4, 3, and 1 are cleared to 0 by the Clear Status Register command or Reset command. 6. Upon issuing the Erase Suspend Command, the user must continue to read status until DRB becomes 1. 7.
  • Page 37 S29GL01GS/S29GL512S S29GL256S/S29GL128S Figure 5.5 Data# Polling Algorithm START Read DQ7 -DQ0 DQ7 = Data? DQ5 = 1? Read DQ 7 -DQ0 DQ7 = Data? FAIL PASS Note: 1. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5. 5.5.2.2 DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device...
  • Page 38 S29GL01GS/S29GL512S S29GL256S/S29GL128S 5.5.2.4 DQ2: Toggle Bit II Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence.
  • Page 39 S29GL01GS/S29GL512S S29GL256S/S29GL128S 5.5.2.6 DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a 1. This is a failure condition that indicates the program or erase cycle was not successfully completed. The system must issue the reset command to return the device to reading array data.
  • Page 40 S29GL01GS/S29GL512S S29GL256S/S29GL128S 5.5.2.7 DQ1: Write-to-Buffer Abort DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a 1. The system must issue the Write-to-Buffer-Abort-Reset command sequence to return the EAC to standby (Read Mode) and the Status Register failed bits are cleared.

  • Page 41: Error Types And Clearing Procedures

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Error Types and Clearing Procedures There are three types of errors reported by the embedded operation status methods. Depending on the error type, the status reported and procedure for clearing the error status is different. Following is the clearing of error status: ...
  • Page 42 S29GL01GS/S29GL512S S29GL256S/S29GL128S 5.6.2 Protection Error If an embedded algorithm attempts to change data within a protected area (program, or erase of a protected sector or OTP area) the device (EAC) goes busy for a period of 20 to 100 µs then returns to normal operation. During the busy period the RY/BY# output remains Low, data polling status continues to be overlaid on all address locations, and the status register shows not ready with invalid status bits (SR[7] = 0).
  • Page 43 S29GL01GS/S29GL512S S29GL256S/S29GL128S 5.6.3 Write Buffer Abort If an error occurs during a Write to Buffer command the device (EAC) remains busy. The RY/BY# output remains Low, data polling status continues to be overlaid on all address locations, and the status register shows ready with valid status bits. The device remains busy until the error status is detected by the host system status monitoring and the error status is cleared.

  • Page 44: Embedded Algorithm Performance Table

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Embedded Algorithm Performance Table Table 5.4 Embedded Algorithm Characteristics (-40°C to +85°C) Parameter (Note 2) (Note 3) Unit Comments Includes pre-programming Sector Erase Time 128 kbyte 1100 prior to erasure (Note 5) Single Word Programming Time (Note 1) µs 2-byte (Note 1)
  • Page 45 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 5.5 Embedded Algorithm Characteristics (-40°C to +105°C) Parameter (Note 2) (Note 3) Unit Comments Includes pre-programming Sector Erase Time 128 kbyte 1100 prior to erasure (Note 5) Single Word Programming Time (Note 1) µs 2-byte (Note 1) 1050 32-byte (Note 1)
  • Page 46 S29GL01GS/S29GL512S S29GL256S/S29GL128S 5.7.1 Command State Transitions Table 5.6 Read Command State Transition Command Software Status Status Current State Read Reset / ASO Register Register Unlock 1 Blank Check CFI Entry Condition Exit Read Enter Clear Address x555h x555h x555h (SA)555h (SA)55h Data xF0h...
  • Page 47 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 5.9 Erase Suspend State Command Transition Status Status Command and Software Reset Sector Erase Current State Read Register Read Register Unlock 1 Condition / ASO Exit Start Enter Clear Address x555h x555h x555h (SA)xh Data xF0h x70h x71h xAAh x30h...
  • Page 48 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 5.12 Erase Suspend - Program Command State Transition Erase Command Software Status Status Current Suspend ProgramSuspend Read Reset / Register Register Unlock 1 Write Data State Enhanced Enhanced Method Condition ASO Exit Read Enter Clear Method Address x555h x555h x555h...
  • Page 49 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 5.14 Program State Command Transition Program Erase Program Software Status Status Current Command Buffer to Suspend Suspend Write Read Reset / ASO Register Register Unlock 1 State and Condition flash Enhanced Enhanced Data Exit Read Enter Clear (confirm) Method Method...
  • Page 50 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 5.17 Lock Register State Command Transition Command Software Status Status Command Command PPB Lock Bit Password Current State Read Reset / ASO Register Register Set Exit Set Exit Set Entry Word Count Condition Exit Read Enter Clear Entry Address x555h...
  • Page 51 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 5.21 Secure Silicon Sector Program State Command Transition Command and Software Reset / Status Register Status Register Command Set Current State Read Unlock 1 Condition ASO Exit Read Enter Clear Exit Address x555h x555h x555h Data xF0h x70h x71h xAAh...
  • Page 52 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 5.23 Non-Volatile Protection Command State Transition Command Software Status Status Command All PPB Current Command Program DYB Set All PPB Read Reset / Register Register Set Exit Erase State Set Exit Entry Start Erase Start Condition ASO Exit Read Enter Clear Entry...
  • Page 53 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 5.26 State Transition Definitions Current State Command Transition Definition BLCK Table 5.8 Blank Check Table 5.8 Chip Erase Start Table 5.18 ID (Autoselect) CFISR Table 5.18 ID (Autoselect) - Status Register Read Table 5.25 DYB ASO DYBEXT Table 5.25 DYB ASO - Command Exit DYBSET...
  • Page 54 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 5.26 State Transition Definitions (Continued) Current State Command Transition Definition Table 5.22 Password ASO Table 5.23 PPBER Table 5.23 PPB - Erase PPBEXT Table 5.23 PPB - Command Exit PPBLB Table 5.24 PPB Lock Bit PPBLBEXT Table 5.24 PPB Lock Bit - Command Exit PPBLBSET Table 5.24...

  • Page 55: Data Integrity

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Data Integrity Erase Endurance Table 6.1 Erase Endurance Parameter Minimum Unit Program/Erase cycles per main Flash array sectors 100K P/E cycle Program/Erase cycles per PPB array or non-volatile register array 100K P/E cycle Note: 1. Each write command to a non-volatile register causes a P/E cycle on the entire non-volatile register array. OTP bits and registers internally reside in a separate array that is not P/E cycled.

  • Page 56: Software Interface Reference

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Software Interface Reference Command Summary Table 7.1 Command Definitions – Bus Cycles (Notes Command Sequence First Second Third Fourth Fifth Sixth Seventh (Note 1) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Read (Note 6) Reset/ASO Exit (Notes 7, 16)
  • Page 57 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 7.1 Command Definitions (Continued) – Bus Cycles (Notes Command Sequence First Second Third Fourth Fifth Sixth Seventh (Note 1) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Lock Register Command Set Definitions Lock Register Entry Program (Note 15)
  • Page 58 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 7.1 Command Definitions (Continued) – Bus Cycles (Notes Command Sequence First Second Third Fourth Fifth Sixth Seventh (Note 1) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data Volatile Sector Protection Command Set Definitions DYB ASO Entry DYB Set (Note 17)

  • Page 59: Device Id And Common Flash Interface (Id-Cfi) Aso Map

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Device ID and Common Flash Interface (ID-CFI) ASO Map The Device ID portion of the ASO (word locations 0h to 0Fh) provides manufacturer ID, device ID, Sector Protection State, and basic feature set information for the device. ID-CFI Location 02h displays sector protection status for the sector selected by the sector address (SA) used in the ID-CFI enter command.
  • Page 60 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 7.2 ID (Autoselect) Address Map (Continued) Description Address Read Data Bit 0 - Status Register Support 1 = Status Register Supported 0 = Status Register not supported Bit 1 - DQ polling Support 1 = DQ bits polling supported 0 = DQ bits polling not supported Lower Software Bits (SA) + 000Ch...
  • Page 61 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 7.4 CFI System Interface String Word Address Data Description (SA) + 001Bh 0027h Min. (erase/program) (D7–D4: volts, D3–D0: 100 mV) (SA) + 001Ch 0036h Max. (erase/program) (D7–D4: volts, D3–D0: 100 mV) (SA) + 001Dh 0000h Min. voltage (00h = no V pin present) (SA) + 001Eh 0000h...
  • Page 62 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 7.5 CFI Device Geometry Definition (Continued) Word Address Data Description (SA) + 0035h 0000h (SA) + 0036h 0000h Erase Block Region 3 Information (refer to CFI publication 100) (SA) + 0037h 0000h (SA) + 0038h 0000h (SA) + 0039h 0000h (SA) + 003Ah 0000h...
  • Page 63 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 7.6 CFI Primary Vendor-Specific Extended Query (Continued) Word Address Data Description Sector Protect/Unprotect Scheme 04 = High Voltage Method (SA) + 0049h 0008h 05 = Software Command Locking Method 08 = Advanced Sector Protection Method Simultaneous Operation (SA) + 004Ah 0000h 00 = Not Supported...

  • Page 64: Device Id And Common Flash Interface (Id-Cfi) Aso Map

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 7.6 CFI Primary Vendor-Specific Extended Query (Continued) Word Address Data Description (SA) + 0054h 0005h Page Size = 2 bytes (SA) + 0055h 0006h Erase Suspend Timeout Maximum < 2 (µs) (SA) + 0056h 0006h Program Suspend Timeout Maximum < 2 (µs) (SA) + 0057h FFFFh...

  • Page 65: Signal Descriptions

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Hardware Interface 8. Signal Descriptions Address and Data Configuration Address and data are connected in parallel (ADP) via separate signal inputs and I/Os. Input/Output Summary Table 8.1 I/O Summary Symbol Type Description Hardware Reset. At V , causes the device to reset control logic to its standby state, RESET# Input ready for reading array data.

  • Page 66: Versatile I/O Feature

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Versatile I/O Feature The maximum output voltage level driven by, and input levels acceptable to, the device are determined by the V power supply. This supply allows the device to drive and receive signals to and from other devices on the same bus having interface signal levels different from the device core voltage.

  • Page 67: Signal Protocols

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Signal Protocols The following sections describe the host system interface signal behavior and timing for the 29GL-S family flash devices. Interface States Table 9.1 describes the required value of each interface signal for each interface state. Table 9.1 Interface States Interface State RESET# DQ15-DQ0...

  • Page 68: Power Conservation Modes

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Power Conservation Modes 9.3.1 Interface Standby Standby is the default, low power, state for the interface while the device is not selected by the host for data transfer (CE# = High). All inputs are ignored in this state and all outputs except RY/BY# are high impedance. RY/BY# is a direct output of the EAC, not controlled by the Host Interface.

  • Page 69: Write

    S29GL01GS/S29GL512S S29GL256S/S29GL128S 9.4.3 Page Read After a Random Read access is completed, if CE# remains Low, OE# remains Low, the A to A4 address signals remain stable, and any of the A3 to A0 address signals change, a new access within the same Page begins. The Page Read completes much faster (t ) than a Random Read access.

  • Page 70: Electrical Specifications

    S29GL01GS/S29GL512S S29GL256S/S29GL128S 10. Electrical Specifications 10.1 Absolute Maximum Ratings Table 10.1 Absolute Maximum Ratings Storage Temperature Plastic Packages -65 °C to +150 °C Ambient Temperature with Power Applied -65 °C to +125 °C Voltage with Respect to Ground All pins other than RESET# (Note 1) -0.5 V to (V + 0.5 V)
  • Page 71 S29GL01GS/S29GL512S S29GL256S/S29GL128S 10.4.2 Power Supply Voltages 2.7 V to 3.6 V 1.65 V to V +200 mV Operating ranges define those limits between which the functionality of the device is guaranteed. 10.4.3 Power-Up and Power-Down  V During power-up or power-down V must always be greater than or equal to V The device ignores all inputs until a time delay of t has elapsed after the moment that V...
  • Page 72 S29GL01GS/S29GL512S S29GL256S/S29GL128S Figure 10.2 Power-down and Voltage Drop a n d V (m a x) N o D e vice A cce ss A llo w e d (m in ) F u ll D e vice V C S A ccess (m a x) L K O...

  • Page 73: Dc Characteristics

    S29GL01GS/S29GL512S S29GL256S/S29GL128S 10.5 DC Characteristics Table 10.4 DC Characteristics (–40 °C to +85 °C) Parameter Description Test Conditions Unit (Note 2) Input Load Current to V – +0.02 ±1.0 µA Output Leakage Current to V – +0.02 ±1.0 µA CE# = V , OE# = V , Address Active Read Current...
  • Page 74 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 10.5 DC Characteristics (-40°C to +105°C) Parameter Description Test Conditions Unit (Note 2) Input Load Current to V – +0.02 ±1.0 µA Output Leakage Current to V – +0.02 ±1.0 µA CE# = V , OE# = V , Address Active Read Current –...

  • Page 75: Capacitance Characteristics

    S29GL01GS/S29GL512S S29GL256S/S29GL128S 10.6 Capacitance Characteristics Table 10.6 Connector Capacitance for FBGA (LAA) Package Parameter Symbol Parameter Description Test Setup Unit Input Capacitance Output Capacitance Control Pin Capacitance RY/BY# Output Capacitance Notes: 1. Sampled, not 100% tested. 2. Test conditions T = 25 °C, f = 1.0 MHz.

  • Page 76: Timing Specifications

    S29GL01GS/S29GL512S S29GL256S/S29GL128S 11. Timing Specifications 11.1 Key to Switching Waveforms Waveform Inputs Outputs Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High Impedance State (High-Z) 11.2 AC Test Conditions Figure 11.1 Test Setup...

  • Page 77: Power-On Reset (Por) And Warm Reset

    S29GL01GS/S29GL512S S29GL256S/S29GL128S Figure 11.2 Input Waveforms and Measurement Levels Input 0.5 V Measurement Level 0.5 V Output 0.0 V 11.3 Power-On Reset (POR) and Warm Reset Normal precautions must be taken for supply decoupling to stabilize the V and V power supplies.
  • Page 78 S29GL01GS/S29GL512S S29GL256S/S29GL128S Figure 11.3 Power-Up Diagram tVCS tVIOS RESET# tCEH 11.3.2 Hardware (Warm) Reset During Hardware Reset (t ) the device will draw I current. When RESET# continues to be held at V , the device draws CMOS standby current (I ).

  • Page 79: Ac Characteristics

    S29GL01GS/S29GL512S S29GL256S/S29GL128S 11.4 AC Characteristics 11.4.1 Asynchronous Read Operations Table 11.3 Read Operation V = 2.7 V to 3.6 V (–40 °C to +85 °C) Parameter Speed Option Description Test Setup Unit JEDEC 128 Mb, 256 Mb – Read Cycle Time (Note 1) AVAV 512 Mb, 1 Gb...
  • Page 80 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 11.4 Read Operation V = 1.65 V to V = 2.7 V to 3.6 V (–40 °C to +85 °C) (Continued) Parameter Speed Options Description Test Setup Unit JEDEC Read Output Enable Hold Time Toggle and (Note 1) Data# Polling µs CE# = V...
  • Page 81 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 11.6 Read Operation V = 1.65 V to V = 2.7 V to 3.6 V (–40 °C to +105 °C) (Continued) Parameter Speed Option Description Test Setup Unit JEDEC 128 Mb, 256 Mb – Page Access Time PACC 512 Mb, 1 Gb –...
  • Page 82 S29GL01GS/S29GL512S S29GL256S/S29GL128S Figure 11.7 Page Read Timing Diagram tACC Amax-A4 A3-A0 tPACC DQ15-DQ0 Note: Word Configuration: Toggle A0, A1, A2, and A3. Document Number: 001-98285 Rev. *R Page 81 of 108...
  • Page 83 S29GL01GS/S29GL512S S29GL256S/S29GL128S 11.4.2 Asynchronous Write Operations Table 11.7 Write Operations Parameter = 2.7 V = 1.65 V Description Unit to V to V JEDEC Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Setup Time to OE# Low during toggle bit polling Address Hold Time WLAX...
  • Page 84 S29GL01GS/S29GL512S S29GL256S/S29GL128S Figure 11.9 Back to Back (CE#VIL) Write Operation Timing Diagram Amax-A0 tWPH DQ15-DQ0 Figure 11.10 Write to Read (t ) Operation Timing Diagram tSR_W tACC Amax-A0 tOEH DQ15-DQ0 Document Number: 001-98285 Rev. *R Page 83 of 108...
  • Page 85 S29GL01GS/S29GL512S S29GL256S/S29GL128S Figure 11.11 Write to Read (t ) Operation Timing Diagram tSR_W tACC Amax-A0 tOEH DQ15-DQ0 Figure 11.12 Read to Write (CE# V ) Operation Timing Diagram tACC Amax-A0 tGHWL DQ15-DQ0 Document Number: 001-98285 Rev. *R Page 84 of 108...
  • Page 86 S29GL01GS/S29GL512S S29GL256S/S29GL128S Figure 11.13 Read to Write (CE# Toggle) Operation Timing Diagram tACC Amax-A0 tGHWL DQ15-DQ0 Table 11.8 Erase/Program Operations Parameter = 2.7 V = 1.65 V Description Unit to V to V JEDEC Write Buffer Program Operation (Note 3) µs Effective Write Buffer Program Operation per Word (Note 3)
  • Page 87 S29GL01GS/S29GL512S S29GL256S/S29GL128S Figure 11.14 Program Operation Timing Diagram Program Command Sequence (last two cycles) Read Status Data (last two cycles) 555h Addresses WHWH1 Status Data BUSY RY/BY# Note: 1. PA = program address, PD = program data, D is the true data at the program address. Figure 11.15 Chip/Sector Erase Operation Timing Diagram Erase Command Sequence (last two cycles) Read Status Data (last two cycles)
  • Page 88 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 11.9 ASO Entry Timing Falling edge of CE# or address change whichever comes last ASOSTART Rising edge of CE# or Rising edge of WE# whichever comes first ASOEND 25 ns < t < 50 ns or t >...
  • Page 89 S29GL01GS/S29GL512S S29GL256S/S29GL128S Figure 11.18 Toggle Bit Timing Diagram (During Embedded Algorithms) Addresses CEPH OEPH Valid Valid Valid Valid Data DQ2 and DQ6 Valid Data Status Status Status (first read) (second read) (stops toggling) RY/BY# Note: 1. DQ6 will toggle at any read address while the device is busy. DQ2 will toggle if the address is within the actively erasing sector. Figure 11.19 DQ2 vs.
  • Page 90 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 11.10 Alternate CE# Controlled Write Operations (Continued) Parameter = 2.7 V = 1.65 V Description Unit to V to V JEDEC Read Recovery Time Before Write GHEK GHEL (OE# High to WE# Low) WE# Setup Time WLEL WE# Hold Time ELWH CE# Pulse Width...

  • Page 91: Physical Interface

    S29GL01GS/S29GL512S S29GL256S/S29GL128S 12. Physical Interface 12.1 56-pin TSOP 12.1.1 Connection Diagram Figure 12.1 56-pin Standard TSOP NC for GL256S, GL128S NC for GL128S 56-Pin TSOP NC for GL512S, GL256S, GL128S DQ15 DQ14 DQ13 DQ12 RESET# DQ11 DQ10 RY/BY# Notes: 1. Pin 28, Do Not Use (DNU), a device internal signal is connected to the package connector. The connector may be used by Cypress for test or other purposes and is not intended for connection to any host system signal.
  • Page 92 S29GL01GS/S29GL512S S29GL256S/S29GL128S 12.1.2 Physical Diagram Figure 12.2 56-pin Thin Small Outline Package (TSOP), 14 × 20 mm NOTES: PACKAGE TS 56 JEDEC MO-142 (B) EC CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm). (DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.) SYMBOL MIN. NOM.

  • Page 93: 64-Ball Fbga

    S29GL01GS/S29GL512S S29GL256S/S29GL128S 12.2 64-Ball FBGA 12.2.1 Connection Diagram Figure 12.3 64-ball Fortified Ball Grid Array TOP VIEW PRODUCT Pinout NC for GL256S, GL128S NC for GL128S NC for GL512S, GL256S, GL128S DQ15 DQ14 DQ13 RESET# DQ12 RY/BY# DQ10 DQ11 Notes: 1.
  • Page 94 S29GL01GS/S29GL512S S29GL256S/S29GL128S 12.2.2 Physical Diagram – LAE064 Figure 12.4 LAE064—64-ball Fortified Ball Grid Array (FBGA), 9 × 9 mm NOTES: PACKAGE LAE 064 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. JEDEC 2. ALL DIMENSIONS ARE IN MILLIMETERS. 9.00 mm x 9.00 mm 3.
  • Page 95 S29GL01GS/S29GL512S S29GL256S/S29GL128S 12.2.3 Physical Diagram – LAA064 NOTES: PACKAGE LAA 064 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. JEDEC 2. ALL DIMENSIONS ARE IN MILLIMETERS. 13.00 mm x 11.00 mm 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT PACKAGE AS NOTED).

  • Page 96: 56-Ball Fbga

    S29GL01GS/S29GL512S S29GL256S/S29GL128S 12.3 56-Ball FBGA 12.3.1 Connection Diagram Figure 12.5 56-ball Fortified Ball Grid Array TOP VIEW Product Pinout 512 Mb & 256 Mb Only 512 Mb Only Supports WP# only, not WP#/ACC RFU/A24 DQ15 DQ14 DQ13 DQ12 RFU/A23 RESET# RY/BY# DQ11 DQ10...

  • Page 97: Special Handling Instructions For Fbga Package

    S29GL01GS/S29GL512S S29GL256S/S29GL128S 12.3.2 Physical Diagram - VBU 056 0.10 (2X) A1 CORNER A1 CORNER INDEX MARK 56 b TOP VIEW 0.10 0.08 0.15 (2X) BOTTOM VIEW 0.10 0.08 SEATING PLANE SIDE VIEW NOTES: PACKAGE VBU 056 1. DIMENSIONING AND TOLERANCING METHODS PER JEDEC ASME Y14.5M-1994.

  • Page 98: Ordering Information

    S29GL01GS/S29GL512S S29GL256S/S29GL128S 14. Ordering Information Valid Combinations — Standard Table 14.1 lists configurations planned to be available in volume. The table will be updated as new combinations are released. Consult your local sales representative to confirm availability of specific combinations and to check on newly released combinations. Table 14.1 S29GL-S Valid Combinations —...
  • Page 99 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 14.1 S29GL-S Valid Combinations — Standard (Continued) S29GL-S Valid Combinations — Standard Ordering Part Number Packing Base OPN Speed (ns) Package and Temperature Model Number (yy = Model Number, Type x = Packing Type) S29GL128S90DHIyyx S29GL128S90FAIyyx DHI, FAI, FHI, GHI, TFI (Note 1) 01, 02 S29GL128S90FHIyyx...
  • Page 100 S29GL01GS/S29GL512S S29GL256S/S29GL128S Valid Combinations — Automotive Grade / AEC-Q100 Table 14.2 Table 14.3 list configurations that are Automotive Grade / AEC-Q100 qualified and are planned to be available in volume. The table will be updated as new combinations are released. Consult your local sales representative to confirm availability of specific combinations and to check on newly released combinations.
  • Page 101 S29GL01GS/S29GL512S S29GL256S/S29GL128S Table 14.3 S29GL-S Valid Combinations — Automotive Grade (-40 °C to +105 °C) S29GL-S Valid Combinations — Automotive Grade (-40 °C to +105 °C) Speed Package and Ordering Part Number (yy = Model Base OPN Model Number Packing Type (ns) Temperature Number, x = Packing Type)
  • Page 102 S29GL01GS/S29GL512S S29GL256S/S29GL128S The ordering part number for the General Market device is formed by a valid combination of the following: S29GL01GS Packing Type 0 = Tray 3 = 13” Tape and Reel Model Number (V and V Range) 01 = V = 2.7 to 3.6V, highest address sector protected 02 = V = 2.7 to 3.6V, lowest address sector protected...

  • Page 103: Other Resources

    S29GL01GS/S29GL512S S29GL256S/S29GL128S 15. Other Resources 15.1 Cypress Flash Memory Roadmap http://www.cypress.com/Flash-Roadmap 15.2 Links to Software http://www.cypress.com/software-and-drivers-cypress-flash-memory 15.3 Links to Application Notes http://www.cypress.com/cypressappnotes Document Number: 001-98285 Rev. *R Page 102 of 108...

  • Page 104: Revision History

    S29GL01GS/S29GL512S S29GL256S/S29GL128S 16. Revision History Document History Page Document Title: S29GL01GS/S29GL512S/S29GL256S/S29GL128S, 1-Gbit (128 Mbyte)/512-Mbit (64 Mbyte)/256-Mbit (32 Mbyte)/128-Mbit (16 Mbyte), 3.0 V, GL-S Flash Memory Document Number: 001-98285 Orig. of Submission Rev. ECN No. Description of Change Change Date – BWHA 02/11/2011 Initial release.
  • Page 105 S29GL01GS/S29GL512S S29GL256S/S29GL128S Document History Page (Continued) Document Title: S29GL01GS/S29GL512S/S29GL256S/S29GL128S, 1-Gbit (128 Mbyte)/512-Mbit (64 Mbyte)/256-Mbit (32 Mbyte)/128-Mbit (16 Mbyte), 3.0 V, GL-S Flash Memory Document Number: 001-98285 Orig. of Submission Rev. ECN No. Description of Change Change Date *B (cont) – BWHA 07/08/2011 DC Characteristics:...
  • Page 106 S29GL01GS/S29GL512S S29GL256S/S29GL128S Document History Page (Continued) Document Title: S29GL01GS/S29GL512S/S29GL256S/S29GL128S, 1-Gbit (128 Mbyte)/512-Mbit (64 Mbyte)/256-Mbit (32 Mbyte)/128-Mbit (16 Mbyte), 3.0 V, GL-S Flash Memory Document Number: 001-98285 Orig. of Submission Rev. ECN No. Description of Change Change Date – BWHA 12/21/2012 Distinctive Characteristics: Added In-Cabin temperature range Status Register ASO:...
  • Page 107 S29GL01GS/S29GL512S S29GL256S/S29GL128S Document History Page (Continued) Document Title: S29GL01GS/S29GL512S/S29GL256S/S29GL128S, 1-Gbit (128 Mbyte)/512-Mbit (64 Mbyte)/256-Mbit (32 Mbyte)/128-Mbit (16 Mbyte), 3.0 V, GL-S Flash Memory Document Number: 001-98285 Orig. of Submission Rev. ECN No. Description of Change Change Date 5162387 RYSU 03/04/2016 Updated Ordering Information on page Updated...
  • Page 108 S29GL01GS/S29GL512S S29GL256S/S29GL128S Document History Page (Continued) Document Title: S29GL01GS/S29GL512S/S29GL256S/S29GL128S, 1-Gbit (128 Mbyte)/512-Mbit (64 Mbyte)/256-Mbit (32 Mbyte)/128-Mbit (16 Mbyte), 3.0 V, GL-S Flash Memory Document Number: 001-98285 Orig. of Submission Rev. ECN No. Description of Change Change Date 5776117 SZZX 06/16/2017 Updated Software Interface Reference on page Updated...
  • Page 109 S29GL01GS/S29GL512S S29GL256S/S29GL128S Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. ® Products PSoC Solutions ®...

This manual is also suitable for:

Cypress s29gl512sCypress s29gl256sCypress s29gl128s

Table of Contents