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Summary of Contents for Achronix Speedster7t GDDR6
- Page 1 Speedster7t GDDR6 User Guide (UG091) Speedster FPGAs www.achronix.com...
- Page 2 Copyright © 2019 Achronix Semiconductor Corporation. All rights reserved. Achronix, Speedcore, Speedster, and ACE are trademarks of Achronix Semiconductor Corporation in the U.S. and/or other countries All other trademarks are the property of their respective owners. All specifications subject to change without notice.
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Page 3: Table Of Contents
Speedster7t GDDR6 User Guide (UG091) Table of Contents Chapter - 1: Introduction ............6 Features . - Page 4 Speedster7t GDDR6 User Guide (UG091) Step 4 ................. . 36 Step 5 .
- Page 5 Speedster7t GDDR6 User Guide (UG091) www.achronix.com...
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Page 6: Chapter - 1: Introduction
Speedster7t GDDR6 User Guide (UG091) Chapter - 1: Introduction The Speedster7t FPGA device family provides multiple GDDR6 subsystems that enables the user to fully utilize the high-bandwidth efficiency of these interfaces for critical applications such as high-performance compute and machine learning systems.The number of GDDR6 subsystems varies with Speedster7t device. For example, the Speedster7t1500 device provides eight GDDR6 interfaces (GDDR6 subsystems), four on the east side and four on the west side of the FPGA. -
Page 7: Architecture Overview
Speedster7t GDDR6 User Guide (UG091) Architecture Overview The diagram below shows the architecture of Achronix's 7t1500 FPGA. The eight GDDR6 subsystem are distributed four on the east and west sides each of the fabric. There are PLLs on four corners of the device that supply the external reference clock to the GDDR6 SDRAM cores and other high-speed interfaces that connect with the peripheral NoC over the FPGA fabric. -
Page 8: Gddr6 Subsystem Overview
Speedster7t GDDR6 User Guide (UG091) Figure 1: Speedster7t1500 Architecture Overview Block Diagram GDDR6 Subsystem Overview The GDDR6 subsystem provides a simple interface between off-chip GDDR6 memory component and the user logic mapped to the FPGA core. This memory subsystem comprises the PHY IP, the controller IP, clock and reset block, APB interfaces and AXI4 interfaces to connect to the NoC and fabric. - Page 9 Speedster7t GDDR6 User Guide (UG091) Figure 2: Speedster7t GDDR6 Subsystem Block Diagram The GDDR6 subsystem consists of the following functional blocks: Clock and Reset – The clock and reset block receives its input clocks from the on-chip PLLs and generates clocks to drive the GDDR6 memory controller and the PHY, with a maximum controller frequency of 1 GHz and a PHY clock frequency of 500 MHz.
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Page 10: Supported Frequency Table
Speedster7t GDDR6 User Guide (UG091) PHY IP – The GDDR6 memory PHY enables the communication between the high-speed, high-bandwidth off-chip GDDR6 memory and the controller. The PHY supports two channels, each with a data width of 16 bits and speeds up to 16 Gbps per pin, delivering a maximum bandwidth of up to 64 GBps. -
Page 11: Chapter - 2: Gddr6 Controller Architecture
Speedster7t GDDR6 User Guide (UG091) Chapter - 2: GDDR6 Controller Architecture The Speedster7t GDDR6 controller IP provides a high-performance interface to external GDDR6 SDRAM devices. The memory controller accepts read and write requests using a simple interface and translates these requests to the command sequences.The controller can automatically perform initialization and refresh functions... -
Page 12: Controller Architecture Overview
Speedster7t GDDR6 User Guide (UG091) Feature Description Data width Supports GDDR6 ×16 mode or ×8 clamshell modes. Write masks Supports write single-mask and write double-mask operations. Supports GDDR6 data bus inversion (DBI) and CA bus inversion (CABI). inversion Refresh Per-bank and all-bank refresh support. -
Page 13: Modes Of Operation
APB slaves are connected by CSR signals. The last APB slave is connected to IPCNTL components. Modes of Operation The Speedster7t GDDR6 controller supports two read/write channels, each with an independent memory controller. The GDDR6 subsystem supports the following two modes:... -
Page 14: By 16 Mode
Speedster7t GDDR6 User Guide (UG091) By 16 Mode In this mode each controller provides an interface to a single 16-bit memory channel. A block diagram of the dual- controller system using a single memory device in ×16 mode is shown below: Figure 4: Dual-Controller ×16 Mode Block Diagram... -
Page 15: Chapter - 3: Gddr6 Phy Architecture
Chapter - 3: GDDR6 PHY Architecture PHY Overview The embedded Speedster7t GDDR6 PHY supports the GDDR6 memory standard at the channel interface and DFI-4.0 interface on the FPGA side with the memory controller. It supports a maximum data rate of 16 Gbps and is targeted for systems that require low-latency and high-bandwidth memory solutions. -
Page 16: Phy Features
Speedster7t GDDR6 User Guide (UG091) PHY Features Table 3: Speedster7t GDDR6 PHY Features Feature Description DRAM density SDRAM Density up to 16 Gb per component supported. DRAM speeds The 7t1500 supports 12 Gbps, 14 Gbps and 16 Gbps data rates. -
Page 17: Phy Architecture
Speedster7t GDDR6 User Guide (UG091) PHY Architecture The PHY consists of the command/address (CA) block, DQ byte blocks, PLLs and the global logic block. There are three PLLs present in the entire PHY: one for the CA block and one for each of the two DQ words. - Page 18 Speedster7t GDDR6 User Guide (UG091) Figure 7: High-Level PHY I/O Block Diagram www.achronix.com...
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Page 19: Chapter - 4: Gddr6 Clock And Reset Architecture
Chapter - 4: GDDR6 Clock and Reset Architecture The Speedster7t GDDR6 subsystem has 32 global clocks where the selection of clocks are configurable through IPCNTL registers. These global clocks are generated from two PLLs, each generating 16 clock outs. There are two 32×1 clock multiplexer implemented whose selection is driven by IPCNTL registers. - Page 20 Speedster7t GDDR6 User Guide (UG091) Figure 9: External Clock to South PLLs Driving the GDDR East/West Subsystems on the AC7t1500 device Figure 10: External Clock to North PLLs Driving the GDDR East/West Subsystems on the AC7t1500 device www.achronix.com...
- Page 21 Speedster7t GDDR6 User Guide (UG091) Figure 11: South PLLs Driving Some of the GDDR East/West Subsystems and the North PLLs on the AC7t1500 device Figure 12: North PLLs Driving Some of the GDDR East/West Subsystems and the South PLLs on the AC7t1500 device...
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Page 22: Chapter - 5: Gddr6 Interface Connectivity
GDDR6, DDR4/5, 400G Ethernet, and PCI Express Gen5 data streams, while greatly simplifying access to memory and high-speed protocols. Achronix's network on chip (NoC) provides for read/write transactions throughout the device, as well as specialized support for 400G Ethernet streams in selected columns. - Page 23 Speedster7t GDDR6 User Guide (UG091) Figure 13: AXI4-256b I/O Diagram The following table provides the parameters to be given to the AXI4 Interface: Table 4: AXI4-256b Interface Signals Parameter Value Description AXI_DATA_WIDTH Data width of AXI4 interface AXI_SLAVE_ID_WIDTH Width of awid, wid, bid, arid, rid ports Sets the depth of the read and write command FIFOs.
- Page 24 Speedster7t GDDR6 User Guide (UG091) Parameter Value Description If set in this mode, requests within a port as well as requests across different ports may be reordered. When intra-port reordering is enabled, data may be written to or read from the memory devices in an order different from how they are issued by the AXI4 interface.
- Page 25 Speedster7t GDDR6 User Guide (UG091) The figure below shows PCI Express master issues a transaction to the NoC, which transmits it directly to the GDDR6 interface without involving any resources in the FPGA fabric at all. Figure 14: Data Flow from the PCIe Interface to GDDR6 Subsystem Through the...
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Page 26: Connectivity Through The Beachfront
Speedster7t GDDR6 User Guide (UG091) The following figure shows how the master logic in the FPGA fabric interacts with the GDDR6 interface utilizing the NoC. Figure 15: Data Flow from the FPGA Fabric to the GDDR6 Subsystem Through the Connectivity Through the Beachfront There are only four GDDR6 subsystems, the middle two, on the east and west sides of the chip that enable the beachfront interface connection directly to the fabric. - Page 27 Speedster7t GDDR6 User Guide (UG091) Figure 16: AXI4-512b I/O Diagram The following table provides the parameters to be given to the AXI4 Interface. Table 5: AXI4-512b Interface Signals Parameter Value Description AXI_DATA_WIDTH Data width of the AXI4 interface AXI_SLAVE_ID_WIDTH Width of awid, wid, bid, arid, rid ports.
- Page 28 Speedster7t GDDR6 User Guide (UG091) Parameter Value Description If set to this mode, requests within a port as well as requests across different ports may be reordered. When intra-port reordering is enabled, data may be written to or read from the memory devices in an order different from how they are issued by the AXI4 interface.
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Page 29: Chapter - 6: Gddr6 Core And Interface Signals
Speedster7t GDDR6 User Guide (UG091) Chapter - 6: GDDR6 Core and Interface Signals This section provides a detailed list of all the signals that interface with each GDDR6 subsystem. The following table summarizes the different clock and reset signals the connect to the PHY and controllers inside the GDDR6 subsystem. - Page 30 Speedster7t GDDR6 User Guide (UG091) Pin Name Direction Width Description Input signal to set the burst size. This signal indicates the size of gddr6_*_chan0/1_awsize Input each transfer in the burst. Input signal to set the burst type. The burst type and the size...
- Page 31 Speedster7t GDDR6 User Guide (UG091) Pin Name Direction Width Description gddr6_*_chan0/1_bvalid Output Indicates that the write response channel signals are valid. Indicates that a transfer on the write response channel can be gddr6_*_chan0/1_bready Input accepted. gddr6_*_chan0/1_arid Input Input signal to set the identification tag for a read transaction.
- Page 32 Speedster7t GDDR6 User Guide (UG091) Pin Name Direction Width Description This signal indicates that a transfer on the read data channel can gddr6_*_chan0/1_rready Input be accepted. The table below summarizes the external memory to PHY interface signals. Table 9: Memory to PHY Interface Signals...
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Page 33: Chapter - 7: Gddr6 Ip Software Support In Ace
Speedster7t GDDR6 User Guide (UG091) Chapter - 7: GDDR6 IP Software Support in ACE Overview The GDDR6 IP generation in ACE provides a GUI-based interface to generate and integrate the GDDR6 subsystem instances based on the user specified inputs. The I/O Designer in ACE supports the integration of all the chosen IP for the user design and also allows the user to select the placement and visualize package routing. -
Page 34: Step 2
Speedster7t GDDR6 User Guide (UG091) Step 2 Switch to the 'IP Configuration' perspective and select GPIO IP to create the external input clock source. Then select the ball placement and desired frequency for the GPIO. Once the selection is made, the Layout Diagram highlights the chosen clock input. -
Page 35: Step 3
Speedster7t GDDR6 User Guide (UG091) Step 3 Next, configure the PLL IP with the desired placement and appropriate clock output frequencies based on the data rate user chooses for the GDDR6 interface. The GDDR6 IP requires a GDDR6 reference clock for the controller and PHY operations, and if the GDDR6 subsystem uses the beachfront interface, then the PLL output needs to supply the beachfront AXI clock. - Page 36 Speedster7t GDDR6 User Guide (UG091) Step 4 If the GDDR subsystem also interfaces with the NoC, then the user also must instantiate NoC IP with the appropriate clock setting. The global clock output of the PLL should drive the NoC interface.
- Page 37 Speedster7t GDDR6 User Guide (UG091) Step 5 Next, the user must configure the GDDR6 subsystem interface. Select the desired placement for the interface along with the memory part number, data rate and mode of operation. The GDDR6 clock settings will show the available valid clock input selections for the GDDR6 reference clock, the beachfront AXI clock and the NoC clock based on the clock outputs from the PLL.
- Page 38 Speedster7t GDDR6 User Guide (UG091) Figure 22: Cloning an Existing GDDR6 Subsystem Step 6 After all the configuration options are selected, the 'IP Problems' window reports any errors or warnings that occurred with the configuration. If there are no errors or warnings reported, the user can be assured that the entire I/O interface with all the required IP are integrated properly and will close timing at the required clock frequency.
- Page 39 Speedster7t GDDR6 User Guide (UG091) Revision History Version Date Description 11 Oct 2019 Initial release. Save Save Save Save Save www.achronix.com...