Summary of Contents for Aniotek UFC100-L2
- Page 1 Aniotek Inc. NIFIED IELDBUS ONTROLLER UFC100-L2 ASIC ’ ANUAL...
- Page 2 The product described in this document is meant for commercial and industrial applications and it is not meant for military, space, medical or life-sustaining equipment. Aniotek Inc. does not make any warranty of fitness or suitability of this product for any purpose. Aniotek Inc.
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Page 3: Table Of Contents
Power PC ............................22 MAU I ...........................23 NTERFACE 3.3.1 Transmitter Interface ........................23 3.3.2 Receiver Interface ..........................23 ..........................25 THER NTERFACES 3.4.1 Reset and Interrupt Signals ......................25 ELECTRICAL AND TEMPERATURE SPECIFICATIONS ..............26 21 May 2018 Rev. 1.0 Proprietary and confidential information of Aniotek Inc. - Page 4 Using DMA Write to the Transmit FIFO ..................38 ..........................38 RAME RECEPTION 2.4.1 Using non-DMA access to the FIFO ....................38 2.4.2 Using DMA access to the FIFO ......................39 ............................39 ATCH TIMER ............................39 OKEN TIMER 21 May 2018 Rev. 1.0 Proprietary and confidential information of Aniotek Inc.
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Page 5: Introduction
Page 1 NTRODUCTION The UFC100-L2 (Unified Fieldbus Controller) is a peripheral that that can be used in a Fieldbus Device or Host to provide a complete solution for implementing Fieldbus equipment. The UFC100-L2 includes all of time-critical functions in the hardware. -
Page 6: Applications
Unified Fieldbus Controller in LQFP package Order number of UFC100-L2: IFL-KK-02091 Changes between UFC100-L1 and UFC100-L2 The UFC100-L2 has function, package and pins same as UFC100-L1, except in L2 the following pins are not 5 V tolerant. Signal RESETn FLT0n... - Page 7 Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 3 Table 1: UFC100-L2 Pin out Name Type Reset Description value 1 A4 CPU Address bus 2 RDn/EDSn Read Strobe (Intel mode), E or DSn (Freescale mode) Write Strobe (Intel mode), RWn – Read or Write select (Freescale...
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Page 8: Basic Mode Operation
CPU Bus Interface The UFC100-L2 can be connected to any synchronous or asynchronous bus. The type of CPU can be Intel or Freescale. The selection is done by two input pins. The data interface is 8-bit wide; the address bus is 5-bit wide. -
Page 9: Basic Mode Registers
(1): Unused registers read as 0x00. 2.2.2 Performance Improvement Even with existing software, UFC100-L2 reduces the number of the interrupts to the CPU and thus provides performance improvement. There is filter on bus activity to make it less sensitive to noise. 21 May 2018 Rev. -
Page 10: Reset, Version
Soft Reset Writing ‘1’ to this field applies reset to all parts of the UFC100-L2. It may take up to 4 cycles of input clock to complete the reset operation. If the CPU does not use RDY signal, then it should check ARDY field in Status register – see 2.2.6, before starting the next Read or Write cycle from the CPU. -
Page 11: Control
Receiver enable If this field is set to ‘1’then the Receiver is enabled, else the UFC100-L2 ignores the receive activity. If ‘RE’ is reset to ‘0’ while a reception is active, then it cancels that reception and resets the Receiver. -
Page 12: Status
Writing ‘1’ to this field starts a transmission, which ends after sending the End Delimiter. This field is reset to ‘0’ by the UFC100-L2 at the end of the transmission. If the CPU resets this field to ‘0’ during an active transmission, then the transmission is aborted by sending the current byte, followed by wrong (inverted) FCS followed by End Delimiter and the CPU attempt to write to the FIFO is ignored until the CPU resets transmission error status or TED status field. -
Page 13: Error Status
Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 9 Table 8: UFC Interrupt status register Interrupt status Bit no. Name Not used Error condition This field is inclusive OR of all unmasked fields in the Error status register. Watch-timer interrupt This field is set to ‘1’... -
Page 14: Interrupt Mask
Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 10 Table 9: UFC Error status register Error status Bit no. Name FFER FCSE Not used NEPT FFER FIFO error This field is ‘1’ when any error field in FIFO (RFOR, RFUR, TFOR or TFUR fields in FIFO Status register) is ‘1’. -
Page 15: Error Mask
Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 11 Table 10: UFC Interrupt mask register Interrupt mask Bit no. Name Not used 2.2.10 Error mask Address: 0x07 Reset value: 0xFB This register controls error interrupts specified in Error status register in the same order of error reasons. When a field of this register is set to ‘1’, then the corresponding error in Error status register is masked (does not affect the ERS bit in the... -
Page 16: Fifo Control Register
Clear Transmit FIFO Writing ‘1’ to this field clears the Transmit FIFO, its error status and the FIFO becomes empty. It also resets Transmit length register to zero. This field is automatically reset to ‘0’ by the UFC100-L2. TCTRL Transmit FIFO threshold The value of this field sets the FIFO threshold that is used to set TFI field –... -
Page 17: Fifo Status
Transmit FIFO underrun This field is set to ‘1’ when the Transmit FIFO is empty and the UFC100-L2 tries to read another byte from the Transmit FIFO to transmit the frame, or if the transmission is started and Transmit length register is zero. This field is reset to ‘0’... -
Page 18: Clock Mode
Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 14 2.2.15 Clock mode Address: 0x10 Reset value: 0x00 This register can be written and read. Table 14: Clock mode register Clock mode Bit no. Name 7 – 3 Not used... -
Page 19: Gap Time
These registers are used to read the value from or write the value to the internal Token-time counter. The internal counter is a 16-bit down counter. It is reset to zero at the start of UFC100-L2 operation. Whenever it has non-zero value, it counts down once every byte time –... - Page 20 Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 16 Latch Token-timer Writing ‘1’ to this field snaps the value of the internal Token-time counter into Token counter register – address 0x18, 0x19. Clear Watch-timer Writing ‘1’ to this field clears the internal Watch-time counter to zero.
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Page 21: External Interfaces
3. If the CPU uses a bus that runs at a higher clock rate than CLKIN input of UFC100-L2 and if the CPU cannot use ‘RDY / DACKn’ signal and if the CPU cannot insert enough wait states, then it has to use software to poll a status bit (ARDY) inside UFC100-L2. -
Page 22: Renesas Cpu With Rdy
Figure 2: Interface to Renesas M16 using Multiplexed Bus This type of interface requires separate Read and Write control signals. The UFC100-L2 provides RDY signal, which is normally high. It may become low at the start of the Read or Write cycle to indicate that the CPU has to wait. It becomes high when the CPU can complete the cycle. - Page 23 Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 19 M16C UFC100-L1 BCLK CLKIN CTYP A5, A6 can be connected to Vss. ATYP A6…A0 RES0 RES1 Connection RES2 D7…D0 TxRn /CSx TxEn /INTx INTn /INT0 FLT0n FLT1n RESETn PORT /RESET...
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Page 24: Intel X86 Type Cpu With /Ready
Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 20 3.2.2 Intel X86 Type CPU with /READY UFC100-L1 BCLK CLKIN CTYP A5, A6 can be connected to Vss. ATYP A6…A0 RES0 RES1 Connection RES2 D7…D0 TxRn /CSx TxEn /READY DACKn... -
Page 25: Freescale Type Cpu With /Dtack, Existing Design
Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 21 3.2.3 Freescale Type CPU with /DTACK, Existing Design MC68XXX UFC100-L1 CLKOUT CLKIN CTYP ATYP A6…A0 RES0 RES1 Connection RES2 D7…D0 TxRn /CSx TxEn /DTACK Logic /INTx INTn DMARQ FLT0n FLT1n... -
Page 26: Freescale Type Cpu With /Dtack, New Design
Figure 6: Interface to Freescale MC683XX, MC68C16 – new designs This type of interface requires a common data strobe and another signal for Read, Write control. The UFC100-L2 provides a DACKn signal, which is normally high. It becomes low towards the end of a Read or Write cycle to indicate to the CPU that it can complete the cycle. -
Page 27: Mau Interface
Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 23 MAU Interface This interface consists of four signals – TxEn, TxS, TxRn and TxA for Transmitter and two signals – RxA and RxS for Receiver. These MAU signals are specified in 3.3.1 and 3.3.2. - Page 28 Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 24 Noise Signal Upper threshold Signal on the line Lower threshold Active Inactive RxA – Level High RxS – input signal Figure 7: Carrier Detect (RxA) and Signal (RxS) inputs RxS signal should be generated by comparing the analog received signal with zero and thus it can become active due to noise as shown in the Figure 7.
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Page 29: Other Interfaces
This output becomes active when it needs to interrupt the CPU. The active polarity is low. This signal stays active as long as any one of the interrupt sources in the UFC100-L2 is active. The reset signal should be applied as soon as possible after the power is applied. The clock can become active after reset signal is applied. -
Page 30: Electrical And Temperature Specifications
Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 26 LECTRICAL AND EMPERATURE PECIFICATIONS Absolute Maximum Ratings Symbol Parameter Units – 0.3 V DD Supply Voltage – 0.3 DC Input Voltage V DD + 0.3 – 0.3 DC Output Voltage V DD + 0.3... -
Page 31: Current Consumption
Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 27 4.2.1 Current Consumption The typical operating current for most applications is less than 1 mA. The current consumption is shown in the Figure 8 and Figure 9 below. It was measured while the device was continuously transmitting and receiving in full duplex using DMA, with continuous Read and Write access to the device. -
Page 32: Clock Input Timings
Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 28 Clock Input Timings The timings are shown in the Table 21 and the Figure 10. Table 21: Clock Timings Name Description Clock input period @ V DD = 2.7 to 3.6 V... -
Page 33: Cpu Bus Access Timings
Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 29 CPU Bus Access Timings The timing diagrams are shown for Read and Write access for all types of CPU. The CPU interface is asynchronous to CLKIN. However, internally the bus access is synchronized to CLKIN, for all Write accesses and for those Read accesses (FIFO, interrupt status, error status) that cause a Write. - Page 34 Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 30 Table 22: Bus Timings for Intel type CPU Description Notes Valid Address to RDn, WRn assertion (setup time) RDn, WRn assertion to invalid Address (hold time) CSn assertion to RDn, WRn assertion setup time...
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Page 35: Freescale Type Cpu
Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 31 4.4.2 Freescale Type CPU ADRS DSn or ASn DACKn DATA Figure 13: Freescale Bus Read Cycle Timing Diagram ADRS DSn or ASn DACKn DATA Figure 14: Freescale Bus Write Cycle Timing Diagram 21 May 2018 Rev. -
Page 36: Dma Request Timings
Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 32 Table 23: Bus Timings for Freescale type CPU Description Notes Valid Address to DSn assertion (setup time) DSn assertion to invalid Address (hold time) CSn assertion to DSn assertion setup time... -
Page 37: Mau Interface Timings
Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 33 MAU Interface Timings The timings are shown in the Table 25 and the Figure 16 – Figure 18. The timings for output signals are specified for a 50 pf load. -
Page 38: Other Timings
Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 34 Preamble Start Delimiter Level High LOCK End Delimiter Level High RxAH Figure 18: MAU Interface Receiver Timings Other Timings 4.6.1 Reset Timings Table 26: Reset Timings Description Notes Reset active duration after the active clock... - Page 39 Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 35 2. If end delimiter is not detected and RxA becomes inactive, then this delay is from the end of activity. If DMA is enabled, then the interrupt becomes active only after the receive FIFO becomes empty. The last received byte is available for transfer at the start of end delimiter.
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Page 40: Package
Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 36 ACKAGE UFC100-L2 is available in 44 pin RoHS certified LQFP package. The dimensions are shown in Figure 22. Figure 22: LQFP package dimensions Table 28: LQFP package dimensions Symbol MILLIMETER INCH 1.60... -
Page 41: Test Procedures
If the hardware interface to the CPU uses RDY signal, then the registers can be accessed as memory locations. If the RDY is not used, but Read and Write cycles are at least 4 cycles of the CLKIN input to the UFC100-L2, the registers can be accessed as memory locations. -
Page 42: Using Dma Write To The Transmit Fifo
UFC waits until RxA becomes ‘0’ before starting the transmission. Since the MAU itself receives the transmitted signal, the RxA input to the UFC100-L2 should be ‘1’ during the transmission after a delay. If RxA remain ‘0’ during the transmission then it is considered an error, CNS in Error status register is set to ‘1’ and the transmission is aborted. -
Page 43: Using Dma Access To The Fifo
Unified Fieldbus Controller UFC100-L2 – Basic mode operation Page 39 9. If there was an error then first read FIFO status register (0x0C) and then Error status register (0x05) to find the reason for the error. Clear the FIFO status register by writing ‘1’ to CRF and CTF in FIFO control register (0x0B).
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