Related Manuals for WRS PAK68/3
Summary of Contents for WRS PAK68/3
- Page 1 Processor Replacement Card, Version 3 CPU Accelerator for the Atari ST(E) Series © 2003 WRS Software-Design, Humboldtstrasse 12, 45886 Gelsenkirchen...
- Page 2 CPU Accelerator for the Atari ST(E) Series Developer: Holger Zimmermann Copyright © 2003 WRS Software-Design All Rights Reserved. The copyright to the hardware extension PAK68/3, including the GAL equations, lies with the developers. Reproduction is permitted for private use only! Distributor/Supplier: WRS Software-Design W.
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Page 3: Table Of Contents
Table of Contents Table of Contents Before Starting Notes Delivery Options Requirements Features of the PAK68/3-030 Building the PAK68/3 Prerequisites Clock Buffering – Part 1 The Construction Installing the PAK68/3 Preparing the Mainboard Preparing the PAK Installing the PAK Initial Testing... -
Page 4: Before Starting
The PAK68/3 was first introduced in the magazine c’t. If you would like to read the articles they were in the 11/93 issue page 222 and the 12/93 issue page 276. - Page 5 GAL). When the PAK is used with a MegaSTE make sure to set the processor clock to 8MHz and turn off the board cache (remember to save the settings) otherwise the PAK will not work. PAK68/3 Page 4...
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Page 6: Features Of The Pak68/3-030
Unfortunately, some graphics adapters can cause problems. Candidates for this are the NOVA adapters, the VOFA and the Multiboard. More on this later. 1.4 Features of the PAK68/3-030 68030 processor, 32-bit instruction and data cache on-chip, PMMU 68881/882 FPU (optional) ... -
Page 7: Clock Buffering - Part
Clock Buffering - Permanently Soldered If you will use the PAK long-term without equipping a FRAK/? Then we generally recommend clock buffering for the PAK above 32MHz and always with a FPU (at 50MHz it is PAK68/3 Page 6... -
Page 8: The Construction
10 ohms instead of 33 ohms. For R48 use 68 ohms and for C43 use 220pF (between GAL sockets) Also, in this case, the solder bridge between R47 and the oscillator on the bottom must remain open. Page 7 PAK68/3... -
Page 9: Installing The Pak68/3
The PAK should now be soldered except for any possible wires or cabling. We are moving closer to the installation in Chapter 3. 3. Installing the PAK68/3 3.1 Preparing the Mainboard To start with: The ideal target system for a PAK is a MegaST. - Page 10 RAM on the mainboard then you should bridge the built-in Atari choke which seperates the RAM-Vcc section of the mainboard from the rest. Page 9 PAK68/3...
- Page 11 2. From the chip it goes to a 10k resistor and the choke, which then leads to the keyboard jack. The 10k resistor goes to ground on the other side. Disconnect that side from the mainboard and connect it to +5V. PAK68/3 Page 10...
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Page 12: Preparing The Pak
1 has a square pad. For the CPU and FPU, pin 1 is usually indicated by a golden mark on the top (always on a corner). When inserting the GALs, please follow the instructions in Chapter 4.1. Page PAK68/3... -
Page 13: Installing The Pak
Now you can, for example, test the system speed with the benchmark programs on the included floppy disk. If the PAK won't run right away it doesn't necessarily mean there is a hardware fault. In this case, see Chapter 5 for a checklist. PAK68/3 Page 12... -
Page 14: Configuring The Pak68/3
We recommend using the latest version of HDDriver from Uwe Seimet. 4. Configuring the PAK68/3 4.1 The GAL Set The flow control of the PAK is performed by five 20v8 GALs. So "intelligence"... -
Page 15: The Jumpers
FPU should not run slower than the CPU) 1-2=via MMU J11 Cache-Control 2-3=reserved, not used open=SLC always on Remarks: Standard in this Notation Pin 1 on 3-pin jumpers has a square pad enabled = activated, disabled = deactivated PAK68/3 Page 14... -
Page 16: The Tos
(www.wrsonline.de). If you need help in this regard, please contact us directly. The following country-specific adaptations of PAK-TOS are currently available: German (GER) American (USA) English (UK) French (FRA) Page 15 PAK68/3... - Page 17 PAK was originally designed for 32MHz operation, the first version of the PAK was not designed with optional clock buffering and termination (the 50MHz speed madness came later. Also FPUs were expensive and very rare at that time). PAK68/3 Page...
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Page 18: Pak And 68000: Alternate Operating Mode
(at least 100MHz oscilloscope) and quite a lot of expertise. However, an adjustment should be so rare that we do not want to get into the details here. 4.5 PAK and 68000: Alternate Operating Mode Page 17 PAK68/3... -
Page 19: Pak With Mainboard Clock Greater Than 8Mhz
R43 so that the clock halves are again about the same size. Unfortunately, this sounds easier than it is in practice and it requires at least a 100MHz oscilloscope to observe the double mainboard clock with sufficient accuracy. PAK68/3 Page 18... -
Page 20: Pak And Pupla
CPU is already warm enough. More information can be found at our website (www.wrsonline.de) or directly from us. 5. Troubleshooting The PAK is not a real plug&play system. Unfortunately some things have to be optimized or retrofitted by hand. Page 19 PAK68/3... -
Page 21: Startup Problems
1k reset pull-up (see above) Clock line terminated correctly? Check TOS on the PAK and on the mainboard 5.2 Stability Problems There are three main reasons for stability problems: 1. Contact Problems PAK68/3 Page 20... -
Page 22: Dma/Floppy Problems
Another reason for DMA problems (hard disk/floppy problems) can be an inaccurate clock. Most of the time these problems are related to two bombs on hard disk accesses. See Chapter 4.4. DMA problems have also been observed in non-current Page 21 PAK68/3... -
Page 23: Additional Extensions
PAK. The problem usually lies with the extension itself and not the PAK. Most extensions expect the bus timing to be set for a normal 8MHz 68000 system and cannot handle the much faster PAK. PAK68/3 Page 22... - Page 24 PAK. This should reveal which extension is causing the problem. Exceptions to this are extensions that do not depend on the bus system so, for example, a HD module or a serial interface upgrade shouldn't have any impact. Page 24 PAK68/3...
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Page 25: Appendix A Component Layout
Appendix A – Component Layout Appendix A – Component Layout PAK68/3 Page 24... -
Page 26: B Parts List
5 Pin Header, 3pin CON1 1 SIL Socket 19pin 2 SIL Plug-In Adapter 32pin (mainboard) CON2 Connector) Attention! CON2 are the "inner" pads ST1 (U7) 2 SIL Socket 32pin (68000 socket) Attention! ST1 are the "outer" pads Page 25 PAK68/3... -
Page 27: Ctos Rom Table
the PUK-GAL (U3) is already fully wired, but with a different pin configuration (P3-PUK-A) optional clock buffering, see Chapter 4.4 Appendix C – TOS ROM Table Byte assignment for a TOS longword: PAK68/3 PAK68/2 WRS D24 - D31 D16 - D23 D8 - D15 D0 - D7...
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