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Jumper Pin Location
The jumpers on boards start with Pin 1 on the leftmost side
of the pin. Grouped jumpers increase in pin size with each
jumper added.
Figure 5. Pin Locations for a Single Jumper. Pin 1 is Located at the Leftmost Side
Jumper/Header Functions & Default Positions
The P1 jumper/header configuration allows mode
selection to the Demo 2× Board. The 2−3 default jumper
position puts the Demo 2× in power safe mode, while the 1−2
jumper position puts the Demo 2× in Forced PWM mode.
The P5 jumper/header configuration allows for VDDIO
selection to the Demo 2× Board. The 2−3 default jumper
position connects VDDIO to +1.8 V, while the 1−2 jumper
position connects VDDIO to +2.8 V.
Table 1. 26-PIN DEMO 2X BASEBOARD CONNECTOR FUNCTION DESCRIPTION (P3)
Pin
Name
1
S_DATA8
2
S_DATA9
3
S_DATA10
4
S_DATA11
5
S_DATA12
6
S_DATA13
7
S_DATA14
8
S_DATA15
9
S_DATA6
10
S_DATA7
11
GND
12
GND
13
S_LINE_VALID
14
S_SP5
15
NOT USED
16
HEAD_RESET_L
17
S_FRAME_VALID
18
HEAD_SDA
19
HEAD_SCL
20
NOT USED
21
+5V0_HEAD
22
+5V0_HEAD
23
S_PIXCLK
24
GND
25
GND
26
MCLK
AGB3N0CS−GEVK
Pin 1
Description
Parallel Data8
Parallel Data9
Parallel Data10
Parallel Data11
Parallel Data12
Parallel Data13
Parallel Data14
Parallel Data15
Parallel Data6
Parallel Data7
Ground
Ground
Parallel Line Valid
General Control Signal 5
Not Used
Reset Signal to Sensor
Parallel Frame Valid
2
I
C Data to Sensor
2
I
C Clock to Sensor
Not Used
+5V0 Power Input
+5V0 Power Input
Parallel Pixel Clock
Ground
Ground
Master Clock
www.onsemi.com
Pins 1−4
AGB3N0CS−GEVK Connectors
The adapter board supports has various different
connectors on-board, including a Demo 3 Headboard
connector, two MIPI/HiSPi connectors for the Demo 2×
Board, the 13-pin Demo 2× Board connector, and 26-pin
Demo 2× Board connector.
Baseboard Connectors
The Demo 2× Baseboard connectors are shown in the
pinout in Tables 1 and 2. The Demo 2× connectors has
a 14-pin and 26-pin connector, as well as two MIPI/HiSPi
connectors.
DIR
I/O
Parallel Data Bit
I/O
Parallel Data Bit
I/O
Parallel Data Bit
I/O
Parallel Data Bit
I/O
Parallel Data Bit
I/O
Parallel Data Bit
I/O
Parallel Data Bit
I/O
Parallel Data Bit
I/O
Parallel Data Bit
I/O
Parallel Data Bit
PWR
PWR
Out
Check Line Valid Signal
Out
Signal @ +3.3 V Level
NA
In
Reset to Headboard Sensor
Out
Check Frame Valid Signal
I/O
Signal @ +3.3 V Level
I/O
Signal @ +3.3 V Level
NA
PWR
For Powering Up the Headboard
PWR
For Powering Up the Headboard
In
Parallel Data Pixel Clock
PWR
PWR
In
Master Clock from Demo 3 Board
3
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